From 6f5a1e946eb2838e4ba77ea0530e7b3df23b9f6e Mon Sep 17 00:00:00 2001
From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Mon, 25 Apr 2022 23:00:28 +0200
Subject: [PATCH] placing test point

---
 special/clockbox.vhd | 61 ++++++++++++++++++++++++++++++++++++++++++++
 special/ddmtd.vhd    | 14 +++-------
 2 files changed, 65 insertions(+), 10 deletions(-)
 create mode 100644 special/clockbox.vhd

diff --git a/special/clockbox.vhd b/special/clockbox.vhd
new file mode 100644
index 0000000..6c6f4d1
--- /dev/null
+++ b/special/clockbox.vhd
@@ -0,0 +1,61 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity clockbox is
+  port(
+    SAMPLE_CLK    : in  std_logic;
+    PING_IN       : in  std_logic; -- TX K
+    CLK_PING      : in  std_logic; -- TX CLK
+    PONG_IN       : in  std_logic; -- RX K
+    CLK_PONG      : in  std_logic; -- RX CLK
+    PING_OUT      : out std_logic;
+    PONG_OUT      : out std_logic
+  );
+end entity clockbox;
+
+architecture clockbox_arch of clockbox is
+
+-- Components
+
+-- state machine signals
+
+-- Signals
+  signal ping_i         : std_logic;
+  signal pong_i         : std_logic;
+  signal ping_q         : std_logic;
+  signal pong_q         : std_logic;
+  signal ping_qq        : std_logic;
+  signal pong_qq        : std_logic;
+
+  attribute HGROUP : string;
+  attribute BBOX   : string;
+  attribute HGROUP of clockbox_arch : architecture is "clockbox_group";
+  attribute BBOX   of clockbox_arch : architecture is "1,2";
+  attribute syn_sharing : string;
+  attribute syn_sharing of clockbox_arch : architecture is "off";
+  attribute syn_hier : string;
+  attribute syn_hier of clockbox_arch : architecture is "hard";
+  
+begin
+
+---------------------------------------------------------------------------
+-- we want all logic in here in one PFU (defined timing)!
+---------------------------------------------------------------------------
+
+  ping_i  <= PING_IN when rising_edge(CLK_PING);
+  pong_i  <= PONG_IN when rising_edge(CLK_PONG);
+  ping_q  <= ping_i when rising_edge(SAMPLE_CLK);
+  pong_q  <= pong_i when rising_edge(SAMPLE_CLK);
+  ping_qq <= ping_q when rising_edge(SAMPLE_CLK);
+  pong_qq <= pong_q when rising_edge(SAMPLE_CLK);
+  
+---------------------------------------------------------------------------
+-- outputs
+---------------------------------------------------------------------------
+  PING_OUT <= ping_qq;
+  PONG_OUT <= pong_qq;
+
+end architecture;
diff --git a/special/ddmtd.vhd b/special/ddmtd.vhd
index 0e8b60d..39dc808 100644
--- a/special/ddmtd.vhd
+++ b/special/ddmtd.vhd
@@ -39,8 +39,6 @@ architecture ddmtd_arch of ddmtd is
   );
   end component deglitch;
 
-  signal ping_q        : std_logic_vector(2 downto 0);
-  signal pong_q        : std_logic_vector(2 downto 0);
   signal toggle_q      : std_logic;
   signal start_ping_i  : std_logic;
   signal start_pong_i  : std_logic;
@@ -67,10 +65,6 @@ begin
 THE_SAMPLER_PROC: process( AUXCLK )
 begin
   if( rising_edge(AUXCLK) ) then
-    -- shift register for metastability
-    ping_q        <= ping_q(1 downto 0) & PING_IN;
-    pong_q        <= pong_q(1 downto 0) & PONG_IN;
-    -- register stages
 		delay_valid   <= delay_store;
   end if;
 end process THE_SAMPLER_PROC;
@@ -80,7 +74,7 @@ THE_PING_DEGLITCH: deglitch
 port map(
   AUXCLK     => AUXCLK,
   RESET      => RESET,
-  SIGNAL_IN  => ping_q(1),
+  SIGNAL_IN  => PING_IN,
   START_OUT  => start_ping_i
 );
 
@@ -89,7 +83,7 @@ THE_PONG_DEGLITCH: deglitch
 port map(
   AUXCLK     => AUXCLK,
   RESET      => RESET,
-  SIGNAL_IN  => pong_q(1),
+  SIGNAL_IN  => PONG_IN,
   START_OUT  => start_pong_i
 );
 
@@ -145,8 +139,8 @@ begin
   end if;
 end process THE_TOGGLE_PROC;
 
-PING_OUT         <= ping_q(1);
-PONG_OUT         <= pong_q(1);
+PING_OUT         <= PING_IN;
+PONG_OUT         <= PONG_IN;
 START_PING_OUT   <= start_ping_i;
 START_PONG_OUT   <= start_pong_i;
 DELAY_VALUE_OUT  <= delay_data;
-- 
2.43.0