From 6f822a06ab9ce7c884c75de514abae17685b6c92 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Sat, 29 Sep 2012 12:01:18 +0000
Subject: [PATCH] *** empty log message ***

---
 cts/trb3_central.p2t             |  2 +-
 cts/trb3_central.prj             | 18 +++++++++---------
 cts/trb3_central_constraints.lpf |  4 ++--
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t
index 3838d81..15b316a 100644
--- a/cts/trb3_central.p2t
+++ b/cts/trb3_central.p2t
@@ -4,7 +4,7 @@
 -n 1
 -y
 -s 12
--t 10
+-t 2
 -c 1
 -e 2
 #-g guidefile.ncd
diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index 522ec77..6c751cf 100644
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -89,8 +89,8 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vh
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd"
-#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
-add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd"
 #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd"
@@ -223,13 +223,13 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4
 
 add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
 
-add_file -vhdl -lib work "../cts2/cts_pkg.vhd"
-add_file -vhdl -lib work "../cts2/cts_fifo.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_input.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_coin.vhd"
-add_file -vhdl -lib work "../cts2/cts_trg_pseudorand_pulser.vhd"
-add_file -vhdl -lib work "../cts2/cts_trigger.vhd"
-add_file -vhdl -lib work "../cts2/cts.vhd"
+add_file -vhdl -lib work "source/cts_pkg.vhd"
+add_file -vhdl -lib work "source/cts_fifo.vhd"
+add_file -vhdl -lib work "source/cts_trg_input.vhd"
+add_file -vhdl -lib work "source/cts_trg_coin.vhd"
+add_file -vhdl -lib work "source/cts_trg_pseudorand_pulser.vhd"
+add_file -vhdl -lib work "source/cts_trigger.vhd"
+add_file -vhdl -lib work "source/cts.vhd"
 
 add_file -vhdl -lib work "./trb3_central.vhd"
 
diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf
index ddf8486..7276d94 100644
--- a/cts/trb3_central_constraints.lpf
+++ b/cts/trb3_central_constraints.lpf
@@ -143,11 +143,11 @@ UGROUP "gbe_rx_tx"
 
 	
 REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE;
-REGION "MED0" "R75C2D" 30 35 DEVSIZE;
+REGION "MED0" "R75C2D" 30 45 DEVSIZE;
 LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
 FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ;
 FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ;
-REGION "GBE_MAIN_REGION" "R74C30C" 38 36 DEVSIZE;
+REGION "GBE_MAIN_REGION" "R74C50C" 38 36 DEVSIZE;
 LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
 LOCATE UGROUP "tsmac" REGION "MED0" ;
 BLOCK JTAGPATHS ;
-- 
2.43.0