From 6fb21199ff72f68dc962922ed68cb75f1df0ef4b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 10 Nov 2010 10:44:04 +0000 Subject: [PATCH] *** empty log message *** --- trb_net16_endpoint_hades_full_handler.vhd | 44 +++++++++++++++++------ 1 file changed, 33 insertions(+), 11 deletions(-) diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index fde1d44..8e2b7c4 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -206,11 +206,11 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal tbuf_dataready : std_logic; signal tbuf_read_enable : std_logic; - signal dummy : std_logic_vector(255 downto 0); - signal write_enable : std_logic_vector(5 downto 0); - signal read_enable : std_logic_vector(5 downto 0); - signal last_write_enable : std_logic_vector(5 downto 0); - signal last_read_enable : std_logic_vector(5 downto 0); + signal dummy : std_logic_vector(300 downto 0); + signal write_enable : std_logic_vector(6 downto 0); + signal read_enable : std_logic_vector(6 downto 0); + signal last_write_enable : std_logic_vector(6 downto 0); + signal last_read_enable : std_logic_vector(6 downto 0); signal debug_data_handler_i : std_logic_vector(31 downto 0); signal debug_ipu_handler_i : std_logic_vector(31 downto 0); @@ -222,7 +222,12 @@ architecture trb_net16_endpoint_hades_full_handler_arch of trb_net16_endpoint_ha signal int_spike_detected : std_logic; signal tmg_trg_error_i : std_logic; - + signal stat_buffer_i : std_logic_vector(31 downto 0); + signal stat_buffer_read : std_logic; + signal stat_buffer_ready : std_logic; + signal stat_buffer_unknown : std_logic; + + begin --------------------------------------------------------------------------- -- TrbNet Endpoint @@ -347,9 +352,9 @@ begin THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, others => 0) + PORT_NUMBER => 7, + PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"), + PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0) ) port map( CLK => CLK, @@ -407,55 +412,65 @@ begin BUS_READ_ENABLE_OUT(3) => read_enable(3), BUS_READ_ENABLE_OUT(4) => read_enable(4), BUS_READ_ENABLE_OUT(5) => read_enable(5), + BUS_READ_ENABLE_OUT(6) => stat_buffer_read, BUS_WRITE_ENABLE_OUT(0) => BUS_WRITE_ENABLE_OUT, BUS_WRITE_ENABLE_OUT(1) => dummy(0), BUS_WRITE_ENABLE_OUT(2) => write_enable(2), BUS_WRITE_ENABLE_OUT(3) => write_enable(3), BUS_WRITE_ENABLE_OUT(4) => write_enable(4), BUS_WRITE_ENABLE_OUT(5) => write_enable(5), + BUS_WRITE_ENABLE_OUT(6) => write_enable(6), BUS_DATA_OUT(31 downto 0) => BUS_DATA_OUT, BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2), BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34), BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96), + BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260), BUS_ADDR_OUT(15 downto 0) => BUS_ADDR_OUT, BUS_ADDR_OUT(19 downto 16) => dbuf_addr, BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78), BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), + BUS_ADDR_OUT(111 downto 96)=> dummy(259 downto 244), BUS_TIMEOUT_OUT(0) => BUS_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(94), BUS_TIMEOUT_OUT(2) => dummy(95), BUS_TIMEOUT_OUT(3) => dummy(192), BUS_TIMEOUT_OUT(4) => dummy(193), BUS_TIMEOUT_OUT(5) => dummy(194), + BUS_TIMEOUT_OUT(6) => dummy(243), BUS_DATA_IN(31 downto 0) => BUS_DATA_IN, BUS_DATA_IN(63 downto 32) => dbuf_data_in, BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0), + BUS_DATA_IN(223 downto 192)=> stat_buffer_i, BUS_DATAREADY_IN(0) => BUS_DATAREADY_IN, BUS_DATAREADY_IN(1) => dbuf_dataready, BUS_DATAREADY_IN(2) => tbuf_dataready, BUS_DATAREADY_IN(3) => last_read_enable(3), BUS_DATAREADY_IN(4) => last_read_enable(4), BUS_DATAREADY_IN(5) => last_read_enable(5), + BUS_DATAREADY_IN(6) => stat_buffer_ready, BUS_WRITE_ACK_IN(0) => BUS_WRITE_ACK_IN, BUS_WRITE_ACK_IN(1) => '0', BUS_WRITE_ACK_IN(2) => '0', BUS_WRITE_ACK_IN(3) => '0', BUS_WRITE_ACK_IN(4) => '0', BUS_WRITE_ACK_IN(5) => '0', + BUS_WRITE_ACK_IN(6) => '0', BUS_NO_MORE_DATA_IN(0) => BUS_NO_MORE_DATA_IN, BUS_NO_MORE_DATA_IN(1) => '0', BUS_NO_MORE_DATA_IN(2) => '0', BUS_NO_MORE_DATA_IN(3) => '0', BUS_NO_MORE_DATA_IN(4) => '0', BUS_NO_MORE_DATA_IN(5) => '0', + BUS_NO_MORE_DATA_IN(6) => '0', BUS_UNKNOWN_ADDR_IN(0) => BUS_UNKNOWN_ADDR_IN, BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2), BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), - BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5) + BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), + BUS_UNKNOWN_ADDR_IN(6) => stat_buffer_unknown ); proc_ack_strobes : process(CLK) @@ -521,7 +536,14 @@ begin STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level, STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, STATUS_OUT => stat_handler_i, - + TIMER_TICKS_IN => time_ticks_i, + STATISTICS_DATA_OUT => stat_buffer_i, + STATISTICS_UNKNOWN_OUT => stat_buffer_unknown, + STATISTICS_READY_OUT => stat_buffer_ready, + STATISTICS_READ_IN => stat_buffer_read, + STATISTICS_ADDR_IN => BUS_ADDR_OUT(4 downto 0), + + --Debug DEBUG_DATA_HANDLER_OUT => debug_data_handler_i, DEBUG_IPU_HANDLER_OUT => debug_ipu_handler_i -- 2.43.0