From 704bc7eeed876c2d780644a634c4dfd397fd9a63 Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Tue, 23 Jan 2018 14:07:03 +0100 Subject: [PATCH] fixed small timing bug, IF --- amps2/padiwa_amps2.prj | 4 ++ amps2/padiwa_amps2.vhd | 90 ++++++++++++++++++++++++++++-------------- 2 files changed, 64 insertions(+), 30 deletions(-) diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj index d7e790c..745b9d9 100644 --- a/amps2/padiwa_amps2.prj +++ b/amps2/padiwa_amps2.prj @@ -17,6 +17,10 @@ add_file -vhdl -lib work "../source/pwm.vhd" add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd" add_file -vhdl -lib work "padiwa_amps2.vhd" +add_file -vhdl -lib work "../source/timer.vhd" +add_file -vhdl -lib work "../source/Amps2_Interface.vhd" +add_file -vhdl -lib work "../source/i2c_master.vhd" +add_file -vhdl -lib work "../source/Amps2_TempSensor_UID.vhd" #add_file -vhdl -lib work "../cores/flashram.vhd" diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd index d0dc111..bcfe44f 100644 --- a/amps2/padiwa_amps2.vhd +++ b/amps2/padiwa_amps2.vhd @@ -80,6 +80,7 @@ architecture arch of padiwa_amps2 is signal bus_read : std_logic := '0'; signal bus_write : std_logic := '0'; signal bus_ready : std_logic; + signal delayed_bus_ready : std_logic_vector(1 downto 0) := "00"; signal bus_busy : std_logic; signal spi_data_out : std_logic_vector(15 downto 0); @@ -132,7 +133,8 @@ architecture arch of padiwa_amps2 is signal delayed_inputs : std_logic_vector(127 downto 0); signal selected_delay : std_logic_vector(8 downto 1); signal delayselect : integer range 0 to 15; - + + component OSCH generic (NOM_FREQ: string := "133.00"); port ( @@ -157,12 +159,12 @@ clk_source: OSCH ); THE_PLL : entity work.pll_in133_out33_133_266 - port map ( - CLKI => clk_osc, - CLKOP => clk_i, --133 - CLKOS => clk_33, --33 - CLKOS2=> clk_266 --266 - ); + port map ( + CLKI => clk_osc, + CLKOP => clk_i, --133 + CLKOS => clk_33, --33 + CLKOS2=> clk_266 --266 + ); --------------------------------------------------------------------------- @@ -210,7 +212,7 @@ THE_PLL : entity work.pll_in133_out33_133_266 THE_SPI : entity work.spi_slave port map( - CLK => clk_i, + CLK => clk_33, SPI_CLK => SPI_CLK, SPI_CS => SPI_CS, SPI_IN => SPI_IN, @@ -232,7 +234,7 @@ THE_SPI : entity work.spi_slave THE_FLASH_CONTROLLER : entity generic_flash_ctrl port map( - CLK => clk_i, + CLK => clk_33, RESET => '0', SPI_DATA_IN => spi_data_out, @@ -258,6 +260,13 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl -- Temperature and UID reader --------------------------------------------------------------------------- +TEMP_SENSOR_AND_UID: entity temp_sensor_and_UID + port map( + clk => clk_i, + temperature => temperature_i, + sda => I2C_SCL, + scl => I2C_SCL + ); --------------------------------------------------------------------------- @@ -281,31 +290,52 @@ end generate; --------------------------------------------------------------------------- THE_IO_REG : process begin - wait until rising_edge(clk_i); + wait until rising_edge(clk_33); bus_ready <= '0'; pwm_write_i <= '0'; - + spi_tx_data <= x"0000"; + + if delayed_bus_ready = "01" then + --bus_ready <= '1'; + spi_tx_data <= pwm_data_o; + delayed_bus_ready <= "10"; + elsif delayed_bus_ready = "10" then + bus_ready <= '1'; + spi_tx_data <= pwm_data_o; + delayed_bus_ready <= "00"; + else + delayed_bus_ready <= "00"; + end if; + if bus_read = '1' then bus_ready <= '1'; - case spi_addr is - when x"20" => spi_tx_data <= input_enable; - when x"21" => spi_tx_data <= inp_status; - when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ; - when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); - when x"24" => spi_tx_data <= inp_invert; - when x"25" => spi_tx_data <= inp_stretch; - when x"26" => spi_tx_data <= comp_setting; - when x"27" => spi_tx_data <= x"00" & discharge_disable; - when x"28" => spi_tx_data <= x"00" & discharge_override; - when x"29" => spi_tx_data <= x"00" & discharge_highz; - when x"2a" => spi_tx_data <= x"00" & delay_invert; - when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8)); - - when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); - when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); - when x"32" => spi_tx_data <= x"0000"; - when others => null; - end case; + if (spi_addr >= x"00") and (spi_addr < x"10") and delayed_bus_ready = "00"then + bus_ready <= '0'; + delayed_bus_ready <= "01"; + spi_tx_data <= pwm_data_o; + pwm_addr_i <= spi_addr(3 downto 0); + else + case spi_addr is + when x"14" => spi_tx_data <= "0000" & temperature_i; + when x"20" => spi_tx_data <= input_enable; + when x"21" => spi_tx_data <= inp_status; + when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ; + when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); + when x"24" => spi_tx_data <= inp_invert; + when x"25" => spi_tx_data <= inp_stretch; + when x"26" => spi_tx_data <= comp_setting; + when x"27" => spi_tx_data <= x"00" & discharge_disable; + when x"28" => spi_tx_data <= x"00" & discharge_override; + when x"29" => spi_tx_data <= x"00" & discharge_highz; + when x"2a" => spi_tx_data <= x"00" & delay_invert; + when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8)); + + when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); + when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); + when x"32" => spi_tx_data <= x"0000"; + when others => null; + end case; + end if; elsif bus_write = '1' then if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM pwm_data_i <= spi_rx_data; -- 2.43.0