From 7053e4442fe9197fad1ffc28691ced8767acdde9 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 15 Jan 2008 17:26:44 +0000 Subject: [PATCH] *** empty log message *** --- testbench/trb_net_counter_tester.vhd | 116 +++++++++++++++++++++++++++ trb_net16_io_multiplexer.vhd | 2 +- trb_net16_med_tlk.vhd | 70 ++++++++++++---- 3 files changed, 171 insertions(+), 17 deletions(-) create mode 100644 testbench/trb_net_counter_tester.vhd diff --git a/testbench/trb_net_counter_tester.vhd b/testbench/trb_net_counter_tester.vhd new file mode 100644 index 0000000..c9fcdb0 --- /dev/null +++ b/testbench/trb_net_counter_tester.vhd @@ -0,0 +1,116 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; +use work.trb_net_std.all; + + +entity trb_net_counter_tester is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + -- Media direction port + MED_DATAREADY_IN: in STD_LOGIC; + MED_DATA_IN: in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN: in STD_LOGIC_VECTOR (1 downto 0); + MED_READ_OUT: out STD_LOGIC; + + MED_DATAREADY_OUT: out STD_LOGIC; + MED_DATA_OUT: out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (1 downto 0); + MED_READ_IN: in STD_LOGIC; + + MED_ERROR_IN : in std_logic_vector(2 downto 0); + STAT: out std_logic_vector(63 downto 0) + ); +end entity; + + +architecture trb_net_counter_tester_arch of trb_net_counter_tester is + signal recv_counter : std_logic_vector(17 downto 0); + signal trans_counter : std_logic_vector(17 downto 0); + signal buf_MED_DATAREADY_OUT : std_logic; + signal recv_counter_mismatch : std_logic; + signal next_recv_counter_mismatch : std_logic; + signal t : std_logic; + signal cn : std_logic_vector(7 downto 0); + +begin + + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + MED_DATA_OUT <= trans_counter(17 downto 2); + MED_PACKET_NUM_OUT <= trans_counter(1 downto 0); + MED_READ_OUT <= '1'; + + STAT(17 downto 0) <= MED_DATA_IN & MED_PACKET_NUM_IN; + STAT(24) <= recv_counter_mismatch; + STAT(49 downto 32) <= recv_counter; + + --buf_MED_DATAREADY_OUT <= '1' when MED_ERROR_IN = ERROR_OK else '0'; + + process(MED_ERROR_IN, t) + begin + buf_MED_DATAREADY_OUT <= '0'; + if MED_ERROR_IN = ERROR_OK then + buf_MED_DATAREADY_OUT <= '1'; + end if; + if t = '1' then + buf_MED_DATAREADY_OUT <= '0'; + end if; + end process; + t <= (cn(3) and cn(7) and not cn(5)) or + (not cn(3) and cn(7) and cn(5)) or + (cn(3) and not cn(7) and cn(5)); + + next_recv_counter_mismatch <= '1' when (recv_counter /= (MED_DATA_IN & MED_PACKET_NUM_IN)) or recv_counter_mismatch = '1' else '0'; + + cn_counter : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + cn <= (others => '0'); + else + cn <= cn + 1; + end if; + end if; + end process; + + R_MISMATCH : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + recv_counter_mismatch <= '0'; + elsif MED_DATAREADY_IN = '1' then + recv_counter_mismatch <= next_recv_counter_mismatch; + end if; + end if; + end process; + + R_COUNTER : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + recv_counter <= (others => '0'); + elsif MED_DATAREADY_IN = '1' then + recv_counter <= recv_counter + 1; + end if; + end if; + end process; + + S_COUNTER : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + trans_counter <= (others => '0'); + elsif buf_MED_DATAREADY_OUT = '1' and MED_READ_IN = '1' then + trans_counter <= trans_counter + 1; + end if; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index d4887c3..47dddb4 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -154,7 +154,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is else INT_DATA_OUT ((c_DATA_WIDTH)*(i+1)-1 downto (c_DATA_WIDTH)*(i)) <= MED_DATA_IN; INT_PACKET_NUM_OUT(2*(i+1)-1 downto 2*i) <= MED_PACKET_NUM_IN; - INT_DATAREADY_OUT(i) <= next_demux_dr(i); + INT_DATAREADY_OUT(i) <= next_demux_dr(i) and MED_DATAREADY_IN; end if; end if; end process; diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index a138165..2a988b0 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -76,11 +76,13 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal last_fifo_rd_en_a, last_fifo_rd_en_m : std_logic; signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); signal buf_MED_READ_OUT : std_logic; + signal buf_MED_DATAREADY_OUT : std_logic; signal rx_locked : std_logic; signal tx_allow : std_logic; signal rx_lock_counter : std_logic_vector(20 downto 0); signal internal_reset : std_logic; signal reset_counter : std_logic_vector(16 downto 0); + signal reset_packet_num : std_logic; signal reg_RXD : std_logic_vector(15 downto 0); signal reg_RX_DV : std_logic; @@ -89,7 +91,7 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal reg_TX_EN : std_logic; signal TLK_CLK_neg : std_logic; -signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic; + signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic; begin -- STAT(3 downto 0) <= fifo_status_a; @@ -99,7 +101,7 @@ begin -- STAT(13 downto 12) <= fifo_empty_m & fifo_full_m; -- STAT(31 downto 14) <= (others => '0'); - TLK_TX_ER <= '0'; + TLK_ENABLE <= not RESET; TLK_LCKREFN <= '1'; TLK_PRBSEN <= '0'; @@ -131,11 +133,27 @@ begin fifo_din_a <= rx_locked & reg_RX_ER & reg_RXD; fifo_rd_en_a <= not fifo_empty_a; fifo_reset <= internal_reset; - MED_DATA_OUT <= fifo_dout_a(15 downto 0); - MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16) and fifo_dout_a(17); + --MED_DATA_OUT <= fifo_dout_a(15 downto 0); + buf_MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16) and fifo_dout_a(17); MED_ERROR_OUT <= ERROR_OK when rx_locked = '1' else ERROR_NC; - MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + --MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + --MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + + process(CLK) + begin + if rising_edge(CLK) then + if internal_reset = '1' then + MED_PACKET_NUM_OUT <= "00"; + MED_DATAREADY_OUT <= '0'; + MED_DATA_OUT <= (others => '0'); + else + MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; + MED_DATA_OUT <= fifo_dout_a(15 downto 0); + end if; + end if; + end process; STAT(0) <= internal_reset; STAT(1) <= rx_locked; @@ -146,6 +164,8 @@ begin STAT(6) <= fifo_rd_en_m; STAT(7) <= fifo_empty_m; STAT(8) <= fifo_full_a; + STAT(14) <= reg_RX_DV; + STAT(15) <= reg_RX_ER; STAT(31 downto 16) <= reg_RXD; process(TLK_RX_CLK) @@ -166,9 +186,9 @@ begin process(CLK) begin if rising_edge(CLK) then - if internal_reset = '1' then - buf_MED_PACKET_NUM_OUT <= "11"; - elsif fifo_rd_en_a = '1' then + if internal_reset = '1' or reset_packet_num = '1' then + buf_MED_PACKET_NUM_OUT <= "00"; + elsif buf_MED_DATAREADY_OUT = '1' then buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; end if; end if; @@ -185,6 +205,9 @@ begin end if; end process; +--common network packet number reset + reset_packet_num <= '0'; + ------------- --Sender @@ -211,7 +234,7 @@ U_DCM_Transmitter: DCM LOCKED => open ); -- -U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg); +U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg); U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); @@ -230,10 +253,25 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); ); fifo_rd_en_m <= tx_allow and not fifo_empty_m; - fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; - fifo_din_m <= "00" & MED_DATA_IN; + --fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; + --fifo_din_m <= "00" & MED_DATA_IN; TLK_TXD <= reg_TXD; TLK_TX_EN <= reg_TX_EN; + TLK_TX_ER <= '0'; + + process(CLK) + begin + if rising_edge(CLK) then + if internal_reset = '1' then + fifo_wr_en_m <= '0'; + fifo_din_m <= (others => '0'); + else + fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; + fifo_din_m <= MED_PACKET_NUM_IN & MED_DATA_IN; + end if; + end if; + end process; + process(TLK_CLK_neg) begin @@ -266,7 +304,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); if rising_edge(TLK_RX_CLK) then if internal_reset = '1' or TLK_RX_ER = '1' then rx_lock_counter <= (others => '0'); - elsif rx_lock_counter(20) = '0' then + elsif rx_lock_counter(20) = '0' then --20 rx_lock_counter <= rx_lock_counter + 1; end if; end if; @@ -279,7 +317,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); if rising_edge(TLK_RX_CLK) then if internal_reset = '1' or TLK_RX_ER = '1' then rx_locked <= '0'; - elsif rx_lock_counter(8) = '1' then + elsif rx_lock_counter(8) = '1' then --8 rx_locked <= '1'; end if; end if; @@ -291,7 +329,7 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); if rising_edge(TLK_RX_CLK) then if internal_reset = '1' or TLK_RX_ER = '1' then tx_allow <= '0'; - elsif rx_lock_counter(10) = '1' then + elsif rx_lock_counter(10) = '1' then --10 tx_allow <= '1'; end if; end if; @@ -304,12 +342,12 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); if rising_edge(CLK) then if RESET = '1' then reset_counter <= (others => '0'); - elsif reset_counter(16) = '0' then + elsif reset_counter(16) = '0' then --16 reset_counter <= reset_counter + 1; end if; end if; end process internal_reset_counter; -internal_reset <= not reset_counter(16); +internal_reset <= not reset_counter(16); --16 end architecture; -- 2.43.0