From 70b225e742dbfb18ace5d14e90880c41b7e363c4 Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Tue, 29 Jun 2010 00:44:09 +0000
Subject: [PATCH] 29_06_10

---
 gbe_ecp2m/tb_gbe_buf.vhd                   | 1440 ++++++++++----------
 gbe_ecp2m/trb_net16_gbe_buf.vhd            |   79 +-
 gbe_ecp2m/trb_net16_gbe_frame_constr.vhd   |   24 +-
 gbe_ecp2m/trb_net16_gbe_frame_trans.vhd    |   10 +-
 gbe_ecp2m/trb_net16_gbe_packet_constr.vhd  |  134 +-
 gbe_ecp2m/trb_net16_gbe_setup.vhd          |   40 +-
 gbe_ecp2m/trb_net16_ipu2gbe.vhd            |  125 +-
 gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd |    2 +-
 8 files changed, 1020 insertions(+), 834 deletions(-)

diff --git a/gbe_ecp2m/tb_gbe_buf.vhd b/gbe_ecp2m/tb_gbe_buf.vhd
index 0516ce0..78db3be 100755
--- a/gbe_ecp2m/tb_gbe_buf.vhd
+++ b/gbe_ecp2m/tb_gbe_buf.vhd
@@ -1,720 +1,720 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.math_real.all;
-USE ieee.numeric_std.ALL;
-
-ENTITY testbench IS
-END testbench;
-
-ARCHITECTURE behavior OF testbench IS 
-	component buf_tester is --trb_net16_gbe_buf is
-	generic( 
-		DO_SIMULATION		: integer range 0 to 1 := 1;
-		USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1
-	);
-	port(
-		CLK							: in	std_logic;
-		TEST_CLK					: in	std_logic; -- only for simulation!
-		CLK_125_TX_IN				: in std_logic;  -- gk 28.04.01 used only in internal 125MHz clock mode
-		CLK_125_RX_IN				: in std_logic;  -- gk 28.04.01 used only in internal 125MHz clock mode
-		RESET : IN std_logic;
-		GSR_N : IN std_logic;
-		STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);
-		------------------------
-		IP_CFG_START_IN : IN std_logic;
-		IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);
-		IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);
-		MR_RESET_IN : IN std_logic;
-		MR_MODE_IN : IN std_logic;
-		MR_RESTART_IN : IN std_logic;
-		IP_CFG_MEM_CLK_OUT : OUT std_logic;
-		IP_CFG_DONE_OUT : OUT std_logic;
-		IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);
-		-- gk 29.03.10
-		SLV_ADDR_IN                  : in std_logic_vector(7 downto 0);
-		SLV_READ_IN                  : in std_logic;
-		SLV_WRITE_IN                 : in std_logic;
-		SLV_BUSY_OUT                 : out std_logic;
-		SLV_ACK_OUT                  : out std_logic;
-		SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
-		SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
-		-- gk 26.04.10
-		-- registers setup interface
-		BUS_ADDR_IN               : in std_logic_vector(7 downto 0);
-		BUS_DATA_IN               : in std_logic_vector(31 downto 0);
-		BUS_DATA_OUT              : out std_logic_vector(31 downto 0);  -- gk 26.04.10
-		BUS_WRITE_EN_IN           : in std_logic;  -- gk 26.04.10
-		BUS_READ_EN_IN            : in std_logic;  -- gk 26.04.10
-		BUS_ACK_OUT               : out std_logic;  -- gk 26.04.10
-		-- gk 23.04.10
-		LED_PACKET_SENT_OUT        : out std_logic;
-		LED_AN_DONE_N_OUT            : out std_logic;
-		------------------------
-		CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);
-		CTS_CODE_IN : IN std_logic_vector(7 downto 0);
-		CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);
-		CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);
-		CTS_START_READOUT_IN : IN std_logic;
-		CTS_READ_IN : IN std_logic;
-		FEE_DATA_IN : IN std_logic_vector(15 downto 0);
-		FEE_DATAREADY_IN : IN std_logic;
-		FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);
-		FEE_BUSY_IN : IN std_logic;
-		SFP_RXD_P_IN : IN std_logic;
-		SFP_RXD_N_IN : IN std_logic;
-		SFP_REFCLK_P_IN : IN std_logic;
-		SFP_REFCLK_N_IN : IN std_logic;
-		SFP_PRSNT_N_IN : IN std_logic;
-		SFP_LOS_IN : IN std_logic;          
-		STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);
-		CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);
-		CTS_DATAREADY_OUT : OUT std_logic;
-		CTS_READOUT_FINISHED_OUT : OUT std_logic;
-		CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);
-		CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);
-		FEE_READ_OUT : OUT std_logic;
-		SFP_TXD_P_OUT : OUT std_logic;
-		SFP_TXD_N_OUT : OUT std_logic;
-		SFP_TXDIS_OUT : OUT std_logic;
-		IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0);
-		IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0);
-		IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
-		IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
-		IG_DATA_TST : OUT std_logic_vector(15 downto 0);
-		IG_WCNT_TST : OUT std_logic_vector(15 downto 0);
-		IG_RCNT_TST : OUT std_logic_vector(16 downto 0);
-		IG_RD_EN_TST : OUT std_logic;
-		IG_WR_EN_TST : OUT std_logic;
-		IG_EMPTY_TST : OUT std_logic;
-		IG_AEMPTY_TST : OUT std_logic;
-		IG_FULL_TST : OUT std_logic;
-		IG_AFULL_TST : OUT std_logic;
-		PC_WR_EN_TST : OUT std_logic;
-		PC_DATA_TST : OUT std_logic_vector(7 downto 0);
-		PC_READY_TST : OUT std_logic;
-		PC_START_OF_SUB_TST : OUT std_logic;
-		PC_END_OF_DATA_TST : OUT std_logic;
-		PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0);
-		PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0);
-		PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0);
-		PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0);
-		PC_PADDING_TST : OUT std_logic;
-		PC_DECODING_TST : OUT std_logic_vector(31 downto 0);
-		PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0);
-		PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0);
-		PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0);
-		PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
-		PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
-		PC_SHF_EMPTY_TST : OUT std_logic;
-		PC_SHF_FULL_TST : OUT std_logic;
-		PC_SHF_WR_EN_TST : OUT std_logic;
-		PC_SHF_RD_EN_TST : OUT std_logic;
-		PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0);
-		PC_DF_EMPTY_TST : OUT std_logic;
-		PC_DF_FULL_TST : OUT std_logic;
-		PC_DF_WR_EN_TST : OUT std_logic;
-		PC_DF_RD_EN_TST : OUT std_logic;
-		PC_DF_Q_TST : OUT std_logic_vector(7 downto 0);
-		PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0);
-		PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0);
-		PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0);
-		PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0);
-		PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0);
-		PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
-		PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
-		FC_WR_EN_TST : OUT std_logic;
-		FC_DATA_TST : OUT std_logic_vector(7 downto 0);
-		FC_H_READY_TST : OUT std_logic;
-		FC_READY_TST : OUT std_logic;
-		FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0);
-		FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0);
-		FC_IDENT_TST : OUT std_logic_vector(15 downto 0);
-		FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0);
-		FC_SOD_TST : OUT std_logic;
-		FC_EOD_TST : OUT std_logic;
-		FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0);
-		FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
-		FT_DATA_TST : OUT std_logic_vector(8 downto 0);
-		FT_TX_EMPTY_TST : OUT std_logic;
-		FT_START_OF_PACKET_TST : OUT std_logic;
-		FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0);
-		FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0);
-		FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
-		MAC_HADDR_TST : OUT std_logic_vector(7 downto 0);
-		MAC_HDATA_TST : OUT std_logic_vector(7 downto 0);
-		MAC_HCS_TST : OUT std_logic;
-		MAC_HWRITE_TST : OUT std_logic;
-		MAC_HREAD_TST : OUT std_logic;
-		MAC_HREADY_TST : OUT std_logic;
-		MAC_HDATA_EN_TST : OUT std_logic;
-		MAC_FIFOAVAIL_TST : OUT std_logic;
-		MAC_FIFOEOF_TST : OUT std_logic;
-		MAC_FIFOEMPTY_TST : OUT std_logic;
-		MAC_TX_READ_TST : OUT std_logic;
-		MAC_TX_DONE_TST : OUT std_logic;
-		PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0);
-		PCS_AN_COMPLETE_TST : OUT std_logic;
-		PCS_AN_PAGE_RX_TST : OUT std_logic;
-		ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)
-		);
-	END COMPONENT;
-
-	SIGNAL CLK :  std_logic;
-	SIGNAL TEST_CLK :  std_logic;
-	SIGNAL RESET :  std_logic;
-	SIGNAL GSR_N :  std_logic;
-	SIGNAL STAGE_STAT_REGS_OUT :  std_logic_vector(31 downto 0);
-	SIGNAL STAGE_CTRL_REGS_IN :  std_logic_vector(31 downto 0);
-	SIGNAL IP_CFG_START_IN :  std_logic;
-	SIGNAL IP_CFG_BANK_SEL_IN :  std_logic_vector(3 downto 0);
-	SIGNAL IP_CFG_MEM_DATA_IN :  std_logic_vector(31 downto 0);
-	SIGNAL MR_RESET_IN :  std_logic;
-	SIGNAL MR_MODE_IN :  std_logic;
-	SIGNAL MR_RESTART_IN :  std_logic;
-	SIGNAL IP_CFG_MEM_CLK_OUT :  std_logic;
-	SIGNAL IP_CFG_DONE_OUT :  std_logic;
-	SIGNAL IP_CFG_MEM_ADDR_OUT :  std_logic_vector(7 downto 0);
-	SIGNAL CTS_NUMBER_IN :  std_logic_vector(15 downto 0);
-	SIGNAL CTS_CODE_IN :  std_logic_vector(7 downto 0);
-	SIGNAL CTS_INFORMATION_IN :  std_logic_vector(7 downto 0);
-	SIGNAL CTS_READOUT_TYPE_IN :  std_logic_vector(3 downto 0);
-	SIGNAL CTS_START_READOUT_IN :  std_logic;
-	SIGNAL CTS_DATA_OUT :  std_logic_vector(31 downto 0);
-	SIGNAL CTS_DATAREADY_OUT :  std_logic;
-	SIGNAL CTS_READOUT_FINISHED_OUT :  std_logic;
-	SIGNAL CTS_READ_IN :  std_logic;
-	SIGNAL CTS_LENGTH_OUT :  std_logic_vector(15 downto 0);
-	SIGNAL CTS_ERROR_PATTERN_OUT :  std_logic_vector(31 downto 0);
-	SIGNAL FEE_DATA_IN :  std_logic_vector(15 downto 0);
-	SIGNAL FEE_DATAREADY_IN :  std_logic;
-	SIGNAL FEE_READ_OUT :  std_logic;
-	SIGNAL FEE_STATUS_BITS_IN :  std_logic_vector(31 downto 0);
-	SIGNAL FEE_BUSY_IN :  std_logic;
-	SIGNAL SFP_RXD_P_IN :  std_logic;
-	SIGNAL SFP_RXD_N_IN :  std_logic;
-	SIGNAL SFP_TXD_P_OUT :  std_logic;
-	SIGNAL SFP_TXD_N_OUT :  std_logic;
-	SIGNAL SFP_REFCLK_P_IN :  std_logic;
-	SIGNAL SFP_REFCLK_N_IN :  std_logic;
-	SIGNAL SFP_PRSNT_N_IN :  std_logic;
-	SIGNAL SFP_LOS_IN :  std_logic;
-	SIGNAL SFP_TXDIS_OUT :  std_logic;
-	SIGNAL IG_CTS_CTR_TST :  std_logic_vector(2 downto 0);
-	SIGNAL IG_REM_CTR_TST :  std_logic_vector(3 downto 0);
-	SIGNAL IG_BSM_LOAD_TST :  std_logic_vector(3 downto 0);
-	SIGNAL IG_BSM_SAVE_TST :  std_logic_vector(3 downto 0);
-	SIGNAL IG_DATA_TST :  std_logic_vector(15 downto 0);
-	SIGNAL IG_WCNT_TST :  std_logic_vector(15 downto 0);
-	SIGNAL IG_RCNT_TST :  std_logic_vector(16 downto 0);
-	SIGNAL IG_RD_EN_TST :  std_logic;
-	SIGNAL IG_WR_EN_TST :  std_logic;
-	SIGNAL IG_EMPTY_TST :  std_logic;
-	SIGNAL IG_AEMPTY_TST :  std_logic;
-	SIGNAL IG_FULL_TST :  std_logic;
-	SIGNAL IG_AFULL_TST :  std_logic;
-	SIGNAL PC_WR_EN_TST :  std_logic;
-	SIGNAL PC_DATA_TST :  std_logic_vector(7 downto 0);
-	SIGNAL PC_READY_TST :  std_logic;
-	SIGNAL PC_START_OF_SUB_TST :  std_logic;
-	SIGNAL PC_END_OF_DATA_TST :  std_logic;
-	SIGNAL PC_SUB_SIZE_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_TRIG_NR_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_PADDING_TST :  std_logic;
-	SIGNAL PC_DECODING_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_EVENT_ID_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_QUEUE_DEC_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_BSM_CONSTR_TST :  std_logic_vector(3 downto 0);
-	SIGNAL PC_BSM_LOAD_TST :  std_logic_vector(3 downto 0);
-	SIGNAL PC_BSM_SAVE_TST :  std_logic_vector(3 downto 0);
-	SIGNAL PC_SHF_EMPTY_TST :  std_logic;
-	SIGNAL PC_SHF_FULL_TST :  std_logic;
-	SIGNAL PC_SHF_WR_EN_TST :  std_logic;
-	SIGNAL PC_SHF_RD_EN_TST :  std_logic;
-	SIGNAL PC_SHF_Q_TST :  std_logic_vector(7 downto 0);
-	SIGNAL PC_DF_EMPTY_TST :  std_logic;
-	SIGNAL PC_DF_FULL_TST :  std_logic;
-	SIGNAL PC_DF_WR_EN_TST :  std_logic;
-	SIGNAL PC_DF_RD_EN_TST :  std_logic;
-	SIGNAL PC_DF_Q_TST :  std_logic_vector(7 downto 0); 
-	SIGNAL PC_ALL_CTR_TST :  std_logic_vector(4 downto 0);
-	SIGNAL PC_SUB_CTR_TST :  std_logic_vector(4 downto 0);
-	SIGNAL PC_BYTES_LOADED_TST :  std_logic_vector(15 downto 0);
-	SIGNAL PC_SIZE_LEFT_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_SUB_SIZE_TO_SAVE_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_SUB_SIZE_LOADED_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_SUB_BYTES_LOADED_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_QUEUE_SIZE_TST :  std_logic_vector(31 downto 0);
-	SIGNAL PC_ACT_QUEUE_SIZE_TST :  std_logic_vector(31 downto 0);
-	SIGNAL FC_WR_EN_TST :  std_logic;
-	SIGNAL FC_DATA_TST :  std_logic_vector(7 downto 0);
-	SIGNAL FC_H_READY_TST :  std_logic;
-	SIGNAL FC_READY_TST :  std_logic;
-	SIGNAL FC_IP_SIZE_TST :  std_logic_vector(15 downto 0);
-	SIGNAL FC_UDP_SIZE_TST :  std_logic_vector(15 downto 0);
-	SIGNAL FC_IDENT_TST :  std_logic_vector(15 downto 0);
-	SIGNAL FC_FLAGS_OFFSET_TST :  std_logic_vector(15 downto 0);
-	SIGNAL FC_SOD_TST :  std_logic;
-	SIGNAL FC_EOD_TST :  std_logic;
-	SIGNAL FC_BSM_CONSTR_TST :  std_logic_vector(7 downto 0);
-	SIGNAL FC_BSM_TRANS_TST :  std_logic_vector(3 downto 0);
-	SIGNAL FT_DATA_TST :  std_logic_vector(8 downto 0);
-	SIGNAL FT_TX_EMPTY_TST :  std_logic;
-	SIGNAL FT_START_OF_PACKET_TST :  std_logic;
-	SIGNAL FT_BSM_INIT_TST :  std_logic_vector(3 downto 0);
-	SIGNAL FT_BSM_MAC_TST :  std_logic_vector(3 downto 0);
-	SIGNAL FT_BSM_TRANS_TST :  std_logic_vector(3 downto 0);
-	SIGNAL MAC_HADDR_TST :  std_logic_vector(7 downto 0);
-	SIGNAL MAC_HDATA_TST :  std_logic_vector(7 downto 0);
-	SIGNAL MAC_HCS_TST :  std_logic;
-	SIGNAL MAC_HWRITE_TST :  std_logic;
-	SIGNAL MAC_HREAD_TST :  std_logic;
-	SIGNAL MAC_HREADY_TST :  std_logic;
-	SIGNAL MAC_HDATA_EN_TST :  std_logic;
-	SIGNAL MAC_FIFOAVAIL_TST :  std_logic;
-	SIGNAL MAC_FIFOEOF_TST :  std_logic;
-	SIGNAL MAC_FIFOEMPTY_TST :  std_logic;
-	SIGNAL MAC_TX_READ_TST :  std_logic;
-	SIGNAL MAC_TX_DONE_TST :  std_logic;
-	SIGNAL PCS_AN_LP_ABILITY_TST :  std_logic_vector(15 downto 0);
-	SIGNAL PCS_AN_COMPLETE_TST :  std_logic;
-	SIGNAL PCS_AN_PAGE_RX_TST :  std_logic;
-	SIGNAL ANALYZER_DEBUG_OUT :  std_logic_vector(63 downto 0);
-	--gk 29.03.10
-	signal SLV_ADDR_IN : std_logic_vector(7 downto 0);
-	signal SLV_READ_IN : std_logic;
-	signal SLV_WRITE_IN : std_logic;
-	signal SLV_BUSY_OUT : std_logic;
-	signal SLV_ACK_OUT : std_logic;
-	signal SLV_DATA_IN : std_logic_vector(31 downto 0);
-	signal SLV_DATA_OUT : std_logic_vector(31 downto 0);
-
-BEGIN
-
--- Please check and add your generic clause manually
-	uut: buf_tester --trb_net16_gbe_buf 
-	GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
-	PORT MAP(
-		CLK => CLK,
-		CLK_125_TX_IN => '0',
-		CLK_125_RX_IN => '0',
-		TEST_CLK => TEST_CLK,
-		RESET => RESET,
-		GSR_N => GSR_N,
-		STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,
-		STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,
-		IP_CFG_START_IN => IP_CFG_START_IN,
-		IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,
-		IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,
-		MR_RESET_IN => MR_RESET_IN,
-		MR_MODE_IN => MR_MODE_IN,
-		MR_RESTART_IN => MR_RESTART_IN,
-		IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,
-		IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,
-		IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,
-		-- gk 29.03.10
-		SLV_ADDR_IN => SLV_ADDR_IN,
-		SLV_READ_IN => SLV_READ_IN,
-		SLV_WRITE_IN => SLV_WRITE_IN,
-		SLV_BUSY_OUT => SLV_BUSY_OUT,
-		SLV_ACK_OUT => SLV_ACK_OUT,
-		SLV_DATA_IN => SLV_DATA_IN,
-		SLV_DATA_OUT => SLV_DATA_OUT,
-		-- gk 22.04.10
-		-- registers setup interface
-		BUS_ADDR_IN => x"00",
-		BUS_DATA_IN => x"0000_0000",
-		BUS_DATA_OUT => open,
-		BUS_WRITE_EN_IN => '0',
-		BUS_READ_EN_IN => '0',
-		BUS_ACK_OUT => open,
-		-- gk 23.04.10
-		LED_PACKET_SENT_OUT => open,
-		LED_AN_DONE_N_OUT => open,
-		--------------------------
-		CTS_NUMBER_IN => CTS_NUMBER_IN,
-		CTS_CODE_IN => CTS_CODE_IN,
-		CTS_INFORMATION_IN => CTS_INFORMATION_IN,
-		CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
-		CTS_START_READOUT_IN => CTS_START_READOUT_IN,
-		CTS_DATA_OUT => CTS_DATA_OUT,
-		CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
-		CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
-		CTS_READ_IN => CTS_READ_IN,
-		CTS_LENGTH_OUT => CTS_LENGTH_OUT,
-		CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
-		FEE_DATA_IN => FEE_DATA_IN,
-		FEE_DATAREADY_IN => FEE_DATAREADY_IN,
-		FEE_READ_OUT => FEE_READ_OUT,
-		FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
-		FEE_BUSY_IN => FEE_BUSY_IN,
-		SFP_RXD_P_IN => SFP_RXD_P_IN,
-		SFP_RXD_N_IN => SFP_RXD_N_IN,
-		SFP_TXD_P_OUT => SFP_TXD_P_OUT,
-		SFP_TXD_N_OUT => SFP_TXD_N_OUT,
-		SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,
-		SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,
-		SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
-		SFP_LOS_IN => SFP_LOS_IN,
-		SFP_TXDIS_OUT => SFP_TXDIS_OUT,
-		IG_CTS_CTR_TST => IG_CTS_CTR_TST,
-		IG_REM_CTR_TST => IG_REM_CTR_TST,
-		IG_BSM_LOAD_TST => IG_BSM_LOAD_TST,
-		IG_BSM_SAVE_TST => IG_BSM_SAVE_TST,
-		IG_DATA_TST => IG_DATA_TST,
-		IG_WCNT_TST => IG_WCNT_TST,
-		IG_RCNT_TST => IG_RCNT_TST,
-		IG_RD_EN_TST => IG_RD_EN_TST,
-		IG_WR_EN_TST => IG_WR_EN_TST,
-		IG_EMPTY_TST => IG_EMPTY_TST,
-		IG_AEMPTY_TST => IG_AEMPTY_TST,
-		IG_FULL_TST => IG_FULL_TST,
-		IG_AFULL_TST => IG_AFULL_TST,
-		PC_WR_EN_TST => PC_WR_EN_TST,
-		PC_DATA_TST => PC_DATA_TST,
-		PC_READY_TST => PC_READY_TST,
-		PC_START_OF_SUB_TST => PC_START_OF_SUB_TST,
-		PC_END_OF_DATA_TST => PC_END_OF_DATA_TST,
-		PC_SUB_SIZE_TST => PC_SUB_SIZE_TST,
-		PC_TRIG_NR_TST => PC_TRIG_NR_TST,
-		PC_PADDING_TST => PC_PADDING_TST,
-		PC_DECODING_TST => PC_DECODING_TST,
-		PC_EVENT_ID_TST => PC_EVENT_ID_TST,
-		PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST,
-		PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST,
-		PC_BSM_LOAD_TST => PC_BSM_LOAD_TST,
-		PC_BSM_SAVE_TST => PC_BSM_SAVE_TST,
-		PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST,
-		PC_SHF_FULL_TST => PC_SHF_FULL_TST,
-		PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST,
-		PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST,
-		PC_SHF_Q_TST => PC_SHF_Q_TST,
-		PC_DF_EMPTY_TST => PC_DF_EMPTY_TST,
-		PC_DF_FULL_TST => PC_DF_FULL_TST,
-		PC_DF_WR_EN_TST => PC_DF_WR_EN_TST,
-		PC_DF_RD_EN_TST => PC_DF_RD_EN_TST,
-		PC_DF_Q_TST => PC_DF_Q_TST,
-		PC_ALL_CTR_TST => PC_ALL_CTR_TST,
-		PC_SUB_CTR_TST => PC_SUB_CTR_TST,
-		PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST,
-		PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST,
-		PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST,
-		PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST,
-		PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST,
-		PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST,
-		PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST,		
-		FC_WR_EN_TST => FC_WR_EN_TST,
-		FC_DATA_TST => FC_DATA_TST,
-		FC_H_READY_TST => FC_H_READY_TST,
-		FC_READY_TST => FC_READY_TST,
-		FC_IP_SIZE_TST => FC_IP_SIZE_TST,
-		FC_UDP_SIZE_TST => FC_UDP_SIZE_TST,
-		FC_IDENT_TST => FC_IDENT_TST,
-		FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST,
-		FC_SOD_TST => FC_SOD_TST,
-		FC_EOD_TST => FC_EOD_TST,
-		FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST,
-		FC_BSM_TRANS_TST => FC_BSM_TRANS_TST,
-		FT_DATA_TST => FT_DATA_TST,
-		FT_TX_EMPTY_TST => FT_TX_EMPTY_TST,
-		FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST,
-		FT_BSM_INIT_TST => FT_BSM_INIT_TST,
-		FT_BSM_MAC_TST => FT_BSM_MAC_TST,
-		FT_BSM_TRANS_TST => FT_BSM_TRANS_TST,
-		MAC_HADDR_TST => MAC_HADDR_TST,
-		MAC_HDATA_TST => MAC_HDATA_TST,
-		MAC_HCS_TST => MAC_HCS_TST,
-		MAC_HWRITE_TST => MAC_HWRITE_TST,
-		MAC_HREAD_TST => MAC_HREAD_TST,
-		MAC_HREADY_TST => MAC_HREADY_TST,
-		MAC_HDATA_EN_TST => MAC_HDATA_EN_TST,
-		MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST,
-		MAC_FIFOEOF_TST => MAC_FIFOEOF_TST,
-		MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST,
-		MAC_TX_READ_TST => MAC_TX_READ_TST,
-		MAC_TX_DONE_TST => MAC_TX_DONE_TST,
-		PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST,
-		PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST,
-		PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST,
-		ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT
-	);
-
-
-
--- 100 MHz system clock
-CLOCK_GEN_PROC: process
-begin
-	clk <= '1'; wait for 5.0 ns;
-	clk <= '0'; wait for 5.0 ns;
-end process CLOCK_GEN_PROC;
-
--- 125 MHz MAC clock
-CLOCK2_GEN_PROC: process
-begin
-	test_clk <= '1'; wait for 4.0 ns;
-	test_clk <= '0'; wait for 3.0 ns;
-end process CLOCK2_GEN_PROC;
-
--- Testbench
-TESTBENCH_PROC: process
--- test data from TRBnet
-variable test_data_len : integer range 0 to 65535 := 1;
-variable test_loop_len : integer range 0 to 65535 := 0;
-variable test_hdr_len : unsigned(15 downto 0) := x"0000";
-variable test_evt_len : unsigned(15 downto 0) := x"0000";
-variable test_data : unsigned(15 downto 0) := x"ffff";
-
-variable trigger_counter : unsigned(15 downto 0) := x"4710";
-variable trigger_loop : integer range 0 to 65535 := 15;
-
--- 1400 bytes MTU => 350 as limit for fragmentation
-variable max_event_size : real := 512.0;
-
-variable seed1 : positive; -- seed for random generator
-variable seed2 : positive; -- seed for random generator
-variable rand : real; -- random value (0.0 ... 1.0)
-variable int_rand : integer; -- random value, scaled to your needs
-variable cts_random_number : std_logic_vector(7 downto 0);
-
-variable stim : std_logic_vector(15 downto 0);
-
-
--- RND test
---UNIFORM(seed1, seed2, rand);
---int_rand := INTEGER(TRUNC(rand*65536.0));
---stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
-
-begin
-	-- Setup signals
-	reset <= '0';
-	gsr_n <= '1';
-	
-	stage_ctrl_regs_in <= x"0000_0000";
-	
-	--ip_cfg_start_in <= '0';
-	--ip_cfg_bank_sel_in <= x"0";
-	--ip_cfg_mem_data_in <= x"0000_0000";
-	mr_reset_in <= '0';
-	mr_mode_in <= '0';
-	mr_restart_in <= '0';
-	SLV_ADDR_IN <= x"00";
-	SLV_READ_IN <= '0';
-	SLV_WRITE_IN <= '0';
-	SLV_DATA_IN <= x"0000_0000";
-	
-	sfp_los_in <= '0'; -- signal from SFP is present
-	sfp_prsnt_n_in <= '0'; -- SFP itself is present
-	sfp_refclk_n_in <= '0';
-	sfp_refclk_p_in <= '1';
-	
-	cts_number_in <= x"0000";
-	cts_code_in <= x"00";
-	cts_information_in <= x"00";
-	cts_readout_type_in <= x"0";
-	cts_start_readout_in <= '0';
-	cts_read_in <= '0';
-	
-	fee_data_in <= x"0000";
-	fee_dataready_in <= '0';
-	fee_status_bits_in <= x"1234_5678";
-	fee_busy_in <= '0';
-	
-	wait for 22 ns;
-	
-	-- Reset the whole stuff
-	wait until rising_edge(clk);
-	reset <= '1';
-	gsr_n <= '0';
-	wait until rising_edge(clk);
-	wait until rising_edge(clk);
-	wait until rising_edge(clk);
-	reset <= '0';
-	gsr_n <= '1';
-	wait until rising_edge(clk);
-	--wait for 100 ns;
-	
-	-- Tests may start here
-	wait until ft_bsm_init_tst = x"7";
-
-	--ip_cfg_start_in <= '1';
-
-	wait for 500 ns;
-
-
--------------------------------------------------------------------------------
--- Loop the transmissions
--------------------------------------------------------------------------------
-	trigger_counter := x"4710";
-	trigger_loop    := 10;
-
-	MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
-		-- generate a real random byte for CTS
-		UNIFORM(seed1, seed2, rand);
-		int_rand := INTEGER(TRUNC(rand*256.0));
-		cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
-	
-		-- IPU transmission starts
-		wait until rising_edge(clk);
-		cts_number_in <= std_logic_vector( trigger_counter );
-		cts_code_in <= cts_random_number;
-		cts_information_in <= x"d1"; -- cts_information_in <= x"de"; -- gk 29.03.10
-		cts_readout_type_in <= x"1";
-		cts_start_readout_in <= '1';
-		wait until rising_edge(clk);
-		wait for 400 ns;
-
-		wait until rising_edge(clk);
-		fee_busy_in <= '1';
-		wait for 300 ns;
-		wait until rising_edge(clk);
-
-		-- ONE DATA TRANSMISSION
-		-- dice a length
-		UNIFORM(seed1, seed2, rand);
-		test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;
-		
-		test_data_len := 9685;
-		--test_data_len := 400;
-		
-		-- calculate the needed variables
-		test_loop_len := 2*(test_data_len - 1) + 1;
-		test_hdr_len := to_unsigned( test_data_len + 1, 16 );
-		test_evt_len := to_unsigned( test_data_len, 16 );
-
-		-- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
-		fee_dataready_in <= '1';
-		fee_data_in <= x"10" & cts_random_number;
-		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
-		fee_dataready_in <= '0';
-		wait until rising_edge(clk); -- BLA
-		wait until rising_edge(clk); -- BLA
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		fee_dataready_in <= '1';
-		fee_data_in <= std_logic_vector( trigger_counter );
-		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
-		fee_dataready_in <= '0';
-		wait until rising_edge(clk); -- BLA
-		wait until rising_edge(clk); -- BLA
-		wait until rising_edge(clk); -- BLA
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		fee_dataready_in <= '1';
-		fee_data_in <= std_logic_vector( test_hdr_len );
-		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
-		fee_data_in <= x"ff21";
-		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
-		fee_dataready_in <= '0';
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		fee_dataready_in <= '1';
-		fee_data_in <= std_logic_vector( test_evt_len );
-		wait until rising_edge(clk) and (fee_read_out = '1');
-		fee_data_in <= x"ff22";	
-		wait until rising_edge(clk) and (fee_read_out = '1');
-		fee_dataready_in <= '0';
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-
-		test_data     := x"ffff";
-		MY_DATA_LOOP: for J in 0 to test_loop_len loop
-			test_data := test_data + 1;
-			wait until rising_edge(clk);
-			fee_data_in <= std_logic_vector(test_data); 
-			if( (test_data MOD 5) = 0 ) then
-				fee_dataready_in <= '0';
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				wait until rising_edge(clk);
-				fee_dataready_in <= '1';
-			else
-				fee_dataready_in <= '1';
-			end if;
- 				--fee_dataready_in <= '1';
-		end loop MY_DATA_LOOP;
-		-- there must be padding words to get multiple of four LWs
-	
-		wait until rising_edge(clk);
-		fee_dataready_in <= '0';
-		fee_data_in <= x"0000";	
-
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		fee_busy_in <= '0';
-
-
-		trigger_loop    := trigger_loop + 1;
-		trigger_counter := trigger_counter + 1;
-
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		cts_read_in <= '1';
-		wait until rising_edge(clk);
-		cts_read_in <= '0';
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		cts_start_readout_in <= '0';
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);
-		wait until rising_edge(clk);	
-		
-		--wait for 8 us;
-
-	end loop MY_TRIGGER_LOOP;
-
---	wait for 8 us;
--------------------------------------------------------------------------------
--- end of loop
--------------------------------------------------------------------------------
-	-- Stay a while... stay forever!!!
-	wait;	
-	
-end process TESTBENCH_PROC;
-
-END;
-
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.math_real.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY testbench IS
+END testbench;
+
+ARCHITECTURE behavior OF testbench IS 
+	component trb_net16_gbe_buf is
+	generic( 
+		DO_SIMULATION		: integer range 0 to 1 := 1;
+		USE_125MHZ_EXTCLK       : integer range 0 to 1 := 1
+	);
+	port(
+		CLK							: in	std_logic;
+		TEST_CLK					: in	std_logic; -- only for simulation!
+		CLK_125_TX_IN				: in std_logic;  -- gk 28.04.01 used only in internal 125MHz clock mode
+		CLK_125_RX_IN				: in std_logic;  -- gk 28.04.01 used only in internal 125MHz clock mode
+		RESET : IN std_logic;
+		GSR_N : IN std_logic;
+		STAGE_CTRL_REGS_IN : IN std_logic_vector(31 downto 0);
+		------------------------
+		IP_CFG_START_IN : IN std_logic;
+		IP_CFG_BANK_SEL_IN : IN std_logic_vector(3 downto 0);
+		IP_CFG_MEM_DATA_IN : IN std_logic_vector(31 downto 0);
+		MR_RESET_IN : IN std_logic;
+		MR_MODE_IN : IN std_logic;
+		MR_RESTART_IN : IN std_logic;
+		IP_CFG_MEM_CLK_OUT : OUT std_logic;
+		IP_CFG_DONE_OUT : OUT std_logic;
+		IP_CFG_MEM_ADDR_OUT : OUT std_logic_vector(7 downto 0);
+		-- gk 29.03.10
+		SLV_ADDR_IN                  : in std_logic_vector(7 downto 0);
+		SLV_READ_IN                  : in std_logic;
+		SLV_WRITE_IN                 : in std_logic;
+		SLV_BUSY_OUT                 : out std_logic;
+		SLV_ACK_OUT                  : out std_logic;
+		SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
+		SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
+		-- gk 26.04.10
+		-- registers setup interface
+		BUS_ADDR_IN               : in std_logic_vector(7 downto 0);
+		BUS_DATA_IN               : in std_logic_vector(31 downto 0);
+		BUS_DATA_OUT              : out std_logic_vector(31 downto 0);  -- gk 26.04.10
+		BUS_WRITE_EN_IN           : in std_logic;  -- gk 26.04.10
+		BUS_READ_EN_IN            : in std_logic;  -- gk 26.04.10
+		BUS_ACK_OUT               : out std_logic;  -- gk 26.04.10
+		-- gk 23.04.10
+		LED_PACKET_SENT_OUT        : out std_logic;
+		LED_AN_DONE_N_OUT            : out std_logic;
+		------------------------
+		CTS_NUMBER_IN : IN std_logic_vector(15 downto 0);
+		CTS_CODE_IN : IN std_logic_vector(7 downto 0);
+		CTS_INFORMATION_IN : IN std_logic_vector(7 downto 0);
+		CTS_READOUT_TYPE_IN : IN std_logic_vector(3 downto 0);
+		CTS_START_READOUT_IN : IN std_logic;
+		CTS_READ_IN : IN std_logic;
+		FEE_DATA_IN : IN std_logic_vector(15 downto 0);
+		FEE_DATAREADY_IN : IN std_logic;
+		FEE_STATUS_BITS_IN : IN std_logic_vector(31 downto 0);
+		FEE_BUSY_IN : IN std_logic;
+		SFP_RXD_P_IN : IN std_logic;
+		SFP_RXD_N_IN : IN std_logic;
+		SFP_REFCLK_P_IN : IN std_logic;
+		SFP_REFCLK_N_IN : IN std_logic;
+		SFP_PRSNT_N_IN : IN std_logic;
+		SFP_LOS_IN : IN std_logic;          
+		STAGE_STAT_REGS_OUT : OUT std_logic_vector(31 downto 0);
+		CTS_DATA_OUT : OUT std_logic_vector(31 downto 0);
+		CTS_DATAREADY_OUT : OUT std_logic;
+		CTS_READOUT_FINISHED_OUT : OUT std_logic;
+		CTS_LENGTH_OUT : OUT std_logic_vector(15 downto 0);
+		CTS_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);
+		FEE_READ_OUT : OUT std_logic;
+		SFP_TXD_P_OUT : OUT std_logic;
+		SFP_TXD_N_OUT : OUT std_logic;
+		SFP_TXDIS_OUT : OUT std_logic;
+		IG_CTS_CTR_TST : OUT std_logic_vector(2 downto 0);
+		IG_REM_CTR_TST : OUT std_logic_vector(3 downto 0);
+		IG_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
+		IG_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
+		IG_DATA_TST : OUT std_logic_vector(15 downto 0);
+		IG_WCNT_TST : OUT std_logic_vector(15 downto 0);
+		IG_RCNT_TST : OUT std_logic_vector(16 downto 0);
+		IG_RD_EN_TST : OUT std_logic;
+		IG_WR_EN_TST : OUT std_logic;
+		IG_EMPTY_TST : OUT std_logic;
+		IG_AEMPTY_TST : OUT std_logic;
+		IG_FULL_TST : OUT std_logic;
+		IG_AFULL_TST : OUT std_logic;
+		PC_WR_EN_TST : OUT std_logic;
+		PC_DATA_TST : OUT std_logic_vector(7 downto 0);
+		PC_READY_TST : OUT std_logic;
+		PC_START_OF_SUB_TST : OUT std_logic;
+		PC_END_OF_DATA_TST : OUT std_logic;
+		PC_ALL_CTR_TST : OUT std_logic_vector(4 downto 0);
+		PC_SUB_CTR_TST : OUT std_logic_vector(4 downto 0);
+		PC_SUB_SIZE_TST : OUT std_logic_vector(31 downto 0);
+		PC_TRIG_NR_TST : OUT std_logic_vector(31 downto 0);
+		PC_PADDING_TST : OUT std_logic;
+		PC_DECODING_TST : OUT std_logic_vector(31 downto 0);
+		PC_EVENT_ID_TST : OUT std_logic_vector(31 downto 0);
+		PC_QUEUE_DEC_TST : OUT std_logic_vector(31 downto 0);
+		PC_BSM_CONSTR_TST : OUT std_logic_vector(3 downto 0);
+		PC_BSM_LOAD_TST : OUT std_logic_vector(3 downto 0);
+		PC_BSM_SAVE_TST : OUT std_logic_vector(3 downto 0);
+		PC_SHF_EMPTY_TST : OUT std_logic;
+		PC_SHF_FULL_TST : OUT std_logic;
+		PC_SHF_WR_EN_TST : OUT std_logic;
+		PC_SHF_RD_EN_TST : OUT std_logic;
+		PC_SHF_Q_TST : OUT std_logic_vector(7 downto 0);
+		PC_DF_EMPTY_TST : OUT std_logic;
+		PC_DF_FULL_TST : OUT std_logic;
+		PC_DF_WR_EN_TST : OUT std_logic;
+		PC_DF_RD_EN_TST : OUT std_logic;
+		PC_DF_Q_TST : OUT std_logic_vector(7 downto 0);
+		PC_BYTES_LOADED_TST : OUT std_logic_vector(15 downto 0);
+		PC_SIZE_LEFT_TST : OUT std_logic_vector(31 downto 0);
+		PC_SUB_SIZE_TO_SAVE_TST : OUT std_logic_vector(31 downto 0);
+		PC_SUB_SIZE_LOADED_TST : OUT std_logic_vector(31 downto 0);
+		PC_SUB_BYTES_LOADED_TST : OUT std_logic_vector(31 downto 0);
+		PC_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
+		PC_ACT_QUEUE_SIZE_TST : OUT std_logic_vector(31 downto 0);
+		FC_WR_EN_TST : OUT std_logic;
+		FC_DATA_TST : OUT std_logic_vector(7 downto 0);
+		FC_H_READY_TST : OUT std_logic;
+		FC_READY_TST : OUT std_logic;
+		FC_IP_SIZE_TST : OUT std_logic_vector(15 downto 0);
+		FC_UDP_SIZE_TST : OUT std_logic_vector(15 downto 0);
+		FC_IDENT_TST : OUT std_logic_vector(15 downto 0);
+		FC_FLAGS_OFFSET_TST : OUT std_logic_vector(15 downto 0);
+		FC_SOD_TST : OUT std_logic;
+		FC_EOD_TST : OUT std_logic;
+		FC_BSM_CONSTR_TST : OUT std_logic_vector(7 downto 0);
+		FC_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
+		FT_DATA_TST : OUT std_logic_vector(8 downto 0);
+		FT_TX_EMPTY_TST : OUT std_logic;
+		FT_START_OF_PACKET_TST : OUT std_logic;
+		FT_BSM_INIT_TST : OUT std_logic_vector(3 downto 0);
+		FT_BSM_MAC_TST : OUT std_logic_vector(3 downto 0);
+		FT_BSM_TRANS_TST : OUT std_logic_vector(3 downto 0);
+		MAC_HADDR_TST : OUT std_logic_vector(7 downto 0);
+		MAC_HDATA_TST : OUT std_logic_vector(7 downto 0);
+		MAC_HCS_TST : OUT std_logic;
+		MAC_HWRITE_TST : OUT std_logic;
+		MAC_HREAD_TST : OUT std_logic;
+		MAC_HREADY_TST : OUT std_logic;
+		MAC_HDATA_EN_TST : OUT std_logic;
+		MAC_FIFOAVAIL_TST : OUT std_logic;
+		MAC_FIFOEOF_TST : OUT std_logic;
+		MAC_FIFOEMPTY_TST : OUT std_logic;
+		MAC_TX_READ_TST : OUT std_logic;
+		MAC_TX_DONE_TST : OUT std_logic;
+		PCS_AN_LP_ABILITY_TST : OUT std_logic_vector(15 downto 0);
+		PCS_AN_COMPLETE_TST : OUT std_logic;
+		PCS_AN_PAGE_RX_TST : OUT std_logic;
+		ANALYZER_DEBUG_OUT : OUT std_logic_vector(63 downto 0)
+		);
+	END COMPONENT;
+
+	SIGNAL CLK :  std_logic;
+	SIGNAL TEST_CLK :  std_logic;
+	SIGNAL RESET :  std_logic;
+	SIGNAL GSR_N :  std_logic;
+	SIGNAL STAGE_STAT_REGS_OUT :  std_logic_vector(31 downto 0);
+	SIGNAL STAGE_CTRL_REGS_IN :  std_logic_vector(31 downto 0);
+	SIGNAL IP_CFG_START_IN :  std_logic;
+	SIGNAL IP_CFG_BANK_SEL_IN :  std_logic_vector(3 downto 0);
+	SIGNAL IP_CFG_MEM_DATA_IN :  std_logic_vector(31 downto 0);
+	SIGNAL MR_RESET_IN :  std_logic;
+	SIGNAL MR_MODE_IN :  std_logic;
+	SIGNAL MR_RESTART_IN :  std_logic;
+	SIGNAL IP_CFG_MEM_CLK_OUT :  std_logic;
+	SIGNAL IP_CFG_DONE_OUT :  std_logic;
+	SIGNAL IP_CFG_MEM_ADDR_OUT :  std_logic_vector(7 downto 0);
+	SIGNAL CTS_NUMBER_IN :  std_logic_vector(15 downto 0);
+	SIGNAL CTS_CODE_IN :  std_logic_vector(7 downto 0);
+	SIGNAL CTS_INFORMATION_IN :  std_logic_vector(7 downto 0);
+	SIGNAL CTS_READOUT_TYPE_IN :  std_logic_vector(3 downto 0);
+	SIGNAL CTS_START_READOUT_IN :  std_logic;
+	SIGNAL CTS_DATA_OUT :  std_logic_vector(31 downto 0);
+	SIGNAL CTS_DATAREADY_OUT :  std_logic;
+	SIGNAL CTS_READOUT_FINISHED_OUT :  std_logic;
+	SIGNAL CTS_READ_IN :  std_logic;
+	SIGNAL CTS_LENGTH_OUT :  std_logic_vector(15 downto 0);
+	SIGNAL CTS_ERROR_PATTERN_OUT :  std_logic_vector(31 downto 0);
+	SIGNAL FEE_DATA_IN :  std_logic_vector(15 downto 0);
+	SIGNAL FEE_DATAREADY_IN :  std_logic;
+	SIGNAL FEE_READ_OUT :  std_logic;
+	SIGNAL FEE_STATUS_BITS_IN :  std_logic_vector(31 downto 0);
+	SIGNAL FEE_BUSY_IN :  std_logic;
+	SIGNAL SFP_RXD_P_IN :  std_logic;
+	SIGNAL SFP_RXD_N_IN :  std_logic;
+	SIGNAL SFP_TXD_P_OUT :  std_logic;
+	SIGNAL SFP_TXD_N_OUT :  std_logic;
+	SIGNAL SFP_REFCLK_P_IN :  std_logic;
+	SIGNAL SFP_REFCLK_N_IN :  std_logic;
+	SIGNAL SFP_PRSNT_N_IN :  std_logic;
+	SIGNAL SFP_LOS_IN :  std_logic;
+	SIGNAL SFP_TXDIS_OUT :  std_logic;
+	SIGNAL IG_CTS_CTR_TST :  std_logic_vector(2 downto 0);
+	SIGNAL IG_REM_CTR_TST :  std_logic_vector(3 downto 0);
+	SIGNAL IG_BSM_LOAD_TST :  std_logic_vector(3 downto 0);
+	SIGNAL IG_BSM_SAVE_TST :  std_logic_vector(3 downto 0);
+	SIGNAL IG_DATA_TST :  std_logic_vector(15 downto 0);
+	SIGNAL IG_WCNT_TST :  std_logic_vector(15 downto 0);
+	SIGNAL IG_RCNT_TST :  std_logic_vector(16 downto 0);
+	SIGNAL IG_RD_EN_TST :  std_logic;
+	SIGNAL IG_WR_EN_TST :  std_logic;
+	SIGNAL IG_EMPTY_TST :  std_logic;
+	SIGNAL IG_AEMPTY_TST :  std_logic;
+	SIGNAL IG_FULL_TST :  std_logic;
+	SIGNAL IG_AFULL_TST :  std_logic;
+	SIGNAL PC_WR_EN_TST :  std_logic;
+	SIGNAL PC_DATA_TST :  std_logic_vector(7 downto 0);
+	SIGNAL PC_READY_TST :  std_logic;
+	SIGNAL PC_START_OF_SUB_TST :  std_logic;
+	SIGNAL PC_END_OF_DATA_TST :  std_logic;
+	SIGNAL PC_SUB_SIZE_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_TRIG_NR_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_PADDING_TST :  std_logic;
+	SIGNAL PC_DECODING_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_EVENT_ID_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_QUEUE_DEC_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_BSM_CONSTR_TST :  std_logic_vector(3 downto 0);
+	SIGNAL PC_BSM_LOAD_TST :  std_logic_vector(3 downto 0);
+	SIGNAL PC_BSM_SAVE_TST :  std_logic_vector(3 downto 0);
+	SIGNAL PC_SHF_EMPTY_TST :  std_logic;
+	SIGNAL PC_SHF_FULL_TST :  std_logic;
+	SIGNAL PC_SHF_WR_EN_TST :  std_logic;
+	SIGNAL PC_SHF_RD_EN_TST :  std_logic;
+	SIGNAL PC_SHF_Q_TST :  std_logic_vector(7 downto 0);
+	SIGNAL PC_DF_EMPTY_TST :  std_logic;
+	SIGNAL PC_DF_FULL_TST :  std_logic;
+	SIGNAL PC_DF_WR_EN_TST :  std_logic;
+	SIGNAL PC_DF_RD_EN_TST :  std_logic;
+	SIGNAL PC_DF_Q_TST :  std_logic_vector(7 downto 0); 
+	SIGNAL PC_ALL_CTR_TST :  std_logic_vector(4 downto 0);
+	SIGNAL PC_SUB_CTR_TST :  std_logic_vector(4 downto 0);
+	SIGNAL PC_BYTES_LOADED_TST :  std_logic_vector(15 downto 0);
+	SIGNAL PC_SIZE_LEFT_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_SUB_SIZE_TO_SAVE_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_SUB_SIZE_LOADED_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_SUB_BYTES_LOADED_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_QUEUE_SIZE_TST :  std_logic_vector(31 downto 0);
+	SIGNAL PC_ACT_QUEUE_SIZE_TST :  std_logic_vector(31 downto 0);
+	SIGNAL FC_WR_EN_TST :  std_logic;
+	SIGNAL FC_DATA_TST :  std_logic_vector(7 downto 0);
+	SIGNAL FC_H_READY_TST :  std_logic;
+	SIGNAL FC_READY_TST :  std_logic;
+	SIGNAL FC_IP_SIZE_TST :  std_logic_vector(15 downto 0);
+	SIGNAL FC_UDP_SIZE_TST :  std_logic_vector(15 downto 0);
+	SIGNAL FC_IDENT_TST :  std_logic_vector(15 downto 0);
+	SIGNAL FC_FLAGS_OFFSET_TST :  std_logic_vector(15 downto 0);
+	SIGNAL FC_SOD_TST :  std_logic;
+	SIGNAL FC_EOD_TST :  std_logic;
+	SIGNAL FC_BSM_CONSTR_TST :  std_logic_vector(7 downto 0);
+	SIGNAL FC_BSM_TRANS_TST :  std_logic_vector(3 downto 0);
+	SIGNAL FT_DATA_TST :  std_logic_vector(8 downto 0);
+	SIGNAL FT_TX_EMPTY_TST :  std_logic;
+	SIGNAL FT_START_OF_PACKET_TST :  std_logic;
+	SIGNAL FT_BSM_INIT_TST :  std_logic_vector(3 downto 0);
+	SIGNAL FT_BSM_MAC_TST :  std_logic_vector(3 downto 0);
+	SIGNAL FT_BSM_TRANS_TST :  std_logic_vector(3 downto 0);
+	SIGNAL MAC_HADDR_TST :  std_logic_vector(7 downto 0);
+	SIGNAL MAC_HDATA_TST :  std_logic_vector(7 downto 0);
+	SIGNAL MAC_HCS_TST :  std_logic;
+	SIGNAL MAC_HWRITE_TST :  std_logic;
+	SIGNAL MAC_HREAD_TST :  std_logic;
+	SIGNAL MAC_HREADY_TST :  std_logic;
+	SIGNAL MAC_HDATA_EN_TST :  std_logic;
+	SIGNAL MAC_FIFOAVAIL_TST :  std_logic;
+	SIGNAL MAC_FIFOEOF_TST :  std_logic;
+	SIGNAL MAC_FIFOEMPTY_TST :  std_logic;
+	SIGNAL MAC_TX_READ_TST :  std_logic;
+	SIGNAL MAC_TX_DONE_TST :  std_logic;
+	SIGNAL PCS_AN_LP_ABILITY_TST :  std_logic_vector(15 downto 0);
+	SIGNAL PCS_AN_COMPLETE_TST :  std_logic;
+	SIGNAL PCS_AN_PAGE_RX_TST :  std_logic;
+	SIGNAL ANALYZER_DEBUG_OUT :  std_logic_vector(63 downto 0);
+	--gk 29.03.10
+	signal SLV_ADDR_IN : std_logic_vector(7 downto 0);
+	signal SLV_READ_IN : std_logic;
+	signal SLV_WRITE_IN : std_logic;
+	signal SLV_BUSY_OUT : std_logic;
+	signal SLV_ACK_OUT : std_logic;
+	signal SLV_DATA_IN : std_logic_vector(31 downto 0);
+	signal SLV_DATA_OUT : std_logic_vector(31 downto 0);
+
+BEGIN
+
+-- Please check and add your generic clause manually
+	uut: trb_net16_gbe_buf
+	GENERIC MAP( DO_SIMULATION => 1, USE_125MHZ_EXTCLK => 1 )
+	PORT MAP(
+		CLK => CLK,
+		CLK_125_TX_IN => '0',
+		CLK_125_RX_IN => '0',
+		TEST_CLK => TEST_CLK,
+		RESET => RESET,
+		GSR_N => GSR_N,
+		STAGE_STAT_REGS_OUT => STAGE_STAT_REGS_OUT,
+		STAGE_CTRL_REGS_IN => STAGE_CTRL_REGS_IN,
+		IP_CFG_START_IN => IP_CFG_START_IN,
+		IP_CFG_BANK_SEL_IN => IP_CFG_BANK_SEL_IN,
+		IP_CFG_MEM_DATA_IN => IP_CFG_MEM_DATA_IN,
+		MR_RESET_IN => MR_RESET_IN,
+		MR_MODE_IN => MR_MODE_IN,
+		MR_RESTART_IN => MR_RESTART_IN,
+		IP_CFG_MEM_CLK_OUT => IP_CFG_MEM_CLK_OUT,
+		IP_CFG_DONE_OUT => IP_CFG_DONE_OUT,
+		IP_CFG_MEM_ADDR_OUT => IP_CFG_MEM_ADDR_OUT,
+		-- gk 29.03.10
+		SLV_ADDR_IN => SLV_ADDR_IN,
+		SLV_READ_IN => SLV_READ_IN,
+		SLV_WRITE_IN => SLV_WRITE_IN,
+		SLV_BUSY_OUT => SLV_BUSY_OUT,
+		SLV_ACK_OUT => SLV_ACK_OUT,
+		SLV_DATA_IN => SLV_DATA_IN,
+		SLV_DATA_OUT => SLV_DATA_OUT,
+		-- gk 22.04.10
+		-- registers setup interface
+		BUS_ADDR_IN => x"00",
+		BUS_DATA_IN => x"0000_0000",
+		BUS_DATA_OUT => open,
+		BUS_WRITE_EN_IN => '0',
+		BUS_READ_EN_IN => '0',
+		BUS_ACK_OUT => open,
+		-- gk 23.04.10
+		LED_PACKET_SENT_OUT => open,
+		LED_AN_DONE_N_OUT => open,
+		--------------------------
+		CTS_NUMBER_IN => CTS_NUMBER_IN,
+		CTS_CODE_IN => CTS_CODE_IN,
+		CTS_INFORMATION_IN => CTS_INFORMATION_IN,
+		CTS_READOUT_TYPE_IN => CTS_READOUT_TYPE_IN,
+		CTS_START_READOUT_IN => CTS_START_READOUT_IN,
+		CTS_DATA_OUT => CTS_DATA_OUT,
+		CTS_DATAREADY_OUT => CTS_DATAREADY_OUT,
+		CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+		CTS_READ_IN => CTS_READ_IN,
+		CTS_LENGTH_OUT => CTS_LENGTH_OUT,
+		CTS_ERROR_PATTERN_OUT => CTS_ERROR_PATTERN_OUT,
+		FEE_DATA_IN => FEE_DATA_IN,
+		FEE_DATAREADY_IN => FEE_DATAREADY_IN,
+		FEE_READ_OUT => FEE_READ_OUT,
+		FEE_STATUS_BITS_IN => FEE_STATUS_BITS_IN,
+		FEE_BUSY_IN => FEE_BUSY_IN,
+		SFP_RXD_P_IN => SFP_RXD_P_IN,
+		SFP_RXD_N_IN => SFP_RXD_N_IN,
+		SFP_TXD_P_OUT => SFP_TXD_P_OUT,
+		SFP_TXD_N_OUT => SFP_TXD_N_OUT,
+		SFP_REFCLK_P_IN => SFP_REFCLK_P_IN,
+		SFP_REFCLK_N_IN => SFP_REFCLK_N_IN,
+		SFP_PRSNT_N_IN => SFP_PRSNT_N_IN,
+		SFP_LOS_IN => SFP_LOS_IN,
+		SFP_TXDIS_OUT => SFP_TXDIS_OUT,
+		IG_CTS_CTR_TST => IG_CTS_CTR_TST,
+		IG_REM_CTR_TST => IG_REM_CTR_TST,
+		IG_BSM_LOAD_TST => IG_BSM_LOAD_TST,
+		IG_BSM_SAVE_TST => IG_BSM_SAVE_TST,
+		IG_DATA_TST => IG_DATA_TST,
+		IG_WCNT_TST => IG_WCNT_TST,
+		IG_RCNT_TST => IG_RCNT_TST,
+		IG_RD_EN_TST => IG_RD_EN_TST,
+		IG_WR_EN_TST => IG_WR_EN_TST,
+		IG_EMPTY_TST => IG_EMPTY_TST,
+		IG_AEMPTY_TST => IG_AEMPTY_TST,
+		IG_FULL_TST => IG_FULL_TST,
+		IG_AFULL_TST => IG_AFULL_TST,
+		PC_WR_EN_TST => PC_WR_EN_TST,
+		PC_DATA_TST => PC_DATA_TST,
+		PC_READY_TST => PC_READY_TST,
+		PC_START_OF_SUB_TST => PC_START_OF_SUB_TST,
+		PC_END_OF_DATA_TST => PC_END_OF_DATA_TST,
+		PC_SUB_SIZE_TST => PC_SUB_SIZE_TST,
+		PC_TRIG_NR_TST => PC_TRIG_NR_TST,
+		PC_PADDING_TST => PC_PADDING_TST,
+		PC_DECODING_TST => PC_DECODING_TST,
+		PC_EVENT_ID_TST => PC_EVENT_ID_TST,
+		PC_QUEUE_DEC_TST => PC_QUEUE_DEC_TST,
+		PC_BSM_CONSTR_TST => PC_BSM_CONSTR_TST,
+		PC_BSM_LOAD_TST => PC_BSM_LOAD_TST,
+		PC_BSM_SAVE_TST => PC_BSM_SAVE_TST,
+		PC_SHF_EMPTY_TST => PC_SHF_EMPTY_TST,
+		PC_SHF_FULL_TST => PC_SHF_FULL_TST,
+		PC_SHF_WR_EN_TST => PC_SHF_WR_EN_TST,
+		PC_SHF_RD_EN_TST => PC_SHF_RD_EN_TST,
+		PC_SHF_Q_TST => PC_SHF_Q_TST,
+		PC_DF_EMPTY_TST => PC_DF_EMPTY_TST,
+		PC_DF_FULL_TST => PC_DF_FULL_TST,
+		PC_DF_WR_EN_TST => PC_DF_WR_EN_TST,
+		PC_DF_RD_EN_TST => PC_DF_RD_EN_TST,
+		PC_DF_Q_TST => PC_DF_Q_TST,
+		PC_ALL_CTR_TST => PC_ALL_CTR_TST,
+		PC_SUB_CTR_TST => PC_SUB_CTR_TST,
+		PC_BYTES_LOADED_TST => PC_BYTES_LOADED_TST,
+		PC_SIZE_LEFT_TST => PC_SIZE_LEFT_TST,
+		PC_SUB_SIZE_TO_SAVE_TST => PC_SUB_SIZE_TO_SAVE_TST,
+		PC_SUB_SIZE_LOADED_TST => PC_SUB_SIZE_LOADED_TST,
+		PC_SUB_BYTES_LOADED_TST => PC_SUB_BYTES_LOADED_TST,
+		PC_QUEUE_SIZE_TST => PC_QUEUE_SIZE_TST,
+		PC_ACT_QUEUE_SIZE_TST => PC_ACT_QUEUE_SIZE_TST,		
+		FC_WR_EN_TST => FC_WR_EN_TST,
+		FC_DATA_TST => FC_DATA_TST,
+		FC_H_READY_TST => FC_H_READY_TST,
+		FC_READY_TST => FC_READY_TST,
+		FC_IP_SIZE_TST => FC_IP_SIZE_TST,
+		FC_UDP_SIZE_TST => FC_UDP_SIZE_TST,
+		FC_IDENT_TST => FC_IDENT_TST,
+		FC_FLAGS_OFFSET_TST => FC_FLAGS_OFFSET_TST,
+		FC_SOD_TST => FC_SOD_TST,
+		FC_EOD_TST => FC_EOD_TST,
+		FC_BSM_CONSTR_TST => FC_BSM_CONSTR_TST,
+		FC_BSM_TRANS_TST => FC_BSM_TRANS_TST,
+		FT_DATA_TST => FT_DATA_TST,
+		FT_TX_EMPTY_TST => FT_TX_EMPTY_TST,
+		FT_START_OF_PACKET_TST => FT_START_OF_PACKET_TST,
+		FT_BSM_INIT_TST => FT_BSM_INIT_TST,
+		FT_BSM_MAC_TST => FT_BSM_MAC_TST,
+		FT_BSM_TRANS_TST => FT_BSM_TRANS_TST,
+		MAC_HADDR_TST => MAC_HADDR_TST,
+		MAC_HDATA_TST => MAC_HDATA_TST,
+		MAC_HCS_TST => MAC_HCS_TST,
+		MAC_HWRITE_TST => MAC_HWRITE_TST,
+		MAC_HREAD_TST => MAC_HREAD_TST,
+		MAC_HREADY_TST => MAC_HREADY_TST,
+		MAC_HDATA_EN_TST => MAC_HDATA_EN_TST,
+		MAC_FIFOAVAIL_TST => MAC_FIFOAVAIL_TST,
+		MAC_FIFOEOF_TST => MAC_FIFOEOF_TST,
+		MAC_FIFOEMPTY_TST => MAC_FIFOEMPTY_TST,
+		MAC_TX_READ_TST => MAC_TX_READ_TST,
+		MAC_TX_DONE_TST => MAC_TX_DONE_TST,
+		PCS_AN_LP_ABILITY_TST => PCS_AN_LP_ABILITY_TST,
+		PCS_AN_COMPLETE_TST => PCS_AN_COMPLETE_TST,
+		PCS_AN_PAGE_RX_TST => PCS_AN_PAGE_RX_TST,
+		ANALYZER_DEBUG_OUT => ANALYZER_DEBUG_OUT
+	);
+
+
+
+-- 100 MHz system clock
+CLOCK_GEN_PROC: process
+begin
+	clk <= '1'; wait for 5.0 ns;
+	clk <= '0'; wait for 5.0 ns;
+end process CLOCK_GEN_PROC;
+
+-- 125 MHz MAC clock
+CLOCK2_GEN_PROC: process
+begin
+	test_clk <= '1'; wait for 4.0 ns;
+	test_clk <= '0'; wait for 3.0 ns;
+end process CLOCK2_GEN_PROC;
+
+-- Testbench
+TESTBENCH_PROC: process
+-- test data from TRBnet
+variable test_data_len : integer range 0 to 65535 := 1;
+variable test_loop_len : integer range 0 to 65535 := 0;
+variable test_hdr_len : unsigned(15 downto 0) := x"0000";
+variable test_evt_len : unsigned(15 downto 0) := x"0000";
+variable test_data : unsigned(15 downto 0) := x"ffff";
+
+variable trigger_counter : unsigned(15 downto 0) := x"4710";
+variable trigger_loop : integer range 0 to 65535 := 15;
+
+-- 1400 bytes MTU => 350 as limit for fragmentation
+variable max_event_size : real := 512.0;
+
+variable seed1 : positive; -- seed for random generator
+variable seed2 : positive; -- seed for random generator
+variable rand : real; -- random value (0.0 ... 1.0)
+variable int_rand : integer; -- random value, scaled to your needs
+variable cts_random_number : std_logic_vector(7 downto 0);
+
+variable stim : std_logic_vector(15 downto 0);
+
+
+-- RND test
+--UNIFORM(seed1, seed2, rand);
+--int_rand := INTEGER(TRUNC(rand*65536.0));
+--stim := std_logic_vector(to_unsigned(int_rand, stim'LENGTH));
+
+begin
+	-- Setup signals
+	reset <= '0';
+	gsr_n <= '1';
+	
+	stage_ctrl_regs_in <= x"0000_0000";
+	
+	--ip_cfg_start_in <= '0';
+	--ip_cfg_bank_sel_in <= x"0";
+	--ip_cfg_mem_data_in <= x"0000_0000";
+	mr_reset_in <= '0';
+	mr_mode_in <= '0';
+	mr_restart_in <= '0';
+	SLV_ADDR_IN <= x"00";
+	SLV_READ_IN <= '0';
+	SLV_WRITE_IN <= '0';
+	SLV_DATA_IN <= x"0000_0000";
+	
+	sfp_los_in <= '0'; -- signal from SFP is present
+	sfp_prsnt_n_in <= '0'; -- SFP itself is present
+	sfp_refclk_n_in <= '0';
+	sfp_refclk_p_in <= '1';
+	
+	cts_number_in <= x"0000";
+	cts_code_in <= x"00";
+	cts_information_in <= x"00";
+	cts_readout_type_in <= x"0";
+	cts_start_readout_in <= '0';
+	cts_read_in <= '0';
+	
+	fee_data_in <= x"0000";
+	fee_dataready_in <= '0';
+	fee_status_bits_in <= x"1234_5678";
+	fee_busy_in <= '0';
+	
+	wait for 22 ns;
+	
+	-- Reset the whole stuff
+	wait until rising_edge(clk);
+	reset <= '1';
+	gsr_n <= '0';
+	wait until rising_edge(clk);
+	wait until rising_edge(clk);
+	wait until rising_edge(clk);
+	reset <= '0';
+	gsr_n <= '1';
+	wait until rising_edge(clk);
+	--wait for 100 ns;
+	
+	-- Tests may start here
+	wait until ft_bsm_init_tst = x"7";
+
+	--ip_cfg_start_in <= '1';
+
+	wait for 500 ns;
+
+
+-------------------------------------------------------------------------------
+-- Loop the transmissions
+-------------------------------------------------------------------------------
+	trigger_counter := x"4710";
+	trigger_loop    := 10;
+
+	MY_TRIGGER_LOOP: for J in 0 to trigger_loop loop
+		-- generate a real random byte for CTS
+		UNIFORM(seed1, seed2, rand);
+		int_rand := INTEGER(TRUNC(rand*256.0));
+		cts_random_number := std_logic_vector(to_unsigned(int_rand, cts_random_number'LENGTH));
+	
+		-- IPU transmission starts
+		wait until rising_edge(clk);
+		cts_number_in <= std_logic_vector( trigger_counter );
+		cts_code_in <= cts_random_number;
+		cts_information_in <= x"d2"; -- cts_information_in <= x"de"; -- gk 29.03.10
+		cts_readout_type_in <= x"1";
+		cts_start_readout_in <= '1';
+		wait until rising_edge(clk);
+		wait for 400 ns;
+
+		wait until rising_edge(clk);
+		fee_busy_in <= '1';
+		wait for 300 ns;
+		wait until rising_edge(clk);
+
+		-- ONE DATA TRANSMISSION
+		-- dice a length
+		UNIFORM(seed1, seed2, rand);
+		test_data_len := INTEGER(TRUNC(rand*max_event_size)) + 1;
+		
+		test_data_len := 9685;
+		--test_data_len := 400;
+		
+		-- calculate the needed variables
+		test_loop_len := 2*(test_data_len - 1) + 1;
+		test_hdr_len := to_unsigned( test_data_len + 1, 16 );
+		test_evt_len := to_unsigned( test_data_len, 16 );
+
+		-- original data block (trigger 1, random 0xaa, number 0x4711, source 0x21)
+		fee_dataready_in <= '1';
+		fee_data_in <= x"10" & cts_random_number;
+		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of first data word
+		fee_dataready_in <= '0';
+		wait until rising_edge(clk); -- BLA
+		wait until rising_edge(clk); -- BLA
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		fee_dataready_in <= '1';
+		fee_data_in <= std_logic_vector( trigger_counter );
+		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of second data word
+		fee_dataready_in <= '0';
+		wait until rising_edge(clk); -- BLA
+		wait until rising_edge(clk); -- BLA
+		wait until rising_edge(clk); -- BLA
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		fee_dataready_in <= '1';
+		fee_data_in <= std_logic_vector( test_hdr_len );
+		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of third data word
+		fee_data_in <= x"ff21";
+		wait until rising_edge(clk) and (fee_read_out = '1'); -- transfer of fourth data word
+		fee_dataready_in <= '0';
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		fee_dataready_in <= '1';
+		fee_data_in <= std_logic_vector( test_evt_len );
+		wait until rising_edge(clk) and (fee_read_out = '1');
+		fee_data_in <= x"ff22";	
+		wait until rising_edge(clk) and (fee_read_out = '1');
+		fee_dataready_in <= '0';
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+
+		test_data     := x"ffff";
+		MY_DATA_LOOP: for J in 0 to test_loop_len loop
+			test_data := test_data + 1;
+			wait until rising_edge(clk);
+			fee_data_in <= std_logic_vector(test_data); 
+			if( (test_data MOD 5) = 0 ) then
+				fee_dataready_in <= '0';
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				wait until rising_edge(clk);
+				fee_dataready_in <= '1';
+			else
+				fee_dataready_in <= '1';
+			end if;
+ 				--fee_dataready_in <= '1';
+		end loop MY_DATA_LOOP;
+		-- there must be padding words to get multiple of four LWs
+	
+		wait until rising_edge(clk);
+		fee_dataready_in <= '0';
+		fee_data_in <= x"0000";	
+
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		fee_busy_in <= '0';
+
+
+		trigger_loop    := trigger_loop + 1;
+		trigger_counter := trigger_counter + 1;
+
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		cts_read_in <= '1';
+		wait until rising_edge(clk);
+		cts_read_in <= '0';
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		cts_start_readout_in <= '0';
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);
+		wait until rising_edge(clk);	
+		
+		--wait for 8 us;
+
+	end loop MY_TRIGGER_LOOP;
+
+--	wait for 8 us;
+-------------------------------------------------------------------------------
+-- end of loop
+-------------------------------------------------------------------------------
+	-- Stay a while... stay forever!!!
+	wait;	
+	
+end process TESTBENCH_PROC;
+
+END;
+
diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd
index 74ad3e3..9906432 100755
--- a/gbe_ecp2m/trb_net16_gbe_buf.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd
@@ -248,7 +248,7 @@ port(
 	DBG_SF_AEMPTY_OUT			: out	std_logic;
 	DBG_SF_FULL_OUT				: out	std_logic;
 	DBG_SF_AFULL_OUT			: out	std_logic;
-	DEBUG_OUT				: out	std_logic_vector(31 downto 0)	
+	DEBUG_OUT				: out	std_logic_vector(63 downto 0)	
 );
 end component;
 
@@ -331,7 +331,7 @@ port (
 	DBG_SUB_BYTES_LOADED	: out	std_logic_vector(31 downto 0);
 	DBG_QUEUE_SIZE			: out	std_logic_vector(31 downto 0);
 	DBG_ACT_QUEUE_SIZE		: out	std_logic_vector(31 downto 0);
-	DEBUG_OUT				: out	std_logic_vector(31 downto 0)
+	DEBUG_OUT				: out	std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -374,7 +374,7 @@ port (
 	-- debug ports
 	BSM_CONSTR_OUT			: out	std_logic_vector(7 downto 0);
 	BSM_TRANS_OUT			: out	std_logic_vector(3 downto 0);
-	DEBUG_OUT				: out std_logic_vector(31 downto 0)
+	DEBUG_OUT				: out std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -405,7 +405,7 @@ port (
 	DBG_RD_DONE_OUT			: out	std_logic;
 	DBG_INIT_DONE_OUT		: out	std_logic;
 	DBG_ENABLED_OUT			: out	std_logic;
-	DEBUG_OUT				: out	std_logic_vector(31 downto 0)
+	DEBUG_OUT				: out	std_logic_vector(63 downto 0)
 );
 end component;
 
@@ -624,7 +624,16 @@ port(
 	GBE_USE_MULTIEVENTS_OUT   : out std_logic;
 	GBE_READOUT_CTR_OUT       : out std_logic_vector(23 downto 0);  -- gk 26.04.10
 	GBE_READOUT_CTR_VALID_OUT : out std_logic;  -- gk 26.04.10
-	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0)
+	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0);
+	-- gk 01.06.10
+	DBG_IPU2GBE1_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE2_IN          : in std_logic_vector(31 downto 0);
+	DBG_PC1_IN               : in std_logic_vector(31 downto 0);
+	DBG_PC2_IN               : in std_logic_vector(31 downto 0);
+	DBG_FC1_IN               : in std_logic_vector(31 downto 0);
+	DBG_FC2_IN               : in std_logic_vector(31 downto 0);
+	DBG_FT1_IN               : in std_logic_vector(31 downto 0);
+	DBG_FT2_IN               : in std_logic_vector(31 downto 0)
 );
 end component;
 
@@ -770,6 +779,19 @@ signal gbe_trig_nr                   : std_logic_vector(31 downto 0);
 signal pc_delay                      : std_logic_vector(31 downto 0);
 -- gk 04.05.10
 signal ft_eod                        : std_logic;
+-- gk 01.06.10
+signal dbg_ipu2gbe1                  : std_logic_vector(31 downto 0);
+signal dbg_ipu2gbe2                  : std_logic_vector(31 downto 0);
+signal dbg_pc1                       : std_logic_vector(31 downto 0);
+signal dbg_pc2                       : std_logic_vector(31 downto 0);
+signal dbg_fc1                       : std_logic_vector(31 downto 0);
+signal dbg_fc2                       : std_logic_vector(31 downto 0);
+signal dbg_ft1                       : std_logic_vector(31 downto 0);
+signal dbg_ft2                       : std_logic_vector(31 downto 0);
+-- gk 08.06.10
+signal mac_tx_staten                 : std_logic;
+signal mac_tx_statevec               : std_logic_vector(30 downto 0);
+signal mac_tx_discfrm                : std_logic;
 
 begin
 
@@ -820,7 +842,16 @@ port map(
 	GBE_USE_MULTIEVENTS_OUT   => use_multievents,
 	GBE_READOUT_CTR_OUT       => readout_ctr,  -- gk 26.04.10
 	GBE_READOUT_CTR_VALID_OUT => readout_ctr_valid,  -- gk 26.04.10
-	GBE_DELAY_OUT             => pc_delay
+	GBE_DELAY_OUT             => pc_delay,
+	-- gk 01.06.10
+	DBG_IPU2GBE1_IN           => dbg_ipu2gbe1,
+	DBG_IPU2GBE2_IN           => dbg_ipu2gbe2,
+	DBG_PC1_IN                => dbg_pc1,
+	DBG_PC2_IN                => dbg_pc2,
+	DBG_FC1_IN                => dbg_fc1,
+	DBG_FC2_IN                => dbg_fc2,
+	DBG_FT1_IN                => dbg_ft1,
+	DBG_FT2_IN                => dbg_ft2
 );
 
 -- IP configurator: allows IP config to change for each event builder
@@ -928,7 +959,9 @@ port map(
 	DBG_SF_AEMPTY_OUT			=> ig_aempty,
 	DBG_SF_FULL_OUT				=> ig_full,
 	DBG_SF_AFULL_OUT			=> ig_afull,
-	DEBUG_OUT					=> ig_debug
+	--DEBUG_OUT					=> ig_debug
+	DEBUG_OUT(31 downto 0)                  => dbg_ipu2gbe1,
+	DEBUG_OUT(63 downto 32)                 => dbg_ipu2gbe2
 );      
 
 -- Second stage: Packet constructor
@@ -986,7 +1019,8 @@ port map(
 	DBG_SUB_BYTES_LOADED	=> pc_sub_bytes_loaded,
 	DBG_QUEUE_SIZE			=> pc_queue_size,
 	DBG_ACT_QUEUE_SIZE		=> pc_act_queue_size,
-	DEBUG_OUT				=> open
+	DEBUG_OUT(31 downto 0)		=> dbg_pc1,
+	DEBUG_OUT(63 downto 32)         => dbg_pc2
 );
           
 -- Third stage: Frame Constructor
@@ -1028,7 +1062,8 @@ port map(
 	-- debug ports
 	BSM_CONSTR_OUT			=> fc_bsm_constr,
 	BSM_TRANS_OUT			=> fc_bsm_trans,
-	DEBUG_OUT				=> open
+	DEBUG_OUT(31 downto 0)		=> dbg_fc1,
+	DEBUG_OUT(63 downto 32)         => dbg_fc2
 );        
           
 FRAME_TRANSMITTER: trb_net16_gbe_frame_trans
@@ -1058,7 +1093,8 @@ port map(
 	DBG_RD_DONE_OUT			=> open,
 	DBG_INIT_DONE_OUT		=> open,
 	DBG_ENABLED_OUT			=> open,
-	DEBUG_OUT				=> open
+	DEBUG_OUT(31 downto 0)		=> open,
+	DEBUG_OUT(63 downto 32)		=> open
 );        
 
 -- in case of real hardware, we use the IP cores for MAC and PHY, and also put a SerDes in
@@ -1113,9 +1149,9 @@ imp_gen: if (DO_SIMULATION = 0) generate
 		cpu_if_gbit_en		=> open,
 	------------- Output signals from the Tx MAC FIFO I/F --------------- 
 		tx_macread			=> mac_tx_read,
-		tx_discfrm			=> open,
-		tx_staten			=> open,
-		tx_statvec			=> open,
+		tx_discfrm			=> mac_tx_discfrm,
+		tx_staten			=> mac_tx_staten,  -- gk 08.06.10
+		tx_statvec			=> mac_tx_statevec,  -- gk 08.06.10
 		tx_done				=> mac_tx_done,
 	------------- Output signals from the Rx MAC FIFO I/F ---------------   
 		rx_fifo_error		=> open,
@@ -1127,6 +1163,21 @@ imp_gen: if (DO_SIMULATION = 0) generate
 		rx_error			=> open
 	);
 
+	-- gk 08.06.10
+	dbg_statevec_proc : process(serdes_clk_125)
+	begin
+		if rising_edge(serdes_clk_125) then
+			if (RESET = '1') then
+				dbg_ft1 <= (others => '0');
+			elsif (mac_tx_staten = '1') then
+				dbg_ft1(30 downto 0) <= mac_tx_statevec;
+				dbg_ft1(31) <= mac_tx_discfrm;
+			end if;
+		end if;
+	end process dbg_statevec_proc;
+
+	dbg_ft2 <= stage_stat_regs;
+
 	serdes_intclk_gen: if (USE_125MHZ_EXTCLK = 0) generate
 		-- PHY part
 		PCS_SERDES : trb_net16_med_ecp_sfp_gbe_8b
@@ -1225,7 +1276,7 @@ imp_gen: if (DO_SIMULATION = 0) generate
 	end generate serdes_extclk_gen;
 
 	stage_stat_regs(31 downto 28) <= x"e";
-	stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link status 
+	stage_stat_regs(27 downto 24) <= pcs_stat_debug(25 downto 22); -- link s-tatus 
 	stage_stat_regs(23 downto 20) <= pcs_stat_debug(35 downto 32); -- reset bsm
 	stage_stat_regs(19 downto 18) <= (others => '0');
 	stage_stat_regs(17)           <= pcs_an_complete;
diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
index ce1ff3c..628e05d 100755
--- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
@@ -45,7 +45,7 @@ port(
 	-- debug ports
 	BSM_CONSTR_OUT          : out   std_logic_vector(7 downto 0);
 	BSM_TRANS_OUT           : out   std_logic_vector(3 downto 0);
-	DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+	DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_frame_constr;
 
@@ -94,7 +94,7 @@ signal ft_sop               : std_logic;
 signal put_udp_headers      : std_logic;
 signal ready_frames_ctr     : std_logic_vector(15 downto 0);
 signal sent_frames_ctr      : std_logic_vector(15 downto 0);
-signal debug                : std_logic_vector(31 downto 0);
+signal debug                : std_logic_vector(63 downto 0);
 signal ready                : std_logic;
 signal headers_ready        : std_logic;
 
@@ -107,7 +107,7 @@ begin
 
 -- Fakes
 udp_checksum  <= x"0000";  -- no checksum test needed
-debug         <= (others => '0');
+--debug         <= (others => '0');
 
 ready         <= '1' when (constructCurrentState = IDLE)
 					 else '0';
@@ -337,9 +337,11 @@ begin
 end process putUdpHeadersProc;
 
 
-fpfWrEnProc : process(constructCurrentState, WR_EN_IN)
+fpfWrEnProc : process(constructCurrentState, WR_EN_IN, RESET)
 begin
-	if (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then
+	if (RESET = '1') then  -- gk 31.05.10
+		fpf_wr_en <= '0';
+	elsif (constructCurrentState /= IDLE) and (constructCurrentState /= CLEANUP) and (constructCurrentState /= SAVE_DATA) then
 		fpf_wr_en <= '1';
 	elsif (constructCurrentState = SAVE_DATA) and (WR_EN_IN = '1') then
 		fpf_wr_en <= '1';
@@ -486,7 +488,17 @@ begin
 	end if;
 end process sentFramesCtrProc;
 
--- Outputs
+debug(7 downto 0)      <= bsm_constr;
+debug(11 downto 8)     <= bsm_trans;
+debug(27 downto 12)    <= sent_frames_ctr;
+debug(28)              <= fpf_full;
+debug(29)              <= fpf_empty;
+debug(30)              <= ready;
+debug(31)              <= headers_ready;
+debug(47 downto 32)    <= ready_frames_ctr;
+
+
+-- Output
 FT_DATA_OUT            <= fpf_q;
 FT_TX_EMPTY_OUT        <= fpf_empty;
 FT_START_OF_PACKET_OUT <= ft_sop;
diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
index 3778f3e..5acafa7 100755
--- a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
@@ -35,7 +35,7 @@ port (
 	DBG_RD_DONE_OUT		: out	std_logic;
 	DBG_INIT_DONE_OUT	: out	std_logic;
 	DBG_ENABLED_OUT		: out	std_logic;
-	DEBUG_OUT			: out	std_logic_vector(31 downto 0)
+	DEBUG_OUT			: out	std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_frame_trans;
 
@@ -89,7 +89,7 @@ signal addr2			: std_logic_vector(5 downto 0);
 signal resetAddr		: std_logic;
 
 signal FifoEmpty		: std_logic;
-signal debug			: std_logic_vector(31 downto 0);
+signal debug			: std_logic_vector(63 downto 0);
 
 begin
 
@@ -151,9 +151,11 @@ begin
 	end if;
 end process FifoAvailProc;
 
-FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN)
+FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, RESET)
 begin
-	if    (transmitCurrentState = T_WAITFORFIFO) then
+	if (RESET = '1') then   -- gk 31.05.10
+		FifoEmpty <= '0';
+	elsif    (transmitCurrentState = T_WAITFORFIFO) then
 		FifoEmpty <= '1';
 	elsif (transmitCurrentState = T_TRANSMIT) then
 		FifoEmpty <= TX_EMPTY_IN;
diff --git a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
index 3fec624..4e76533 100755
--- a/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_packet_constr.vhd
@@ -63,7 +63,7 @@ port(
 	DBG_SUB_BYTES_LOADED    : out   std_logic_vector(31 downto 0);
 	DBG_QUEUE_SIZE          : out   std_logic_vector(31 downto 0);
 	DBG_ACT_QUEUE_SIZE      : out   std_logic_vector(31 downto 0);
-	DEBUG_OUT               : out   std_logic_vector(31 downto 0)
+	DEBUG_OUT               : out   std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_packet_constr;
 
@@ -153,7 +153,7 @@ signal fc_ip_size           : std_logic_vector(15 downto 0);
 signal fc_udp_size          : std_logic_vector(15 downto 0);
 signal max_frame_size       : std_logic_vector(15 downto 0);
 signal divide_position      : std_logic_vector(1 downto 0); -- 00->data, 01->sub, 11->term
-signal debug                : std_logic_vector(31 downto 0);
+signal debug                : std_logic_vector(63 downto 0);
 signal pc_ready             : std_logic;
 
 signal pc_sub_size          : std_logic_vector(31 downto 0);
@@ -168,7 +168,7 @@ signal ticks_ctr            : std_logic_vector(7 downto 0);  -- gk 28.04.10
 begin
 
 -- Fakes
-debug <= (others => '0');
+--debug <= (others => '0');
 
 my_int_ctr <= (3 - to_integer(to_unsigned(sub_int_ctr, 2))); -- reverse byte order
 load_int_ctr <= (3 - to_integer(to_unsigned(all_int_ctr, 2)));  -- gk 08.04.10
@@ -191,7 +191,10 @@ pc_ready <= '1' when (constructCurrentState = CIDLE) and (df_empty = '1') else '
 THE_EVT_INFO_STORE_PROC: process( CLK )
 begin
 	if( rising_edge(CLK) ) then
-		if( PC_START_OF_SUB_IN = '1' ) then
+		if (RESET = '1') then  -- gk 31.05.10
+			pc_sub_size <= (others => '0');
+			pc_trig_nr <= (others => '0');
+		elsif( PC_START_OF_SUB_IN = '1' ) then
 			pc_sub_size <= PC_SUB_SIZE_IN;
 			pc_trig_nr  <= PC_TRIG_NR_IN;
 		end if;
@@ -587,57 +590,63 @@ end process dividePositionProc;
 allIntCtrProc : process(CLK)
 begin
 	if rising_edge(CLK) then
-		case loadCurrentState is
-
-			when LIDLE => all_int_ctr <= 0;
-
-			when WAIT_FOR_FC => all_int_ctr <= 0;
-
-			when PUT_Q_LEN =>
-				if (all_int_ctr = 3) then
-					all_int_ctr <= 0;
-				else
-					all_int_ctr <= all_int_ctr + 1;
-				end if;
-
-			when PUT_Q_DEC =>
-				if (all_int_ctr = 3) then
-					all_int_ctr <= 0;
-				else
-					all_int_ctr <= all_int_ctr + 1;
-				end if;
-
-			when LOAD_SUB =>
-				if (all_int_ctr = 15) then
-					all_int_ctr <= 0;
-				else
-					all_int_ctr <= all_int_ctr + 1;
-				end if;
-
-			when LOAD_DATA => all_int_ctr <= 0;
-
-			when LOAD_TERM =>
-				if (all_int_ctr = 31) then
-					all_int_ctr <= 0;
-				else
-					all_int_ctr <= all_int_ctr + 1;
-				end if;
-
-			when DIVIDE => null; --all_int_ctr <= all_int_ctr;
-
-			when CLEANUP => all_int_ctr <= 0;
-
-			when PREP_DATA => all_int_ctr <= 0;
-
-			when DELAY => all_int_ctr <= 0;
-		end case;
+		if (RESET = '1') then  -- gk 31.05.10
+			all_int_ctr <= 0;
+		else
+			case loadCurrentState is
+	
+				when LIDLE => all_int_ctr <= 0;
+	
+				when WAIT_FOR_FC => all_int_ctr <= 0;
+	
+				when PUT_Q_LEN =>
+					if (all_int_ctr = 3) then
+						all_int_ctr <= 0;
+					else
+						all_int_ctr <= all_int_ctr + 1;
+					end if;
+	
+				when PUT_Q_DEC =>
+					if (all_int_ctr = 3) then
+						all_int_ctr <= 0;
+					else
+						all_int_ctr <= all_int_ctr + 1;
+					end if;
+	
+				when LOAD_SUB =>
+					if (all_int_ctr = 15) then
+						all_int_ctr <= 0;
+					else
+						all_int_ctr <= all_int_ctr + 1;
+					end if;
+	
+				when LOAD_DATA => all_int_ctr <= 0;
+	
+				when LOAD_TERM =>
+					if (all_int_ctr = 31) then
+						all_int_ctr <= 0;
+					else
+						all_int_ctr <= all_int_ctr + 1;
+					end if;
+	
+				when DIVIDE => null; --all_int_ctr <= all_int_ctr;
+	
+				when CLEANUP => all_int_ctr <= 0;
+	
+				when PREP_DATA => all_int_ctr <= 0;
+	
+				when DELAY => all_int_ctr <= 0;
+			end case;
+		end if;
 	end if;
 end process allIntCtrProc;
 
 dfRdEnProc : process(loadCurrentState, bytes_loaded, max_frame_size, sub_bytes_loaded, 
-					 sub_size_loaded, all_int_ctr)
+					 sub_size_loaded, all_int_ctr, RESET)
 begin
-	if (loadCurrentState = LOAD_DATA) then
+	if (RESET = '1') then  -- gk 31.05.10
+		df_rd_en <= '0';
+	elsif (loadCurrentState = LOAD_DATA) then
 --      if (bytes_loaded >= max_frame_size - x"1") then
 --          df_rd_en <= '0';
 --      elsif (sub_bytes_loaded >= sub_size_loaded) then
@@ -658,9 +667,11 @@ begin
 	end if;
 end process dfRdEnProc;
 
-shfRdEnProc : process(loadCurrentState, all_int_ctr)
+shfRdEnProc : process(loadCurrentState, all_int_ctr, RESET)
 begin
-	if (loadCurrentState = LOAD_SUB) then
+	if (RESET = '1') then  -- gk 31.05.10
+		shf_rd_en <= '0';
+	elsif (loadCurrentState = LOAD_SUB) then
 		shf_rd_en <= '1';
 	elsif (loadCurrentState = LOAD_TERM) and (all_int_ctr < 31) then
 		shf_rd_en <= '1';
@@ -672,9 +683,11 @@ begin
 end process shfRdEnProc;
 
 
-fcWrEnProc : process(loadCurrentState)
+fcWrEnProc : process(loadCurrentState, RESET)
 begin
-	if (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
+	if (RESET = '1') then  -- gk 31.05.10
+		fc_wr_en <= '0';
+	elsif (loadCurrentState = PUT_Q_LEN) or (loadCurrentState = PUT_Q_DEC) then
 		fc_wr_en <= '1';
 	elsif (loadCurrentState = LOAD_SUB) or (loadCurrentState = LOAD_DATA) or (loadCurrentState = LOAD_TERM) then
 		fc_wr_en <= '1';
@@ -904,6 +917,19 @@ fcUDPSizeProc : process(CLK)
 end process fcUDPSizeProc;
 
 
+debug(3 downto 0)             <= constr_state;
+debug(7 downto 4)             <= save_state;
+debug(11 downto 8)            <= load_state;
+debug(27 downto 12)           <= queue_size(15 downto 0);
+debug(28)                     <= df_full;
+debug(29)                     <= df_empty;
+debug(30)                     <= shf_full;
+debug(31)                     <= shf_empty;
+
+debug(47 downto 32)           <= size_left(15 downto 0);
+debug(52 downto 48)           <= all_ctr;
+debug(53)                     <= pc_ready;
+
 -- outputs
 PC_READY_OUT                  <= pc_ready;
 FC_WR_EN_OUT                  <= fc_wr_en;
diff --git a/gbe_ecp2m/trb_net16_gbe_setup.vhd b/gbe_ecp2m/trb_net16_gbe_setup.vhd
index 89917a2..03a0797 100644
--- a/gbe_ecp2m/trb_net16_gbe_setup.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_setup.vhd
@@ -38,7 +38,16 @@ port(
 	GBE_USE_MULTIEVENTS_OUT   : out std_logic;
 	GBE_READOUT_CTR_OUT       : out std_logic_vector(23 downto 0);  -- gk 26.04.10
 	GBE_READOUT_CTR_VALID_OUT : out std_logic;  -- gk 26.04.10
-	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0)
+	GBE_DELAY_OUT             : out std_logic_vector(31 downto 0);
+	-- gk 01.06.10
+	DBG_IPU2GBE1_IN          : in std_logic_vector(31 downto 0);
+	DBG_IPU2GBE2_IN          : in std_logic_vector(31 downto 0);
+	DBG_PC1_IN               : in std_logic_vector(31 downto 0);
+	DBG_PC2_IN               : in std_logic_vector(31 downto 0);
+	DBG_FC1_IN               : in std_logic_vector(31 downto 0);
+	DBG_FC2_IN               : in std_logic_vector(31 downto 0);
+	DBG_FT1_IN               : in std_logic_vector(31 downto 0);
+	DBG_FT2_IN               : in std_logic_vector(31 downto 0)
 );
 end entity;
 
@@ -104,13 +113,13 @@ begin
 			subevent_id       <= x"0000_00cf";
 			subevent_dec      <= x"0002_0001";
 			queue_dec         <= x"0003_0062";
-			max_packet        <= x"0000_fd00"; --x"0000_fde8"; -- tester
+			max_packet        <= x"0000_fde8"; --x"0000_fde8"; -- tester
 			max_frame         <= x"0578";
 			use_gbe           <= '1';
 			use_trbnet        <= '0';
 			use_multievents   <= '0';
 			reset_values      <= '0';
-			readout_ctr       <= x"00_0000";  -- gk 26.04.10
+			readout_ctr       <= x"ff_ffff";  -- gk 26.04.10  -- gk 07.06.10 corrected bug found by Sergey
 			readout_ctr_valid <= '0';  -- gk 26.04.10
 			delay             <= x"0000_0000"; -- gk 28.04.10
 
@@ -242,6 +251,31 @@ begin
 				when x"09" =>
 					data_out <= delay;
 
+				-- gk 01.06.10
+				when x"e0" =>
+					data_out <= DBG_IPU2GBE1_IN;
+
+				when x"e1" =>
+					data_out <= DBG_IPU2GBE2_IN;
+
+				when x"e2" =>
+					data_out <= DBG_PC1_IN;
+
+				when x"e3" =>
+					data_out <= DBG_PC2_IN;
+
+				when x"e4" =>
+					data_out <= DBG_FC1_IN;
+
+				when x"e5" =>
+					data_out <= DBG_FC2_IN;
+
+				when x"e6" =>
+					data_out <= DBG_FT1_IN;
+
+				when x"e7" =>
+					data_out <= DBG_FT2_IN;
+
 				when others =>
 					data_out <= (others => '0');
 			end case;
diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
index 31db1b9..096acb0 100755
--- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd
+++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
@@ -61,7 +61,7 @@ port(
 	DBG_SF_AEMPTY_OUT           : out   std_logic;
 	DBG_SF_FULL_OUT             : out   std_logic;
 	DBG_SF_AFULL_OUT            : out   std_logic;
-	DEBUG_OUT                   : out   std_logic_vector(31 downto 0)
+	DEBUG_OUT                   : out   std_logic_vector(63 downto 0)
 );
 end entity;
 
@@ -132,7 +132,7 @@ signal sf_full              : std_logic;
 signal sf_afull             : std_logic;
 
 -------------------------------------------------------------------
-type loadStates is (LIDLE, INIT, REMOVE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC);
+type loadStates is (LIDLE, INIT, REMOVE, DECIDE, CALCA, CALCB, LOAD, PAD0, PAD1, PAD2, PAD3, LOAD_SUBSUB, CALCC, CLOSE, WAIT_PC);
 signal loadCurrentState, loadNextState : loadStates;
 signal state2               :   std_logic_vector(3 downto 0);
 
@@ -177,7 +177,7 @@ signal pc_wr_en_qqq         : std_logic;
 signal pc_eod_q             : std_logic;
 signal pc_eod_qq            : std_logic;
 
-signal debug                : std_logic_vector(31 downto 0);
+signal debug                : std_logic_vector(63 downto 0);
 
 -- gk 
 signal bank_select          : std_logic_vector(3 downto 0);
@@ -221,11 +221,18 @@ begin
 		if ((RESET = '1') or (READOUT_CTR_VALID_IN = '1')) then
 			readout_ctr <= READOUT_CTR_IN;
 			readout_ctr_lock <= '0';
-		elsif ((CTS_START_READOUT_IN = '1') and (readout_ctr_lock = '0')) then
-			readout_ctr <= readout_ctr + x"1";
+		-- gk 15.06.10
+		-- increment the counter after the event is sent
+		elsif ( (saveCurrentState = SCLOSE) and (readout_ctr_lock = '0') ) then
 			readout_ctr_lock <= '1';
-		elsif (CTS_START_READOUT_IN = '0') then
+			readout_ctr <= readout_ctr + x"1";
+		elsif (saveCurrentState = SIDLE) then
 			readout_ctr_lock <= '0';
+-- 		elsif ((CTS_START_READOUT_IN = '0') and (readout_ctr_lock = '0')) then
+-- 			readout_ctr <= readout_ctr + x"1";
+-- 			readout_ctr_lock <= '1';
+-- 		elsif (CTS_START_READOUT_IN = '0') then
+-- 			readout_ctr_lock <= '0';
 		end if;
 	end if;
 end process READOUT_CTR_PROC;
@@ -241,10 +248,11 @@ begin
 -- 			bank_select <= bank_select + x"1";
 -- 		end if;
 		-- gk 29.03.10
-		if( (RESET = '1') or (rst_regs = '1') ) then
+		if( (RESET = '1') or (rst_msg = '1') ) then --(rst_regs = '1') ) then
 			bank_select <= "0000";
+		-- gk 01.06.10 THERE WAS A BUG, IT SHOUDL BE TAKEN FROM SF_Q
 		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
-			bank_select <= CTS_INFORMATION_IN(3 downto 0);
+			bank_select <= pc_data(3 downto 0); --CTS_INFORMATION_IN(3 downto 0);
 		end if;
 	end if;
 end process bank_select_proc;
@@ -253,9 +261,9 @@ end process bank_select_proc;
 start_config_proc : process( CLK )
 begin
 	if rising_edge( CLK ) then
-		if( (RESET = '1') or (rst_regs = '1') or (config_done = '1') ) then
+		if( (RESET = '1') or (config_done = '1') or (rst_msg = '1') ) then --(rst_regs = '1') or (config_done = '1') ) then
 			start_config <= '0';
-		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then
+		elsif( (sf_rd_en = '1') and (rem_ctr = x"2") ) then  -- gk 01.06.10
 			start_config <= '1';
 		end if;
 	end if;
@@ -302,14 +310,16 @@ end process THE_SYNC_PROC;
 SF_DATA_PROC : process( CLK )
 begin
 	if( rising_edge(CLK) ) then
-		if( save_addr = '1' ) then
+		if (RESET = '1') then  -- gk 31.05.10
+			sf_data <= (others => '0');
+		elsif( save_addr = '1' ) then
 			sf_data(3 downto 0) <= CTS_INFORMATION_IN(3 downto 0); -- only last 4 bits are the evt builder address
 			sf_data(15 downto 4) <= x"abc";
 		-- gk 29.03.10 four entries to save the fee_status into sf for the subsubevent
 		elsif( (add_sub_state = '1') and (add_sub_ctr = x"0") ) then
-			sf_data <= x"5555"; --x"0001";  -- gk 15.04.10
+			sf_data <= x"0001"; -- gk 06.11.10
 		elsif( (add_sub_state = '1') and (add_sub_ctr = x"1") ) then
-			sf_data <= x"0001"; --x"5555";  -- gk 15.04.10
+			sf_data <= x"5555"; -- gk 06.11.10
 		elsif( (add_sub_state = '1') and (add_sub_ctr = x"2") ) then
 			sf_data <= FEE_STATUS_BITS_IN(31 downto 16);
 		elsif( (add_sub_state = '1') and (add_sub_ctr = x"3") ) then
@@ -632,13 +642,23 @@ begin
 		when REMOVE =>
 			state2 <= x"2";
 			if( remove_done = '1' ) then
+				loadNextState <= DECIDE;
 				if (MULTI_EVT_ENABLE_IN = '1') then
-					-- gk 29.04.10
-					if((actual_message_size + pc_sub_size) < MAX_MESSAGE_SIZE_IN) then
-						loadNextState <= CALCA;
-						calc_pad_comb <= '1';
+					-- gk 03.06.10
+					if(pc_sub_size(2) = '0') then
+						if((actual_message_size + pc_sub_size + x"18") <= MAX_MESSAGE_SIZE_IN) then
+							loadNextState <= CALCA;
+							calc_pad_comb <= '1';
+						else
+							loadNextState <= CALCC;
+						end if;
 					else
-						loadNextState <= CALCC;
+						if((actual_message_size + pc_sub_size + x"1c") <= MAX_MESSAGE_SIZE_IN) then
+							loadNextState <= CALCA;
+							calc_pad_comb <= '1';
+						else
+							loadNextState <= CALCC;
+						end if;
 					end if;
 				else
 					loadNextState <= CALCA;
@@ -715,7 +735,7 @@ begin
 		when PAD3 =>
 			state2 <= x"9";
 			if (MULTI_EVT_ENABLE_IN = '1') then
-				loadNextState <= INIT; --CALCC; --LOAD_SUBSUB; --CALCC;  -- gk 30.03.10  -- gk 31.03.10  -- gk 08.04.10
+				loadNextState <= INIT; -- gk 08.04.10
 				rst_rem_ctr_comb <= '1';  -- gk 08.04.10
 				rst_regs_comb <= '1';  -- gk 08.04.10
 			else
@@ -883,9 +903,9 @@ begin
 		-- gk 30.03.10 bug fixed in the way that is written below
 		-- gk 27.03.10 should be corrected by sending padding_needed signal to pc and take care of it when setting sub_size_to_save
 		elsif( (calc_pad = '1') and (padding_needed = '1') ) then
-			pc_sub_size <= pc_sub_size + 4 + 8; -- BUG: SubEvtSize does NOT include 64bit padding!!!
+			pc_sub_size <= pc_sub_size + x"4" + x"8"; -- BUG: SubEvtSize does NOT include 64bit padding!!!
 		elsif( (calc_pad = '1') and (padding_needed = '0') ) then
-			pc_sub_size <= pc_sub_size + 8;
+			pc_sub_size <= pc_sub_size + x"8";
 		end if;
 	end if;
 end process THE_SUB_SIZE_PROC;
@@ -935,17 +955,58 @@ read_done_comb <= '1' when (read_size < 3 ) else '0'; -- "2"
 ------------------------------------------------------------------------------------------
 
 -- Debug signals
-debug(31)           <= remove_done;
-debug(30)           <= read_done;
-debug(29)           <= ce_rem_ctr;
-debug(28)           <= rst_rem_ctr;
-debug(27)           <= rst_regs;
-debug(26)           <= rem_phase;
-debug(25)           <= data_phase;
-debug(24)           <= pad_phase;
-debug(23)           <= pad_data;
-debug(22 downto 17) <= (others => '0');
-debug(16 downto 0)  <= saved_ctr;
+debug(0)              <= sf_full;
+debug(1)              <= sf_empty;
+debug(2)              <= sf_afull;
+debug(3)              <= sf_aempty;
+
+debug(7 downto  4)    <= state2;
+
+debug(11 downto 8)    <= state;
+
+dbg_bs_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if RESET = '1' then
+			debug(15 downto 12) <= (others => '0');
+		elsif ( (sf_rd_en = '1') and (rem_ctr = x"3") ) then
+			debug(15 downto 12) <= bank_select;
+		end if;
+	end if;
+end process dbg_bs_proc;
+
+debug(16)             <= config_done;
+debug(17)             <= remove_done;
+debug(18)             <= read_done;
+debug(19)             <= padding_needed;
+
+debug(20)             <= load_sub_done;
+
+dbg_cts_inf_proc : process(CLK)
+begin
+	if rising_edge(CLK) then
+		if RESET = '1' then
+			debug(39 downto 32) <= (others => '0');
+		elsif ( save_addr = '1' ) then
+			debug(39 downto 32) <= CTS_INFORMATION_IN;
+		end if;
+	end if;
+end process dbg_cts_inf_proc;
+--debug(47 downto 32)   <= pc_sub_size(15 downto 0);
+debug(47 downto 40) <= (others => '0');
+debug(63 downto 48)   <= actual_message_size(15 downto 0);
+
+-- debug(31)           <= remove_done;
+-- debug(30)           <= read_done;
+-- debug(29)           <= ce_rem_ctr;
+-- debug(28)           <= rst_rem_ctr;
+-- debug(27)           <= rst_regs;
+-- debug(26)           <= rem_phase;
+-- debug(25)           <= data_phase;
+-- debug(24)           <= pad_phase;
+-- debug(23)           <= pad_data;
+-- debug(22 downto 17) <= (others => '0');
+-- debug(16 downto 0)  <= saved_ctr;
 
 -- Outputs
 FEE_READ_OUT             <= fee_read;
diff --git a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd
index 59eac52..877620f 100755
--- a/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd
+++ b/gbe_ecp2m/trb_net16_med_ecp_sfp_gbe_8b.vhd
@@ -390,7 +390,7 @@ buf_stat_debug(28 downto 26) <= reset_bsm(2 downto 0);
 buf_stat_debug(25 downto 23) <= sd_link_error(2 downto 0);
 buf_stat_debug(22)           <= sd_link_ok;
 buf_stat_debug(21 downto 12) <= sd_tx_debug(9 downto 0);
-buf_stat_debug(11 downto 0)  <= sd_rx_debug(11 downto 0); 
+buf_stat_debug(11 downto 0)  <= sd_rx_debug(11 downto 0);
 
 
 SGMII_GBE_PCS : sgmii_gbe_pcs32
-- 
2.43.0