From 70fa5f60f5973a2ede97c52d2d0b5febdb563415 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 20 Jul 2020 12:51:28 +0200 Subject: [PATCH] hub for stacking: hub is controlling hubs --- src/hub/trb_net16_cri_hub.vhd | 364 +++++++++++++++++++++++++ src/hub/trb_net16_cri_hub_base3.vhd | 59 +++- src/hub/trb_net16_cri_hub_slwcntrl.vhd | 17 ++ 3 files changed, 427 insertions(+), 13 deletions(-) create mode 100644 src/hub/trb_net16_cri_hub.vhd diff --git a/src/hub/trb_net16_cri_hub.vhd b/src/hub/trb_net16_cri_hub.vhd new file mode 100644 index 0000000..8f0cfad --- /dev/null +++ b/src/hub/trb_net16_cri_hub.vhd @@ -0,0 +1,364 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +--take care of USE_INPUT_SBUF for multiplexer! + +entity trb_net16_cri_hub is + generic ( + --hub control + HUB_CTRL_CHANNELNUM : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL; + HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; + HUB_CTRL_ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; + HUB_CTRL_BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FE"; + HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); + USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + IBUF_SECURE_MODE : integer range 0 to 1 := c_YES; --not used any more + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); + INIT_CTRL_REGS : std_logic_vector(2**(4)*32-1 downto 0) := + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_00000000_00000000" & + x"00000000_00000000_000050FF_00000000" & + x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; + COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; + HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; + CLOCK_FREQUENCY : integer range 1 to 200 := 100; + BROADCAST_SPECIAL_ADDR : std_logic_vector(7 downto 0) := x"FF"; + --media interfaces + MII_NUMBER : integer range 0 to 32 := 4; --TODO increase to 48; will be a problem due to reg sizes + MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH; + MII_IS_UPLINK : hub_mii_config_t := (others => c_YES); + MII_IS_DOWNLINK : hub_mii_config_t := (others => c_YES); + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO); + -- settings for external api connections + INT_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0; + INT_CHANNELS : hub_api_config_t := (others => 3); + INT_IBUF_DEPTH : hub_api_config_t := (others => 6); + RESET_IOBUF_AT_TIMEOUT : integer range 0 to 1 := c_NO; + HUB_CONTROLLER_NUM : integer range 2 to 5 := 2 + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + --Media interfacces + MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0); + MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); + MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0); + MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0); + + --Received Data from connected boards + DATA_ACTIVE : out std_logic_vector(MII_NUMBER-1 downto 0); + DATA_OUT : out std_logic_vector((MII_NUMBER*(2*c_DATA_WIDTH))-1 downto 0); + DATA_READY : out std_logic_vector(MII_NUMBER-1 downto 0); + + DATA_ADDRESS_SENDER : out std_logic_vector((MII_NUMBER*c_DATA_WIDTH)-1 downto 0); + DATA_SEQNMBR : out std_logic_vector((MII_NUMBER*8)-1 downto 0); + DATA_LENGTH : out std_logic_vector((MII_NUMBER*c_DATA_WIDTH)-1 downto 0); + + + --ONEWIRE + ONEWIRE_DATA : in std_logic_vector(15 downto 0); + ONEWIRE_ADDR : in std_logic_vector( 2 downto 0); + ONEWIRE_WRITE : in std_logic; + + --INT: interfaces to connect APIs +-- INT_INIT_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); +-- INT_INIT_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); +-- INT_INIT_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); +-- INT_INIT_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); +-- INT_INIT_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); +-- INT_INIT_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); +-- INT_INIT_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); +-- INT_INIT_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); +-- INT_REPLY_DATAREADY_OUT : out std_logic_vector (INT_NUMBER downto 0); +-- INT_REPLY_DATA_OUT : out std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0); +-- INT_REPLY_PACKET_NUM_OUT : out std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0); +-- INT_REPLY_READ_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); +-- INT_REPLY_DATAREADY_IN : in std_logic_vector (INT_NUMBER downto 0) := (others => '0'); +-- INT_REPLY_DATA_IN : in std_logic_vector (INT_NUMBER*c_DATA_WIDTH downto 0) := (others => '0'); +-- INT_REPLY_PACKET_NUM_IN : in std_logic_vector (INT_NUMBER*c_NUM_WIDTH downto 0) := (others => '0'); +-- INT_REPLY_READ_OUT : out std_logic_vector (INT_NUMBER downto 0); + + COMMON_STAT_REGS : in std_logic_vector (std_COMSTATREG*32-1 downto 0) := (others => '0'); --Status of common STAT regs + COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs + COMMON_STAT_REG_STROBE : out std_logic_vector (std_COMSTATREG-1 downto 0); + COMMON_CTRL_REG_STROBE : out std_logic_vector (std_COMCTRLREG-1 downto 0); + MY_ADDRESS_OUT : out std_logic_vector (15 downto 0); + TEMPERATURE_IN : in std_logic_vector (11 downto 0); + + --REGIO INTERFACE + REGIO_ADDR_OUT : out std_logic_vector(16-1 downto 0); + REGIO_READ_ENABLE_OUT : out std_logic; + REGIO_WRITE_ENABLE_OUT : out std_logic; + REGIO_DATA_OUT : out std_logic_vector(32-1 downto 0); + REGIO_DATA_IN : in std_logic_vector(32-1 downto 0) := (others => '0'); + REGIO_DATAREADY_IN : in std_logic := '0'; + REGIO_NO_MORE_DATA_IN : in std_logic := '0'; + REGIO_WRITE_ACK_IN : in std_logic := '0'; + REGIO_UNKNOWN_ADDR_IN : in std_logic := '0'; + REGIO_TIMEOUT_OUT : out std_logic; + REGIO_VAR_ENDPOINT_ID : in std_logic_vector(15 downto 0) := (others => '0'); + TIMER_TICKS_OUT : out std_logic_vector(1 downto 0); + HUB_LED_OUT : out std_logic_vector (MII_NUMBER-1 downto 0); + + --Fixed status and control ports + HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + HUB_STAT_GEN : out std_logic_vector (31 downto 0); + MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0); + MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0); + STAT_REGS : out std_logic_vector (16*32-1 downto 0); --Status of custom STAT regs + STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs + IOBUF_STAT_INIT_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0); + IOBUF_STAT_REPLY_OBUF_DEBUG : out std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0); + + --Debugging registers + STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging + CTRL_DEBUG : in std_logic_vector (31 downto 0); --free control regs for debugging + -- bits 0-2 are NOT (inverted) error of streaming port + + BUS_HUB_DBG_RX : in CTRLBUS_RX; + BUS_HUB_DBG_TX : out CTRLBUS_TX + ); +end entity; + +architecture trb_net16_cri_hub_arch of trb_net16_cri_hub is + + signal int_med_dataready_out : std_logic_vector (HUB_CONTROLLER_NUM-2 downto 0); + signal int_med_data_out : std_logic_vector ((HUB_CONTROLLER_NUM-1)*16-1 downto 0); + signal int_med_packet_num_out : std_logic_vector ((HUB_CONTROLLER_NUM-1)*3-1 downto 0); + signal int_med_read_in : std_logic_vector (HUB_CONTROLLER_NUM-2 downto 0); + + signal int_med_dataready_in : std_logic_vector (HUB_CONTROLLER_NUM-2 downto 0); + signal int_med_data_in : std_logic_vector ((HUB_CONTROLLER_NUM-1)*16-1 downto 0); + signal int_med_packet_num_in : std_logic_vector ((HUB_CONTROLLER_NUM-1)*3-1 downto 0); + signal int_med_read_out : std_logic_vector (HUB_CONTROLLER_NUM-2 downto 0); + + signal int_med_stat_op : std_logic_vector ((HUB_CONTROLLER_NUM-1)*16-1 downto 0); + signal int_med_ctrl_op : std_logic_vector ((HUB_CONTROLLER_NUM-1)*16-1 downto 0); + + signal bus_hub_dbg_0_rx, bus_hub_dbg_1_rx : CTRLBUS_RX; + signal bus_hub_dbg_0_tx, bus_hub_dbg_1_tx : CTRLBUS_TX; + + signal loc_stat_op_1 : std_logic_vector (15 downto 0); + signal loc_ctrl_op_1 : std_logic_vector (15 downto 0); + + signal buf_DATA_ACTIVE : std_logic_vector(MII_NUMBER-1 downto 0); + signal buf_DATA_OUT : std_logic_vector((MII_NUMBER*(2*c_DATA_WIDTH))-1 downto 0); + signal buf_DATA_READY : std_logic_vector(MII_NUMBER-1 downto 0); + + signal buf_DATA_ADDRESS_SENDER : std_logic_vector((MII_NUMBER*c_DATA_WIDTH)-1 downto 0); + signal buf_DATA_SEQNMBR : std_logic_vector((MII_NUMBER*8)-1 downto 0); + signal buf_DATA_LENGTH : std_logic_vector((MII_NUMBER*c_DATA_WIDTH)-1 downto 0); + +begin + + THE_HUB_CONTROLLER : entity work.trb_net16_cri_hub_base + generic map( + HUB_USED_CHANNELS => (0,0,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => HUB_CONTROLLER_NUM, + MII_IS_UPLINK => (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),--(0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0), -- adjust to HUB_CONTROLLER_NUM (here it is for 5) + MII_IS_DOWNLINK => (1,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),--(1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0), + MII_IS_UPLINK_ONLY => (0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),--(0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0), + --USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => COMPILE_TIME, + USE_VAR_ENDPOINT_ID => c_NO + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(HUB_CONTROLLER_NUM-2 downto 0) => int_med_dataready_out, -- internal Downlinks to other hubs + MED_DATAREADY_OUT(HUB_CONTROLLER_NUM-1) => MED_DATAREADY_OUT(MII_NUMBER-1),--Uplink + + MED_DATA_OUT((HUB_CONTROLLER_NUM-1)*16-1 downto 0) => int_med_data_out, + MED_DATA_OUT((HUB_CONTROLLER_NUM)*16-1 downto (HUB_CONTROLLER_NUM-1)*16) => MED_DATA_OUT(MII_NUMBER*16-1 downto (MII_NUMBER-1)*16), + + MED_PACKET_NUM_OUT((HUB_CONTROLLER_NUM-1)*3-1 downto 0) => int_med_packet_num_out, + MED_PACKET_NUM_OUT(HUB_CONTROLLER_NUM*3-1 downto (HUB_CONTROLLER_NUM-1)*3) => MED_PACKET_NUM_OUT(MII_NUMBER*3-1 downto (MII_NUMBER-1)*3), + + MED_READ_IN(HUB_CONTROLLER_NUM-2 downto 0) => int_med_read_in, + MED_READ_IN(HUB_CONTROLLER_NUM-1) => MED_READ_IN(MII_NUMBER-1), + ---------- + MED_DATAREADY_IN(HUB_CONTROLLER_NUM-2 downto 0) => int_med_dataready_in, + MED_DATAREADY_IN(HUB_CONTROLLER_NUM-1) => MED_DATAREADY_IN(MII_NUMBER-1), + + MED_DATA_IN((HUB_CONTROLLER_NUM-1)*16-1 downto 0) => int_med_data_in, + MED_DATA_IN((HUB_CONTROLLER_NUM)*16-1 downto (HUB_CONTROLLER_NUM-1)*16) => MED_DATA_IN(MII_NUMBER*16-1 downto (MII_NUMBER-1)*16), + + MED_PACKET_NUM_IN((HUB_CONTROLLER_NUM-1)*3-1 downto 0) => int_med_packet_num_in, + MED_PACKET_NUM_IN(HUB_CONTROLLER_NUM*3-1 downto (HUB_CONTROLLER_NUM-1)*3) => MED_PACKET_NUM_IN(MII_NUMBER*3-1 downto (MII_NUMBER-1)*3), + + MED_READ_OUT(HUB_CONTROLLER_NUM-2 downto 0) => int_med_read_out, + MED_READ_OUT(HUB_CONTROLLER_NUM-1) => MED_READ_OUT(MII_NUMBER-1), + ---------- + MED_STAT_OP((HUB_CONTROLLER_NUM-1)*16-1 downto 0) => int_med_stat_op, + MED_STAT_OP(HUB_CONTROLLER_NUM*16-1 downto (HUB_CONTROLLER_NUM-1)*16) => med_stat_op(MII_NUMBER*16-1 downto (MII_NUMBER-1)*16), + + MED_CTRL_OP((HUB_CONTROLLER_NUM-1)*16-1 downto 0) => int_med_ctrl_op, + MED_CTRL_OP(HUB_CONTROLLER_NUM*16-1 downto (HUB_CONTROLLER_NUM-1)*16) => med_ctrl_op(MII_NUMBER*16-1 downto (MII_NUMBER-1)*16), + + ONEWIRE_DATA => ONEWIRE_DATA, + ONEWIRE_ADDR => ONEWIRE_ADDR, + ONEWIRE_WRITE => ONEWIRE_WRITE, + + COMMON_STAT_REGS => (others => '0'),--open,--common_stat_reg, + COMMON_CTRL_REGS => COMMON_CTRL_REGS, + MY_ADDRESS_OUT => open,--my_address, + TEMPERATURE_IN => TEMPERATURE_IN, + + --REGIO INTERFACE + REGIO_ADDR_OUT => REGIO_ADDR_OUT, + REGIO_READ_ENABLE_OUT => REGIO_READ_ENABLE_OUT, + REGIO_WRITE_ENABLE_OUT => REGIO_WRITE_ENABLE_OUT, + REGIO_DATA_OUT => REGIO_DATA_OUT, + REGIO_DATA_IN => REGIO_DATA_IN, + REGIO_DATAREADY_IN => REGIO_DATAREADY_IN, + REGIO_NO_MORE_DATA_IN => REGIO_NO_MORE_DATA_IN, + REGIO_WRITE_ACK_IN => REGIO_WRITE_ACK_IN, + REGIO_UNKNOWN_ADDR_IN => REGIO_UNKNOWN_ADDR_IN, + REGIO_TIMEOUT_OUT => REGIO_TIMEOUT_OUT, + + --ONEWIRE => TEMPSENS, + --ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open, + + BUS_HUB_DBG_RX => bus_hub_dbg_0_rx, + BUS_HUB_DBG_TX => bus_hub_dbg_0_tx + ); + +THE_HUB_1 : entity work.trb_net16_cri_hub_base + generic map( + HUB_USED_CHANNELS => (0,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => MII_NUMBER, + MII_IS_UPLINK => MII_IS_UPLINK, + MII_IS_DOWNLINK => MII_IS_DOWNLINK, + MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + --USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0002", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => COMPILE_TIME, + USE_VAR_ENDPOINT_ID => c_NO + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(MII_NUMBER-2 downto 0) => MED_DATAREADY_OUT(MII_NUMBER-2 downto 0), + MED_DATAREADY_OUT(MII_NUMBER-1) => int_med_dataready_in(0), + + MED_DATA_OUT((MII_NUMBER-1)*16-1 downto 0) => MED_DATA_OUT((MII_NUMBER-1)*16-1 downto 0), + MED_DATA_OUT(MII_NUMBER*16-1 downto (MII_NUMBER-1)*16) => int_med_data_in(15 downto 0), + + MED_PACKET_NUM_OUT((MII_NUMBER-1)*3-1 downto 0) => MED_PACKET_NUM_OUT((MII_NUMBER-1)*3-1 downto 0), + MED_PACKET_NUM_OUT(MII_NUMBER*3-1 downto (MII_NUMBER-1)*3) => int_med_packet_num_in(2 downto 0), + + MED_READ_IN((MII_NUMBER-1)*1-1 downto 0) => MED_READ_IN((MII_NUMBER-1)*1-1 downto 0), + MED_READ_IN(MII_NUMBER-1) => int_med_read_out(0), + + MED_DATAREADY_IN((MII_NUMBER-1)*1-1 downto 0) => MED_DATAREADY_IN((MII_NUMBER-1)*1-1 downto 0), + MED_DATAREADY_IN(MII_NUMBER-1) => int_med_dataready_out(0), + + MED_DATA_IN((MII_NUMBER-1)*16-1 downto 0) => MED_DATA_IN((MII_NUMBER-1)*16-1 downto 0), + MED_DATA_IN((MII_NUMBER)*16-1 downto (MII_NUMBER-1)*16) => int_med_data_out(15 downto 0), + + MED_PACKET_NUM_IN((MII_NUMBER-1)*3-1 downto 0) => MED_PACKET_NUM_IN((MII_NUMBER-1)*3-1 downto 0), + MED_PACKET_NUM_IN((MII_NUMBER)*3-1 downto (MII_NUMBER-1)*3) => int_med_packet_num_out(2 downto 0), + + MED_READ_OUT((MII_NUMBER-1)*1-1 downto 0) => MED_READ_OUT((MII_NUMBER-1)*1-1 downto 0), + MED_READ_OUT(MII_NUMBER-1) => int_med_read_in(0), + + MED_STAT_OP((MII_NUMBER-1)*16-1 downto 0) => MED_STAT_OP((MII_NUMBER-1)*16-1 downto 0), + MED_STAT_OP((MII_NUMBER)*16-1 downto (MII_NUMBER-1)*16) => loc_stat_op_1, --input + + MED_CTRL_OP((MII_NUMBER-1)*16-1 downto 0) => MED_CTRL_OP((MII_NUMBER-1)*16-1 downto 0), + MED_CTRL_OP((MII_NUMBER)*16-1 downto (MII_NUMBER-1)*16) => loc_ctrl_op_1, --output + + DATA_ACTIVE => buf_DATA_ACTIVE, + DATA_OUT => buf_DATA_OUT, + DATA_READY => buf_DATA_READY, + + DATA_ADDRESS_SENDER => buf_DATA_ADDRESS_SENDER, + DATA_SEQNMBR => buf_DATA_SEQNMBR, + DATA_LENGTH => buf_DATA_LENGTH, + + ONEWIRE_DATA => ONEWIRE_DATA, + ONEWIRE_ADDR => ONEWIRE_ADDR, + ONEWIRE_WRITE => ONEWIRE_WRITE, + + COMMON_STAT_REGS => (others => '0'),--open,--common_stat_reg, + COMMON_CTRL_REGS => open,--common_ctrl_reg, + MY_ADDRESS_OUT => open,--my_address, + TEMPERATURE_IN => TEMPERATURE_IN, + + + --REGIO INTERFACE + REGIO_ADDR_OUT => open,--ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => open,--ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => open,--ctrlbus_rx.write, + REGIO_DATA_OUT => open,--ctrlbus_rx.data, + REGIO_DATA_IN => (others => '0'),--ctrlbus_tx.data, + REGIO_DATAREADY_IN => '0',--rdack, + REGIO_NO_MORE_DATA_IN => '0',--ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => '0',--wrack, + REGIO_UNKNOWN_ADDR_IN => '0',--ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => open,--ctrlbus_rx.timeout, + + --ONEWIRE => TEMPSENS, + --ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open, + + BUS_HUB_DBG_RX => bus_hub_dbg_1_rx, + BUS_HUB_DBG_TX => bus_hub_dbg_1_tx + ); + + +loc_stat_op_1 <= int_med_ctrl_op(15) & "000" & x"007"; +loc_ctrl_op_1 <= int_med_stat_op(15) & "000" & x"000"; + +DATA_ACTIVE <= buf_DATA_ACTIVE; +DATA_OUT <= buf_DATA_OUT; +DATA_READY <= buf_DATA_READY; + +DATA_ADDRESS_SENDER <= buf_DATA_ADDRESS_SENDER; +DATA_SEQNMBR <= buf_DATA_SEQNMBR; +DATA_LENGTH <= buf_DATA_LENGTH; + +end architecture; diff --git a/src/hub/trb_net16_cri_hub_base3.vhd b/src/hub/trb_net16_cri_hub_base3.vhd index 2bb7301..b975d51 100644 --- a/src/hub/trb_net16_cri_hub_base3.vhd +++ b/src/hub/trb_net16_cri_hub_base3.vhd @@ -16,7 +16,7 @@ entity trb_net16_cri_hub_base is HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM; HUB_CTRL_ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF"; HUB_CTRL_BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FE"; - HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_NO,c_YES); + HUB_USED_CHANNELS : hub_channel_config_t := (c_NO,c_YES,c_NO,c_YES); USE_CHECKSUM : hub_channel_config_t := (c_NO,c_YES,c_YES,c_YES); USE_VENDOR_CORES : integer range 0 to 1 := c_YES; IBUF_SECURE_MODE : integer range 0 to 1 := c_YES; --not used any more @@ -274,6 +274,10 @@ architecture trb_net16_cri_hub_base_arch of trb_net16_cri_hub_base is signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0); signal local_reset_med : std_logic_vector(MII_NUMBER-1 downto 0); + + signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); + signal buf_HUB_STAT_CHANNEL : std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + signal buf_HUB_STAT_GEN : std_logic_vector (31 downto 0); type point_array_t is array (0 to 15) of unsigned(15 downto 0); signal dbg_cnt : point_array_t := (others => (others=> '0')); @@ -453,7 +457,7 @@ begin constant i : integer := j*2**(c_MUX_WIDTH-1)+k; begin -- data channel - gen_iobuf: if (k = c_DATA_CHANNEL) generate --and ( j < MII_NUMBER-1) + gen_iobuf: if ((k = c_DATA_CHANNEL) and (HUB_USED_CHANNELS(c_DATA_CHANNEL) = c_YES)) generate --and ( j < MII_NUMBER-1) IOBUF: trb_net16_iobuf generic map ( IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH), @@ -521,7 +525,7 @@ begin end generate; -- slow control channel - gen_iobuf: if k = c_SLOW_CTRL_CHANNEL generate + gen_iobuf: if ((k = c_SLOW_CTRL_CHANNEL) and (HUB_USED_CHANNELS(c_SLOW_CTRL_CHANNEL) = c_YES)) generate IOBUF: trb_net16_iobuf generic map ( IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, INT_IBUF_DEPTH, MII_NUMBER, INT_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH), @@ -588,7 +592,7 @@ begin ); end generate; - gen_trmbuf: if (k = c_TRG_LVL1_CHANNEL) or (k = c_UNUSED_CHANNEL) generate -- or ((k = c_DATA_CHANNEL) and ( j = MII_NUMBER-1)) : terminate trigger channel and chnl 2 and data uplink channel + gen_trmbuf: if (((k = c_TRG_LVL1_CHANNEL) or (k = c_UNUSED_CHANNEL)) or (HUB_USED_CHANNELS(k) = c_NO)) generate -- or ((k = c_DATA_CHANNEL) and ( j = MII_NUMBER-1)) : terminate trigger channel and chnl 2 and data uplink channel hub_to_buf_init_read(i) <= '0'; buf_to_hub_init_dataready(i) <= '0'; buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0'); @@ -799,7 +803,7 @@ begin constant first_point_num : integer := calc_first_point_number(MII_NUMBER, i, HUB_CTRL_CHANNELNUM, INT_NUMBER, INT_CHANNELS); constant next_point_num : integer := first_point_num + point_num; begin - gen_logic : if (i = c_DATA_CHANNEL) generate + gen_logic : if ((i = c_DATA_CHANNEL) and (HUB_USED_CHANNELS(c_DATA_CHANNEL) = c_YES)) generate gen_data_chnl_api : for j in 0 to point_num-1 generate constant local_position : integer := first_point_num+j; begin @@ -922,8 +926,24 @@ begin --buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0'); end generate; end generate; --generate for each data channel + + + gen_no_datalogic : if (i = c_DATA_CHANNEL) and (HUB_USED_CHANNELS(c_DATA_CHANNEL) = c_NO) generate + gen_no_data_chnl_api : for j in 0 to point_num-1 generate + + buf_rec_data_active(j) <= '0'; + buf_rec_data_out(((j+1)*(2*c_DATA_WIDTH))-1 downto (j*(2*c_DATA_WIDTH))) <= (others => '0'); + buf_rec_data_ready(j) <= '0'; + + buf_rec_data_addr_sender(((j+1)*c_DATA_WIDTH)-1 downto (j*c_DATA_WIDTH)) <= (others => '0'); + buf_rec_data_seqnmbr(((j+1)*8)-1 downto (j*8)) <= (others => '0'); + buf_rec_data_length(((j+1)*c_DATA_WIDTH)-1 downto (j*c_DATA_WIDTH)) <= (others => '0'); + + dbg_cnt(j) <= (others => '0'); + end generate; + end generate; - gen_slwcntrl_logic : if (i = c_SLOW_CTRL_CHANNEL) generate + gen_slwcntrl_logic : if (i = c_SLOW_CTRL_CHANNEL) and (HUB_USED_CHANNELS(c_SLOW_CTRL_CHANNEL) = c_YES) generate constant n : integer := 2**(c_MUX_WIDTH-1)*MII_NUMBER; begin --generate here the slow control channels @@ -1033,11 +1053,15 @@ begin STAT_TIMEOUT => open, + HUB_STAT_CHANNEL => buf_HUB_STAT_CHANNEL, + HUB_STAT_GEN => buf_STAT_DEBUG, + + STAT_DEBUG => buf_HUB_STAT_GEN, CTRL_DEBUG => CTRL_DEBUG ); end generate; - gen_select_no_logic : if (i = c_TRG_LVL1_CHANNEL) or (i = c_UNUSED_CHANNEL) generate + gen_select_no_logic : if ((i = c_TRG_LVL1_CHANNEL) or (i = c_UNUSED_CHANNEL)) or (HUB_USED_CHANNELS(i) = c_NO) generate HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0'); HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0'); HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0'); @@ -1056,6 +1080,8 @@ begin --------------------------------------------------------------------------- -- Bus Handler --------------------------------------------------------------------------- + + gen_cri_data_handler : if (HUB_USED_CHANNELS(c_DATA_CHANNEL) = c_YES) generate THE_CRI_DATA_REC_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( PORT_NUMBER => 10, @@ -1095,7 +1121,15 @@ begin BUS_TX(9) => bus_cri_data_rec_tx(9), STAT_DEBUG => open ); - + end generate; + + gen_no_cri_data_handler : if (HUB_USED_CHANNELS(c_DATA_CHANNEL) = c_NO) generate + -- terminate + BUS_HUB_DBG_TX.ack <= '0'; + BUS_HUB_DBG_TX.nack <= '0'; + BUS_HUB_DBG_TX.unknown <= '0'; + end generate; + ------------------------------------------------- -- Include variable Endpoint ID @@ -1225,17 +1259,16 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); -- IOBUF_STAT_REPLY_OBUF_DEBUG <= iobuf_stat_reply_obuf_debug_i; -- IOBUF_CTRL_GEN <= (others => '0'); -- --map regio registers to stat & ctrl outputs --- COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS; + COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS; -- COMMON_CTRL_REG_STROBE <= HC_COMMON_CTRL_REG_STROBE; -- COMMON_STAT_REG_STROBE <= HC_COMMON_STAT_REG_STROBE; -- MY_ADDRESS_OUT <= HUB_ADDRESS; -- STAT_REGS <= HC_STAT_REGS(16*32-1 downto 0); -- STAT_CTRL_REGS <= HC_CTRL_REGS(255 downto 0); --- HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL; --- STAT_DEBUG <= buf_STAT_DEBUG; + HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL; + STAT_DEBUG <= buf_STAT_DEBUG; --- HUB_STAT_GEN(3 downto 0) <= HUB_locked; --- HUB_STAT_GEN(31 downto 4) <= (others => '0'); + HUB_STAT_GEN <= buf_HUB_STAT_GEN; TIMER_TICKS_OUT(0) <= timer_us_tick; TIMER_TICKS_OUT(1) <= timer_ms_tick; diff --git a/src/hub/trb_net16_cri_hub_slwcntrl.vhd b/src/hub/trb_net16_cri_hub_slwcntrl.vhd index 3f45623..801ca3b 100644 --- a/src/hub/trb_net16_cri_hub_slwcntrl.vhd +++ b/src/hub/trb_net16_cri_hub_slwcntrl.vhd @@ -119,6 +119,11 @@ entity trb_net16_cri_hub_slwcntrl is STAT_TIMEOUT : out std_logic_vector(4*32-1 downto 0); --maybe a problem in synth + --Fixed status and control ports + HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0); + HUB_STAT_GEN : out std_logic_vector (31 downto 0); + + STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging CTRL_DEBUG : in std_logic_vector (31 downto 0) ); end entity; @@ -272,6 +277,8 @@ architecture trb_net16_cri_hub_slwcntrl_arch of trb_net16_cri_hub_slwcntrl is signal STAT_REG_STROBE : std_logic_vector (2**6-1 downto 0); + signal buf_STAT_DEBUG : std_logic_vector (31 downto 0); + attribute syn_keep : boolean; attribute syn_keep of reset_i : signal is true; attribute syn_hier : string; @@ -1015,4 +1022,14 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler HC_COMMON_CTRL_REGS <= HC_COMMON_CTRL_REGS_i; + --debugging + buf_STAT_DEBUG( 3 downto 0 ) <= STAT_TIMEOUT(3*32+3 downto 3*32); + buf_STAT_DEBUG( 7 downto 4 ) <= HUB_CTRL_final_activepoints(3*32+3 downto 3*32); + + HUB_STAT_CHANNEL <= buf_HUB_STAT_CHANNEL; + STAT_DEBUG <= buf_STAT_DEBUG; + + HUB_STAT_GEN(3 downto 0) <= HUB_locked; + HUB_STAT_GEN(31 downto 4) <= (others => '0'); + end architecture; -- 2.43.0