From 71270258c39130dd5db0bc5154242a2b9271f008 Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Tue, 30 Jan 2018 16:52:58 +0100 Subject: [PATCH] Description for 16 bit flash scheme, IF --- trb3/AdditionalModules.tex | 65 +++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 12 deletions(-) diff --git a/trb3/AdditionalModules.tex b/trb3/AdditionalModules.tex index 62cac39..6bc5626 100644 --- a/trb3/AdditionalModules.tex +++ b/trb3/AdditionalModules.tex @@ -10,27 +10,56 @@ \item[Debug] For debugging, a UART can be used to access the internal data bus (resources: 300 slices in FPGA) \end{description} +The generic SPI interface which is used for many modules has the following structure: + +\begin{tabularx}{\textwidth}{c|c|X} + \textbf{Bit} & \textbf{Name} & \textbf{Content} \\ + \hline + 31 -- 24 & 8-Bit-Register & \\ + 23 -- 20 & Command & Command, 0: read, 8: write, other: no operation \\ + 19 -- 16 & Subregister & Additional 4 bits (only used for padiwa amps and v123) \\ + 15 -- 0 & Data & 16 Bit data payload for write commands\\ +\end{tabularx} + +The generic UART interface has the following structure: + +\begin{tabularx}{\textwidth}{c|c|X} + \textbf{Bit} & \textbf{Name} & \textbf{Content} \\ + \hline + 39 -- 32 & 8-Bit-Register & \\ + 31 -- 0 & Data & 16 Bit data payload for write commands\\ +\end{tabularx} + \subsection{Flash programming} -Flash programming of the MACHX03 FPGAs (like the DiRich threshold FPGAs or the Logicbox) is done via a generic +Flash programming of the MACHX03 FPGAs (like the DiRich threshold FPGAs or the Logicbox, but also Padiwa-Amps2) is done via a generic flash controller which sits in the middle between the serial interface (SPI or UART) and the local logic (where the local registers are placed). Both, SPI and UART, have 16-bit adresses and a 16/32-bit data bus. The flash controller uses the adresses 0x40 - 0x5F and shades the local user logic for this address space. -The way flash programming is done in the same way as described in the Padiwa documentation, in order to stay consistent. +The flash controller works in 2 modes: in mode 0, the flash programming is done in the same way as described in the Padiwa documentation, +in order to stay consistent. In this case the register 0x50 (flash access) contains the 13-bit flash page and a 3-bit flash command. +In mode 1 (16 bit mode), the access is done with 2 independend registers: first, one has to write first the 3-bit flash command in register +0x51 (this allows multiple uses), and subsequently the 16-bit page address in register 0x50. +The way the user flash and the config flash is selected is also different between the 2 modes. In mode 0, the user flash starts at +0x1C00, and EnableCfg has to be set to 1 only to enable the config space. In mode 1, both address spaces are independent and start +with 0x0, and EnableCfg is used to select the space (0 for user space, 1 for config space). +The flash page is mapped via the read/write command to 16 bytes RAM (0x40-0x4f). As each byte has its own register, 16 read commands are +normally required to read the entire flash page. In order to speed up the readout for slow +interfaces (like UART), the controller allows also multiple-read with a single command (bursts). \begin{longtable} { p{3cm} l c c p{6cm} } \toprule - \textbf{Register} & \textbf{Addr} & \textbf{Bits} & \textbf{Content} & \textbf{Description} \\ + \textbf{Register} & \textbf{Addr} & \textbf{Bit} & \textbf{Content} & \textbf{Description} \\ \midrule \midrule \endfirsthead\multicolumn{4}{c}{\tablename\ \thetable\ -- \textit{Continued from previous page}} \\\toprule - \textbf{Register} & \textbf{Addr} & \textbf{Bits} & \textbf{Content} & \textbf{Description} \\ + \textbf{Register} & \textbf{Addr} & \textbf{Bit} & \textbf{Content} & \textbf{Description} \\ \midrule \midrule \endhead\multicolumn{4}{r}{\textit{Continued on next page}} \\ @@ -38,20 +67,28 @@ The way flash programming is done in the same way as described in the Padiwa doc \endlastfoot \textbf{FlashRAM}\hfill(rw) & 0x4X & & & Mapped flash page (16 bytes in total)\\ \rowcolor{light-gray} - \textbf{FlashAccess}\hfill(w) & 0x50 & & & \\ +\textbf{FlashAddress}\hfill(w) & 0x50 & 15-0 & & For mode 1 \\ + +\rowcolor{light-gray} + \textbf{FlashCommand}\hfill(w) & 0x51 & & & For mode 1 \\ +\rowcolor{light-gray} + & & 3-1 & & (bit 0: don't care) \\ \rowcolor{light-gray} - \quad Flash command\hfill & & 15-13 & & \\ -\rowcolor{light-gray} & & & 0x0 & Read a page from flash and store it in RAM\\ \rowcolor{light-gray} & & & 0x4 & Write a page from RAM to flash\\ \rowcolor{light-gray} - & & & 0x8 & Enable flash (no address required) \\ -\rowcolor{light-gray} - & & & 0xA & Disable flash (no address required) \\ + & & & 0x8 & Enable flash (address: don't care) \\ \rowcolor{light-gray} - & & & 0xE & Erase user of config flash, depending on address \\ + & & & 0xA & Disable flash (address: don't care) \\ \rowcolor{light-gray} + & & & 0xE & Erase user of config flash, depending on EnableCfg \\ + + +%\rowcolor{light-gray} + \textbf{FlashAccess}\hfill(w) & 0x50 & & & For mode 0 \\ +%\rowcolor{light-gray} + \quad Flash command\hfill & & 15-13 & & command like above\\ \quad Flash address\hfill & & 12-0 & & \\ @@ -61,6 +98,10 @@ The way flash programming is done in the same way as described in the Padiwa doc \quad FlashBusy \hfill{r} & & 2 & & Flash busy (e.g. after erase) \\ \quad MasterStart \hfill{w} & & 3 & & Starts the flash master by hand, which unpacks the user flash and writes the local registers \\ \quad MasterRun \hfill{r} & & 4 & & is =1 while the master is running \\ +\quad FlashMode \hfill{w} & & 8 & & flash mode \\ +& & & 0x0 & Mode 0 (13 bit address) \\ +& & & 0x1 & Mode 1 (16 bit address) \\ + \rowcolor{light-gray} \textbf{FlashPageBurst} & 0x5D & & & Can be used to perform multiple reads on the flash page (0x4X) \\ @@ -89,7 +130,7 @@ The way flash programming is done in the same way as described in the Padiwa doc The flash controller adds in addition a master function which reads the user flash space, and writes the local registers after power up (or upon request). This allows to store default values for local registers (like thresholds) in a common way. The -data which is unpacked starts at the first user page (usually 0x0C00), and contains a version byte, an address byte, and 2-4 data bytes +data which is unpacked starts at the first user page, and contains a version byte, an address byte, and 2-4 data bytes (depending on the data width). The data width is selected with the version byte (0x1: 16 bit, 0x2: 32 bit), and any other version byte means ``end of file''. In 32 bit mode, 2 more padding bytes are added in order to align the data content with the flash page. This means in 16 bit mode 4 data words can be stored, and in 32 bit mode 2 data words. The data words are always stored in big-endian. -- 2.43.0