From 7150253af7b61f48a091405ca5fabcd72cd70def Mon Sep 17 00:00:00 2001 From: Cahit Date: Mon, 1 Dec 2014 12:35:14 +0100 Subject: [PATCH] unnecessary files are removed from tdc test folder --- tdc_test/compile_constraints.pl | 13 -- tdc_test/compile_periph_frankfurt.pl | 155 --------------------- tdc_test/compile_periph_synonly.pl | 155 --------------------- tdc_test/config.vhd | 77 ++++++----- tdc_test/currentRelease | 1 - tdc_test/trb3_periph.p2t | 20 --- tdc_test/trb3_periph.prj | 192 --------------------------- 7 files changed, 47 insertions(+), 566 deletions(-) delete mode 100755 tdc_test/compile_constraints.pl delete mode 100755 tdc_test/compile_periph_frankfurt.pl delete mode 100755 tdc_test/compile_periph_synonly.pl delete mode 120000 tdc_test/currentRelease delete mode 100644 tdc_test/trb3_periph.p2t delete mode 100644 tdc_test/trb3_periph.prj diff --git a/tdc_test/compile_constraints.pl b/tdc_test/compile_constraints.pl deleted file mode 100755 index 98cf0e9..0000000 --- a/tdc_test/compile_constraints.pl +++ /dev/null @@ -1,13 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - -my $TOPNAME = "trb3_periph"; #Name of top-level entity - - -#create full lpf file -system("cp ../base/trb3_periph_mainz.lpf diamond/$TOPNAME.lpf"); -system("cat ../tdc_releases/tdc_v1.5.1/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf"); -system("cat ../tdc_releases/tdc_v1.5.1/tdc_constraints.lpf >> diamond/$TOPNAME.lpf"); - diff --git a/tdc_test/compile_periph_frankfurt.pl b/tdc_test/compile_periph_frankfurt.pl deleted file mode 100755 index 33d8046..0000000 --- a/tdc_test/compile_periph_frankfurt.pl +++ /dev/null @@ -1,155 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $BasePath = "../base/"; #path to "base" directory -my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; -my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@localhost"; -my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp $BasePath/".$TOPNAME."_mainz.lpf workdir/$TOPNAME.lpf"); -system("cat srcjan/".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; -system("mv $TOPNAME.ncd guidefile.ncd"); - -#-g guidefile.ncd -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - - -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -execute($c); - -## IOR IO Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/tdc_test/compile_periph_synonly.pl b/tdc_test/compile_periph_synonly.pl deleted file mode 100755 index 379cefc..0000000 --- a/tdc_test/compile_periph_synonly.pl +++ /dev/null @@ -1,155 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $BasePath = "../base/"; #path to "base" directory -my $lattice_path = '/opt/lattice/diamond/1.3'; -my $synplify_path = '/opt/synplicity/fpga_e201103'; -my $lm_license_file_for_synplify = "27000\@localhost"; -my $lm_license_file_for_par = "1710\@cronos.e12.physik.tu-muenchen.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp $BasePath/".$TOPNAME."_ada.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -#$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -#execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -#execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -#execute($c); - -#my $tpmap = $TOPNAME . "_map" ; - -#$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -#execute($c); - - -#system("rm $TOPNAME.ncd"); - -#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; -#execute($c); - -## IOR IO Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -## TWR Timing Report -#$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -#execute($c); - -#$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -#execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/tdc_test/config.vhd b/tdc_test/config.vhd index a5029e9..5a0121f 100644 --- a/tdc_test/config.vhd +++ b/tdc_test/config.vhd @@ -10,32 +10,31 @@ package config is --Begin of design configuration ------------------------------------------------------------------------------ ---Include GbE logic - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 3; - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons - constant USE_DOUBLE_EDGE : integer := c_YES; +--TDC settings + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 8; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 1; --ring buffer size: 0, 1, 2, 3 + --ring buffer size: 32,64,96,128 --Include SPI on AddOn connector - constant INCLUDE_SPI : integer := c_NO; + constant INCLUDE_SPI : integer := c_YES; --Add logic to generate configurable trigger signal from input signals. - constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; - ---Do histos of all inputs - constant INCLUDE_STATISTICS : integer := c_YES; - ---number of real inputs to the FPGA - constant PHYSICAL_INPUTS : integer := 32; - ---Define ringbuffer size for TDC channels: 32-64-128 - constant RING_BUFFER_SIZE : integer range 32 to 128 := 32; - ---Run wih 125 MHz instead of 100 MHz - constant USE_125_MHZ : integer := c_NO; --not implemented yet! - ---Use sync mode, RX clock for all parts of the FPGA - constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; --Do histos of all inputs + constant PHYSICAL_INPUTS : integer := 32; --number of inputs connected + constant USE_SINGLE_FIFO : integer := c_YES; -- single fifo for statistics +--Run wih 125 MHz instead of 100 MHz, use received clock from serdes or external clock input + constant USE_125_MHZ : integer := c_NO; --not implemented yet! + constant USE_RXCLOCK : integer := c_NO; --not implemented yet! + constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet! --Address settings constant INIT_ADDRESS : std_logic_vector := x"F305"; @@ -45,17 +44,12 @@ package config is --End of design configuration ------------------------------------------------------------------------------ - ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ type intlist_t is array(0 to 7) of integer; type hw_info_t is array(0 to 7) of unsigned(31 downto 0); - constant HW_INFO_BASE : unsigned(31 downto 0) := x"91007000"; - constant HW_INFO_SPI : hw_info_t := (x"00000000", x"00000400", others => x"00000000"); - constant HW_INFO_DOUBLE_EDGE : hw_info_t := (x"00000000", x"00000800", others => x"00000000"); - constant HW_INFO_NUM_CHANS : hw_info_t := (x"00000000", x"00000010", x"00000020", x"00000030", - x"00000040", x"00000050", x"00000060", x"00000070", others => x"00000000"); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"91004000"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100, 125, others => 0); constant MEDIA_FREQUENCY_ARR : intlist_t := (200, 125, others => 0); @@ -63,16 +57,39 @@ package config is constant HARDWARE_INFO : std_logic_vector(31 downto 0); constant CLOCK_FREQUENCY : integer; constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + +function generateIncludedFeatures return std_logic_vector; + + end; package body config is --compute correct configuration mode - constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( - HW_INFO_BASE + HW_INFO_SPI(INCLUDE_SPI) + HW_INFO_DOUBLE_EDGE(USE_DOUBLE_EDGE) + - HW_INFO_NUM_CHANS(NUM_TDC_CHANNELS_POWER2)); +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); +begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2 + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1)); + return t; +end function; + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ); constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ); + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); -- := generateIncludedFeatures; end package body; diff --git a/tdc_test/currentRelease b/tdc_test/currentRelease deleted file mode 120000 index ef8072e..0000000 --- a/tdc_test/currentRelease +++ /dev/null @@ -1 +0,0 @@ -../tdc_releases/tdc_v1.6.2 \ No newline at end of file diff --git a/tdc_test/trb3_periph.p2t b/tdc_test/trb3_periph.p2t deleted file mode 100644 index c037b03..0000000 --- a/tdc_test/trb3_periph.p2t +++ /dev/null @@ -1,20 +0,0 @@ --w --i 15 --l 5 --n 1 --y --s 12 --t 12 --c 1 --e 2 --m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/tdc_test/trb3_periph.prj b/tdc_test/trb3_periph.prj deleted file mode 100644 index c6ee60e..0000000 --- a/tdc_test/trb3_periph.prj +++ /dev/null @@ -1,192 +0,0 @@ - - -# implementation: "workdir" -impl -add workdir -type fpga - -# device options -set_option -technology LATTICE-ECP3 -set_option -part LFE3_150EA -set_option -package FN672C -set_option -speed_grade -8 -set_option -part_companion "" - -# compilation/mapping options -set_option -default_enum_encoding sequential -set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3_periph" -set_option -resource_sharing true - -# map options -set_option -frequency 200 -set_option -fanout_limit 100 -set_option -disable_io_insertion 0 -set_option -retiming 0 -set_option -pipe 0 -#set_option -force_gsr -set_option -force_gsr false -set_option -fixgatedclocks 3 -set_option -fixgeneratedclocks 3 -set_option -compiler_compatible true - - -# simulation options -set_option -write_verilog 0 -set_option -write_vhdl 1 - -# automatic place and route (vendor) options -set_option -write_apr_constraint 0 - -# set result format/file last -project -result_format "edif" -project -result_file "workdir/trb3_periph.edf" - -#implementation attributes - -set_option -vlog_std v2001 -set_option -project_relative_includes 1 -impl -active "workdir" - -#################### - - - -#add_file options - -add_file -vhdl -lib work "version.vhd" -add_file -vhdl -lib work "currectRelease/tdc_version.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib "work" "../base/trb3_components.vhd" - -add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" -add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" - -add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" -add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" -add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" - -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" - -add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" -add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" - -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" - -add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" - - -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/trb3_periph.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Adder_304.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/bit_sync.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Encoder_304_Bit.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/FIFO_32x32_OutReg.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/Reference_channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/ROM_encoder_3.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/ROM_FIFO.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/TDC.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.2/source/up_counter.vhd" - -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/trb3_periph.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Adder_304.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/bit_sync.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Encoder_304_Bit.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/FIFO_32x32_OutReg.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/Reference_channel.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_encoder_3.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/ROM_FIFO.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/TDC.vhd" -#add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.4/up_counter.vhd" - -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/trb3_periph.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Adder_304.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/bit_sync.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Channel_200.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Encoder_304_Bit.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/FIFO_32x32_OutReg.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/Reference_channel.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_encoder_3.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/ROM_FIFO.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/TDC.vhd" -add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.5/up_counter.vhd" - -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/trb3_periph.vhd" -# #add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Adder_304.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/bit_sync.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Channel_200.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Encoder_304_Bit.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/FIFO_32x32_OutReg.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/Reference_Channel.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_encoder_3.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/ROM_FIFO.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/TDC.vhd" -# add_file -vhdl -lib "work" "../tdc_releases/tdc_v0.6/up_counter.vhd" -- 2.43.0