From 71d1b70672bbf635ab0ffbde7d223b7a29c583f0 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Sat, 23 Aug 2014 02:03:54 +0200 Subject: [PATCH] try modified adc handler, without reset to DQS --- nxyter/compile_munich32.pl | 163 ++++++++ nxyter/compile_munich32.sh | 12 + nxyter/source/nx_data_receiver.vhd | 643 ++++++++++------------------- nxyter/trb3_periph_constraints.lpf | 2 +- 4 files changed, 388 insertions(+), 432 deletions(-) create mode 100755 nxyter/compile_munich32.pl create mode 100755 nxyter/compile_munich32.sh diff --git a/nxyter/compile_munich32.pl b/nxyter/compile_munich32.pl new file mode 100755 index 0000000..2ad7c9e --- /dev/null +++ b/nxyter/compile_munich32.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/3.2'; +my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; + +$c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) +{ + if(/\@E:/) + { + print STDERR "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print STDERR "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm -vf $TOPNAME.ncd"); +system("rm -vf $TOPNAME.dir/*"); + +$c=qq|$lattice_path/ispfpga/bin/lin64/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; +execute($c, "do_not_exit"); + +print STDERR "Do 0\n"; + +system("cp -va ${TOPNAME}.dir/*.ncd ./${TOPNAME}.ncd"); + +print STDERR "Do 1\n"; + + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 2\n"; + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 3\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 4\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +print STDERR "Do 5\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; + +print STDERR "Do 6\n"; + +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print STDERR "option: $op \n"; + $op = "" if(!$op); + print STDERR "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print STDERR "$!"; + if($op ne "do_not_exit") { + print STDERR "------- EXIT by function execute --------\n"; + exit; + } + } + + return $r; + +} diff --git a/nxyter/compile_munich32.sh b/nxyter/compile_munich32.sh new file mode 100755 index 0000000..746f1ee --- /dev/null +++ b/nxyter/compile_munich32.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +. /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env + +./compile_munich32.pl + +#grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup" +grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup +grep 'Error:' ./workdir/trb3_periph.twr.hold +grep 'potential circuit loops' ./workdir/* + +echo "Script DONE!" diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 67ab0ab..94fcb86 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -248,7 +248,7 @@ architecture Behavioral of nx_data_receiver is signal nx_timestamp_delay_s : unsigned(2 downto 0); signal nx_timestamp_delay_actr : unsigned(15 downto 0); signal nx_frame_word_delay_rr : unsigned(1 downto 0); - signal nx_frame_word_delay_r : unsigned(1 downto 0); + signal nx_frame_word_delay_reg : unsigned(1 downto 0); signal fifo_full_rr : std_logic; signal fifo_full_r : std_logic; signal fifo_empty_rr : std_logic; @@ -268,6 +268,7 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- Reset Handler ----------------------------------------------------------------------------- + signal disable_resets : std_logic; signal nx_online_ii : std_logic; signal nx_online_i : std_logic; signal adc_error : std_logic; @@ -362,7 +363,7 @@ architecture Behavioral of nx_data_receiver is attribute syn_keep of nx_frame_word_f : signal is true; attribute syn_keep of nx_frame_word_delay_rr : signal is true; - attribute syn_keep of nx_frame_word_delay_r : signal is true; + attribute syn_keep of nx_frame_word_delay_reg : signal is true; attribute syn_preserve : boolean; attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; @@ -389,7 +390,7 @@ architecture Behavioral of nx_data_receiver is attribute syn_preserve of nx_frame_word_f : signal is true; attribute syn_preserve of nx_frame_word_delay_rr : signal is true; - attribute syn_preserve of nx_frame_word_delay_r : signal is true; + attribute syn_preserve of nx_frame_word_delay_reg : signal is true; begin @@ -654,7 +655,7 @@ begin timer_static_RESET_TIMEOUT: timer_static generic map ( CTR_WIDTH => 32, - CTR_END => 2000000000 -- 10s + CTR_END => 1000000000 -- 10s ) port map ( CLK_IN => CLK_IN, @@ -1469,213 +1470,216 @@ begin debug_state <= x"0"; - if (reset_handler_start_r = '1') then - -- Reset by register always wins, start it - rs_timeout_timer_reset <= '1'; - reset_timeout_flag <= '0'; - reset_handler_trigger(0) <= '1'; - reset_handler_trigger(15 downto 1) <= (others => '0'); - R_STATE <= R_START; - elsif (rs_timeout_timer_done = '1') then - -- Reset Timeout, retry RESET - rs_timeout_timer_reset <= '1'; - reset_timeout_flag <= '1'; - reset_handler_trigger(0) <= '0'; - reset_handler_trigger(1) <= '1'; - reset_handler_trigger(15 downto 2) <= (others => '0'); - R_STATE <= R_START; - else + if (disable_resets = '0') then - case R_STATE is - when R_IDLE => - if (NX_CLOCK_ON_IN = '1') then - if ((disable_adc_r = '0' and - (pll_adc_not_lock = '1' or - adc_reset_sync = '1' or - adc_frame_rate_error = '1' or - adc_error = '1' or - adc_dt_error = '1' or - adc_sclk_ok_c100 = '0' or - adc_locked_c100 = '0' - ) - ) or - nx_frame_rate_error = '1' or - startup_reset = '1' or - timestamp_dt_error = '1' or - parity_rate_error = '1' or - nx_frame_rate_error = '1' - ) then - - reset_handler_trigger(1 downto 0) <= (others => '0'); - reset_handler_trigger( 2) <= nx_frame_rate_error; - reset_handler_trigger( 3) <= startup_reset; - reset_handler_trigger( 4) <= timestamp_dt_error; - reset_handler_trigger( 5) <= parity_rate_error; - reset_handler_trigger( 6) <= nx_frame_rate_error; - reset_handler_trigger( 7) <= pll_adc_not_lock; - reset_handler_trigger( 8) <= adc_reset_sync; - reset_handler_trigger( 9) <= adc_frame_rate_error; - reset_handler_trigger(10) <= adc_error; - reset_handler_trigger(11) <= adc_dt_error ; - reset_handler_trigger(12) <= not adc_sclk_ok_c100; - reset_handler_trigger(13) <= not adc_locked_c100; - reset_handler_trigger(15 downto 4) <= (others => '0'); - - R_STATE <= R_RESET_TIMESTAMP; - else - reset_timeout_flag <= '0'; - rs_timeout_timer_reset <= '1'; - reset_handler_busy <= '0'; - R_STATE <= R_IDLE; + if (reset_handler_start_r = '1') then + -- Reset by register always wins, start it + rs_timeout_timer_reset <= '1'; + reset_timeout_flag <= '0'; + reset_handler_trigger(0) <= '1'; + reset_handler_trigger(15 downto 1) <= (others => '0'); + R_STATE <= R_START; + elsif (rs_timeout_timer_done = '1') then + -- Reset Timeout, retry RESET + rs_timeout_timer_reset <= '1'; + reset_timeout_flag <= '1'; + reset_handler_trigger(0) <= '0'; + reset_handler_trigger(1) <= '1'; + reset_handler_trigger(15 downto 2) <= (others => '0'); + R_STATE <= R_START; + else + + case R_STATE is + when R_IDLE => + if (NX_CLOCK_ON_IN = '1') then + if ((disable_adc_r = '0' and + (pll_adc_not_lock = '1' or + adc_reset_sync = '1' or + adc_frame_rate_error = '1' or + adc_error = '1' or + adc_dt_error = '1' or + adc_sclk_ok_c100 = '0' or + adc_locked_c100 = '0' + ) + ) or + nx_frame_rate_error = '1' or + startup_reset = '1' or + timestamp_dt_error = '1' or + parity_rate_error = '1' or + nx_frame_rate_error = '1' + ) then + + reset_handler_trigger(1 downto 0) <= (others => '0'); + reset_handler_trigger( 2) <= nx_frame_rate_error; + reset_handler_trigger( 3) <= startup_reset; + reset_handler_trigger( 4) <= timestamp_dt_error; + reset_handler_trigger( 5) <= parity_rate_error; + reset_handler_trigger( 6) <= nx_frame_rate_error; + reset_handler_trigger( 7) <= pll_adc_not_lock; + reset_handler_trigger( 8) <= adc_reset_sync; + reset_handler_trigger( 9) <= adc_frame_rate_error; + reset_handler_trigger(10) <= adc_error; + reset_handler_trigger(11) <= adc_dt_error ; + reset_handler_trigger(12) <= not adc_sclk_ok_c100; + reset_handler_trigger(13) <= not adc_locked_c100; + reset_handler_trigger(15 downto 4) <= (others => '0'); + + R_STATE <= R_RESET_TIMESTAMP; + else + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + reset_handler_busy <= '0'; + R_STATE <= R_IDLE; + end if; + else + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + R_STATE <= R_IDLE; end if; - else - reset_timeout_flag <= '0'; - rs_timeout_timer_reset <= '1'; - R_STATE <= R_IDLE; - end if; - debug_state <= x"1"; - - when R_START => - -- First wait 1mue for NX_MAIN_CLK, have to put lock status here - -- to check in the future. - rs_wait_timer_start <= '1'; - R_STATE <= R_WAIT_0; - debug_state <= x"2"; - - when R_WAIT_0 => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_0; - else - R_STATE <= R_WAIT_NX_ONLINE; - end if; - debug_state <= x"3"; - - when R_WAIT_NX_ONLINE => - if (nx_online_i = '0') then - R_STATE <= R_WAIT_NX_ONLINE; - else - -- Just wait again - rs_wait_timer_start <= '1'; - R_STATE <= R_WAIT_1; - end if; - debug_state <= x"4"; - - when R_WAIT_1 => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_1; - else - R_STATE <= R_RESET_TIMESTAMP; - end if; - debug_state <= x"5"; - - when R_RESET_TIMESTAMP => - -- must reset/resync Timestamp clock and data transmission clock - -- of nxyter first, afterwards wait a bit to let settle down - reset_handler_counter <= reset_handler_counter + 1; - nx_timestamp_reset_o <= '1'; - rs_wait_timer_start <= '1'; -- wait 1mue to settle - R_STATE <= R_WAIT_2; - debug_state <= x"6"; - - when R_WAIT_2 => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_2; - else - R_STATE <= R_SET_ALL_RESETS; - end if; - debug_state <= x"7"; + debug_state <= x"1"; - when R_SET_ALL_RESETS => - -- timer reset should be finished, can we check status, - -- To be done? - -- now set reset of all handlers - frame_rates_reset <= '1'; - pll_adc_sampling_clk_reset <= '1'; - adc_reset_p <= '1'; - adc_reset_handler <= '1'; - output_handler_reset <= '1'; - fifo_reset_handler <= '1'; - - -- give resets 1mue to take effect - rs_wait_timer_start <= '1'; - R_STATE <= R_WAIT_3; - debug_state <= x"3"; - - when R_WAIT_3 => - pll_adc_sampling_clk_reset <= '1'; - adc_reset_handler <= '1'; - output_handler_reset <= '1'; - fifo_reset_handler <= '1'; - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_3; - else - -- now start timeout timer and begin to release resets - -- step by step - rs_timeout_timer_start <= '1'; - R_STATE <= R_WAIT_NX_FRAME_RATE_OK; - end if; - debug_state <= x"8"; - - when R_WAIT_NX_FRAME_RATE_OK => - if (nx_frame_rate_offline = '0' and - nx_frame_rate_error = '0') then - -- Next: Release PLL Reset, i.e. sampling_clk_reset + when R_START => + -- First wait 1mue for NX_MAIN_CLK, have to put lock status here + -- to check in the future. + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_0; + debug_state <= x"2"; + + when R_WAIT_0 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_0; + else + R_STATE <= R_WAIT_NX_ONLINE; + end if; + debug_state <= x"3"; + + when R_WAIT_NX_ONLINE => + if (nx_online_i = '0') then + R_STATE <= R_WAIT_NX_ONLINE; + else + -- Just wait again + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_1; + end if; + debug_state <= x"4"; + + when R_WAIT_1 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_1; + else + R_STATE <= R_RESET_TIMESTAMP; + end if; + debug_state <= x"5"; + + when R_RESET_TIMESTAMP => + -- must reset/resync Timestamp clock and data transmission clock + -- of nxyter first, afterwards wait a bit to let settle down + reset_handler_counter <= reset_handler_counter + 1; + nx_timestamp_reset_o <= '1'; + rs_wait_timer_start <= '1'; -- wait 1mue to settle + R_STATE <= R_WAIT_2; + debug_state <= x"6"; + + when R_WAIT_2 => + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_2; + else + R_STATE <= R_SET_ALL_RESETS; + end if; + debug_state <= x"7"; + + when R_SET_ALL_RESETS => + -- timer reset should be finished, can we check status, + -- To be done? + -- now set reset of all handlers + frame_rates_reset <= '1'; + pll_adc_sampling_clk_reset <= '1'; + adc_reset_p <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; - if (disable_adc_r = '0') then - R_STATE <= R_PLL_WAIT_LOCK; - else - R_STATE <= R_WAIT_DATA_HANDLER_OK; - end if; - else + + -- give resets 1mue to take effect + rs_wait_timer_start <= '1'; + R_STATE <= R_WAIT_3; + debug_state <= x"3"; + + when R_WAIT_3 => pll_adc_sampling_clk_reset <= '1'; adc_reset_handler <= '1'; output_handler_reset <= '1'; fifo_reset_handler <= '1'; - R_STATE <= R_WAIT_NX_FRAME_RATE_OK; - end if; - debug_state <= x"9"; - - when R_PLL_WAIT_LOCK => - if (adc_sclk_ok_c100 = '1' and - pll_adc_not_lock = '0') then - -- Next: Release ADC Reset - output_handler_reset <= '1'; - fifo_reset_handler <= '1'; - R_STATE <= R_WAIT_ADC_OK; - else - adc_reset_handler <= '1'; - output_handler_reset <= '1'; - fifo_reset_handler <= '1'; - R_STATE <= R_PLL_WAIT_LOCK; - end if; - debug_state <= x"6"; - - when R_WAIT_ADC_OK => - if (adc_locked_c100 = '1' and - adc_frame_rate_error = '0') then - -- Next: Release Output Handler and Clock Domain transfer Fifo - -- Resets - R_STATE <= R_WAIT_DATA_HANDLER_OK; - else - output_handler_reset <= '1'; - fifo_reset_handler <= '1'; - R_STATE <= R_WAIT_ADC_OK; - end if; - debug_state <= x"a"; - - when R_WAIT_DATA_HANDLER_OK => - if (frame_rate_error = '0') then - startup_reset <= '0'; - reset_timeout_flag <= '0'; - rs_timeout_timer_reset <= '1'; - R_STATE <= R_IDLE; - else - R_STATE <= R_WAIT_DATA_HANDLER_OK; - end if; - debug_state <= x"b"; - end case; + if (rs_wait_timer_done = '0') then + R_STATE <= R_WAIT_3; + else + -- now start timeout timer and begin to release resets + -- step by step + rs_timeout_timer_start <= '1'; + R_STATE <= R_WAIT_NX_FRAME_RATE_OK; + end if; + debug_state <= x"8"; + + when R_WAIT_NX_FRAME_RATE_OK => + if (nx_frame_rate_offline = '0' and + nx_frame_rate_error = '0') then + -- Next: Release PLL Reset, i.e. sampling_clk_reset + adc_reset_handler <= '1'; + output_handler_reset <= '1'; + fifo_reset_handler <= '1'; + if (disable_adc_r = '0') then + R_STATE <= R_PLL_WAIT_LOCK; + else + R_STATE <= R_WAIT_DATA_HANDLER_OK; + end if; + else + pll_adc_sampling_clk_reset <= '1'; + adc_reset_handler <= '1'; + output_handler_reset <= '1'; + fifo_reset_handler <= '1'; + R_STATE <= R_WAIT_NX_FRAME_RATE_OK; + end if; + debug_state <= x"9"; + + when R_PLL_WAIT_LOCK => + if (adc_sclk_ok_c100 = '1' and + pll_adc_not_lock = '0') then + -- Next: Release ADC Reset + output_handler_reset <= '1'; + fifo_reset_handler <= '1'; + R_STATE <= R_WAIT_ADC_OK; + else + adc_reset_handler <= '1'; + output_handler_reset <= '1'; + fifo_reset_handler <= '1'; + R_STATE <= R_PLL_WAIT_LOCK; + end if; + debug_state <= x"6"; + + when R_WAIT_ADC_OK => + if (adc_locked_c100 = '1' and + adc_frame_rate_error = '0') then + -- Next: Release Output Handler and Clock Domain transfer Fifo + -- Resets + R_STATE <= R_WAIT_DATA_HANDLER_OK; + else + output_handler_reset <= '1'; + fifo_reset_handler <= '1'; + R_STATE <= R_WAIT_ADC_OK; + end if; + debug_state <= x"a"; + + when R_WAIT_DATA_HANDLER_OK => + if (frame_rate_error = '0') then + startup_reset <= '0'; + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + R_STATE <= R_IDLE; + else + R_STATE <= R_WAIT_DATA_HANDLER_OK; + end if; + debug_state <= x"b"; + end case; + end if; end if; end if; end if; @@ -1825,7 +1829,7 @@ begin new_timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); - nx_frame_word_delay_r <= (others => '0'); + nx_frame_word_delay_reg <= (others => '0'); else fifo_full_r <= fifo_full_rr; fifo_empty_r <= fifo_empty_rr; @@ -1834,7 +1838,7 @@ begin new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; - nx_frame_word_delay_r <= nx_frame_word_delay_rr; + nx_frame_word_delay_reg <= nx_frame_word_delay_rr; end if; end if; end process PROC_SLAVE_BUS_BUFFER; @@ -1865,6 +1869,7 @@ begin adc_sloppy_frame <= '0'; reset_inhibit_r <= '0'; + disable_resets <= '0'; else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -1885,7 +1890,8 @@ begin when x"0001" => slv_data_out_o(0) <= reset_handler_busy; slv_data_out_o(1) <= reset_timeout_flag; - slv_data_out_o(15 downto 2) <= (others => '0'); + slv_data_out_o(2) <= disable_resets; + slv_data_out_o(15 downto 3) <= (others => '0'); slv_data_out_o(31 downto 16) <= reset_handler_trigger; slv_ack_o <= '1'; @@ -2008,172 +2014,11 @@ begin slv_unknown_addr_o <= '1'; end case; - -- case SLV_ADDR_IN is - -- when x"0000" => - -- slv_data_out_o(15 downto 0) <= error_status_bits; - -- slv_data_out_o(31 downto 16) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0001" => - -- slv_data_out_o(0) <= reset_handler_busy; - -- slv_data_out_o(1) <= reset_timeout_flag; - -- slv_data_out_o(31 downto 2) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0002" => - -- slv_data_out_o(27 downto 0) <= std_logic_vector(frame_rate); - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0003" => - -- slv_data_out_o(27 downto 0) <= std_logic_vector(nx_frame_rate); - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0004" => - -- slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate); - -- slv_data_out_o(30 downto 28) <= (others => '0'); - -- slv_data_out_o(31) <= disable_adc_r; - -- slv_ack_o <= '1'; - -- - -- when x"0005" => - -- slv_data_out_o(27 downto 0) <= parity_err_rate; - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0006" => - -- slv_data_out_o(15 downto 0) <= reset_handler_counter; - -- slv_data_out_o(31 downto 6) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0007" => - -- slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr); - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0008" => - -- slv_data_out_o(7 downto 0) <= - -- std_logic_vector(adc_notlock_ctr_r); - -- slv_data_out_o(31 downto 8) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0009" => - -- slv_data_out_o(11 downto 0) <= merge_error_ctr_r; - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000a" => - -- slv_data_out_o(11 downto 0) <= - -- std_logic_vector(resync_counter); - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000b" => - -- slv_data_out_o(11 downto 0) <= - -- std_logic_vector(parity_error_counter); - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000c" => - -- slv_data_out_o(11 downto 0) <= - -- std_logic_vector(pll_adc_not_lock_ctr); - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000d" => - -- slv_data_out_o(3 downto 0) <= - -- std_logic_vector(pll_adc_sample_clk_dphase_r); - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000e" => - -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb_r; - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"000f" => - -- slv_data_out_o(1 downto 0) <= johnson_counter_sync_r; - -- slv_data_out_o(31 downto 2) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0010" => - -- slv_data_out_o(2 downto 0) <= - -- std_logic_vector(nx_timestamp_delay_s); - -- slv_data_out_o(3) <= '0'; - -- slv_data_out_o(5 downto 4) <= - -- std_logic_vector(nx_frame_word_delay_r); - -- slv_data_out_o(14 downto 6) <= (others => '0'); - -- slv_data_out_o(15) <= nx_timestamp_delay_adjust; - -- slv_data_out_o(31 downto 16) <= nx_timestamp_delay_actr; - -- slv_ack_o <= '1'; - -- - -- when x"0011" => - -- slv_data_out_o(0) <= fifo_full_r; - -- slv_data_out_o(1) <= fifo_empty_r; - -- slv_data_out_o(2) <= '0'; - -- slv_data_out_o(3) <= '0'; - -- slv_data_out_o(4) <= '0'; - -- slv_data_out_o(5) <= '0'; - -- slv_data_out_o(29 downto 6) <= (others => '0'); - -- slv_data_out_o(30) <= '0'; - -- slv_data_out_o(31) <= nx_frame_synced_r; - -- slv_ack_o <= '1'; - -- - -- when x"0012" => - -- slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift); - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0013" => - -- slv_data_out_o <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0014" => - -- slv_data_out_o(11 downto 0) <= new_adc_dt_error_ctr_r; - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0015" => - -- slv_data_out_o(11 downto 0) <= new_timestamp_dt_error_ctr_r; - -- slv_data_out_o(31 downto 12) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0016" => - -- slv_data_out_o(27 downto 0) <= - -- std_logic_vector(adc_notlock_counter); - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0017" => - -- slv_data_out_o(27 downto 0) <= - -- std_logic_vector(adc_error_counter); - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"0018" => - -- slv_data_out_o(27 downto 0) <= - -- std_logic_vector(adc_error_undef_counter); - -- slv_data_out_o(31 downto 28) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"001e" => - -- slv_data_out_o(2 downto 0) <= debug_mode; - -- slv_data_out_o(31 downto 3) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when x"001f" => - -- slv_data_out_o(3 downto 0) <= adc_debug_type_r; - -- slv_data_out_o(31 downto 4) <= (others => '0'); - -- slv_ack_o <= '1'; - -- - -- when others => - -- slv_unknown_addr_o <= '1'; - -- end case; - elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0001" => - reset_handler_start_r <= '1'; + reset_handler_start_r <= SLV_DATA_IN(0); + disable_resets <= SLV_DATA_IN(2); slv_ack_o <= '1'; when x"0004" => @@ -2228,70 +2073,6 @@ begin slv_unknown_addr_o <= '1'; end case; - - -- case SLV_ADDR_IN is - -- when x"0001" => - -- reset_handler_start_r <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"0004" => - -- disable_adc_r <= SLV_DATA_IN(31); - -- slv_ack_o <= '1'; - -- - -- when x"000a" => - -- reset_resync_ctr <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000b" => - -- reset_parity_error_ctr <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000c" => - -- pll_adc_not_lock_ctr_clear <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000d" => - -- pll_adc_sample_clk_dphase_r <= - -- unsigned(SLV_DATA_IN(3 downto 0)); - -- reset_handler_start_r <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000e" => - -- pll_adc_sample_clk_finedelb_r <= SLV_DATA_IN(3 downto 0); - -- reset_handler_start_r <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"000f" => - -- johnson_counter_sync_r - -- <= unsigned(SLV_DATA_IN(1 downto 0)) + 1; - -- reset_handler_start_r <= '1'; - -- slv_ack_o <= '1'; - -- - -- when x"0010" => - -- nx_timestamp_delay_r <= - -- unsigned(SLV_DATA_IN(2 downto 0)); - -- nx_timestamp_delay_adjust <= SLV_DATA_IN(15); - -- slv_ack_o <= '1'; - -- - -- when x"0012" => - -- adc_bit_shift <= - -- unsigned(SLV_DATA_IN(3 downto 0)); - -- slv_ack_o <= '1'; - -- - -- when x"001e" => - -- debug_mode <= SLV_DATA_IN(2 downto 0); - -- slv_ack_o <= '1'; - -- - -- when x"001f" => - -- adc_debug_type_r <= - -- unsigned(SLV_DATA_IN(3 downto 0)); - -- slv_ack_o <= '1'; - -- - -- when others => - -- slv_unknown_addr_o <= '1'; - -- - -- end case; - end if; end if; end if; diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index d251f27..ba84272 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -100,7 +100,7 @@ MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cn MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_rr*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_reg*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; -- 2.43.0