From 72e8400b21ba0cc6aeeed4287aefadc0cfaf6a76 Mon Sep 17 00:00:00 2001 From: palka Date: Thu, 26 Jun 2008 12:49:59 +0000 Subject: [PATCH] vulom files --- oldfiles/vulom3/beam_ramp.vhd | 259 ++ oldfiles/vulom3/bus_data_com5.vhd | 699 +++++ oldfiles/vulom3/clocking.vhd | 168 ++ oldfiles/vulom3/compile_vulom3.pl | 143 ++ oldfiles/vulom3/delay.vhd | 60 + oldfiles/vulom3/downscale.vhd | 74 + oldfiles/vulom3/eco_delay.vhd | 51 + oldfiles/vulom3/impact_batch_vulom3.txt | 6 + oldfiles/vulom3/new_downscale_ck.vhd | 113 + oldfiles/vulom3/one_clock_long.vhd | 48 + oldfiles/vulom3/one_clock_long_test.vhd | 96 + oldfiles/vulom3/scaler.vhd | 59 + oldfiles/vulom3/scaler_s.vhd | 68 + oldfiles/vulom3/set_width.vhd | 69 + oldfiles/vulom3/set_width_special.vhd | 79 + oldfiles/vulom3/trig_box1.vhd | 895 +++++++ oldfiles/vulom3/trigger_box1.stapl | 3106 +++++++++++++++++++++++ oldfiles/vulom3/ulogic.vhd | 320 +++ oldfiles/vulom3/vlogic_1.prj | 15 + oldfiles/vulom3/vlogic_1.sdc | 57 + oldfiles/vulom3/vlogic_1.ucf | 249 ++ oldfiles/vulom3/vlogic_1.vhd | 261 ++ oldfiles/vulom3/vlogic_1_syn.prj | 76 + oldfiles/vulom3/vmelogic.vhd | 247 ++ 24 files changed, 7218 insertions(+) create mode 100644 oldfiles/vulom3/beam_ramp.vhd create mode 100644 oldfiles/vulom3/bus_data_com5.vhd create mode 100644 oldfiles/vulom3/clocking.vhd create mode 100755 oldfiles/vulom3/compile_vulom3.pl create mode 100644 oldfiles/vulom3/delay.vhd create mode 100644 oldfiles/vulom3/downscale.vhd create mode 100644 oldfiles/vulom3/eco_delay.vhd create mode 100644 oldfiles/vulom3/impact_batch_vulom3.txt create mode 100644 oldfiles/vulom3/new_downscale_ck.vhd create mode 100644 oldfiles/vulom3/one_clock_long.vhd create mode 100644 oldfiles/vulom3/one_clock_long_test.vhd create mode 100644 oldfiles/vulom3/scaler.vhd create mode 100644 oldfiles/vulom3/scaler_s.vhd create mode 100644 oldfiles/vulom3/set_width.vhd create mode 100644 oldfiles/vulom3/set_width_special.vhd create mode 100644 oldfiles/vulom3/trig_box1.vhd create mode 100644 oldfiles/vulom3/trigger_box1.stapl create mode 100644 oldfiles/vulom3/ulogic.vhd create mode 100644 oldfiles/vulom3/vlogic_1.prj create mode 100644 oldfiles/vulom3/vlogic_1.sdc create mode 100644 oldfiles/vulom3/vlogic_1.ucf create mode 100644 oldfiles/vulom3/vlogic_1.vhd create mode 100644 oldfiles/vulom3/vlogic_1_syn.prj create mode 100644 oldfiles/vulom3/vmelogic.vhd diff --git a/oldfiles/vulom3/beam_ramp.vhd b/oldfiles/vulom3/beam_ramp.vhd new file mode 100644 index 0000000..c28fcd4 --- /dev/null +++ b/oldfiles/vulom3/beam_ramp.vhd @@ -0,0 +1,259 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 26/6/07 +-- Design Name: vulom3 +-- Module Name: beam_ramp - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Programmable delayer and shaper for beam signal +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity beam_ramp is + port ( clk_300MHz : in std_logic; + clk_50MHz : in std_logic; + input : in std_logic; + output_inhibit : out std_logic; + output_external : out std_logic; + delay_value : in std_logic_vector(7 downto 0); + width_value_inhibit : in std_logic_vector(7 downto 0); + width_value_external : in std_logic_vector(7 downto 0) + ); +end beam_ramp; + +architecture Behavioral of beam_ramp is + +signal count_ck : std_logic_vector(23 downto 0); +signal clk_10Hz : std_logic; +signal input_r, input_q, output_s_inhibit, output_s_external : std_logic; +signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0); +type state_type is (reset, del, wid); +signal state : state_type; + + + +begin + + ck: process(clk_50MHz) + begin + if rising_edge(clk_50MHz) then + if count_ck = x"2625a0" then --2,5e6 + count_ck <= x"000000"; + clk_10Hz <= not clk_10Hz; + else + count_ck <= count_ck + 1; + end if; + + output_inhibit <= output_s_inhibit; + output_external <= output_s_external; + + end if; + end process; + + latch: process(clk_300MHz) + begin + if rising_edge(clk_300MHz) then + if input_r = '1' then + input_q <= '0'; + elsif input = '1' then + input_q <= '1'; + end if; + + end if; + end process; + + fsm : process(clk_10Hz) + begin + if rising_edge(clk_10Hz) then + case (state) is + + when reset => + input_r <= '0'; + count_delay <=delay_value; + count_width_inhibit <= width_value_inhibit; + count_width_external <= width_value_external + width_value_inhibit; + if input_q = '0' then + state <= reset; + else + state <= del; + end if; + +-- when reset => +-- input_r <= '0'; +-- count_delay <=delay_value; +-- count_width_inhibit <= width_value_inhibit + 1; +-- count_width_external <= width_value_external + 1; +-- if input_q = '0' then +-- state <= reset; +-- else +-- state <= del; +-- end if; + + when del => + if count_delay = x"00" then + state <= wid; + else + count_delay <= count_delay - 1; + state <= del; + end if; + + when wid => + input_r <= '1'; + if (count_width_inhibit = x"00" and count_width_external = x"00") then + output_s_inhibit <= '0'; + output_s_external <= '0'; + state <= reset; + elsif count_width_external = x"00" then + output_s_inhibit <= '1'; + output_s_external <= '0'; + count_width_inhibit <= count_width_inhibit - 1; + state <= wid; + elsif count_width_inhibit = x"00" then + output_s_inhibit <= '0'; + output_s_external <= '1'; + count_width_external <= count_width_external - 1; + state <= wid; + else + output_s_inhibit <= '1'; + output_s_external <= '1'; + count_width_inhibit <= count_width_inhibit - 1; + count_width_external <= count_width_external - 1; + state <= wid; + end if; + + when others => + state <= reset; + + end case; + end if; + end process; + + + +end Behavioral; + + + + + + + +--entity beam_ramp is +-- port ( clk_300MHz : in std_logic; +-- clk_50MHz : in std_logic; +-- input : in std_logic; +-- output_inhibit : out std_logic; +-- output_external : out std_logic; +-- delay_value : in std_logic_vector(7 downto 0); +-- width_value_inhibit : in std_logic_vector(7 downto 0); +-- width_value_external : in std_logic_vector(7 downto 0) +-- ); +--end beam_ramp; +-- +--architecture Behavioral of beam_ramp is +-- +--signal count_ck : std_logic_vector(24 downto 0); +--signal clk_10Hz : std_logic; +--signal input_r, input_q, output_s_inhibit, output_s_external : std_logic; +--signal count_delay, count_width_inhibit, count_width_external : std_logic_vector(7 downto 0); +--type state_type is (reset, del, wid); +--signal state : state_type; +-- +-- +-- +--begin +-- +-- ck: process(clk_50MHz) +-- begin +-- if rising_edge(clk_50MHz) then +-- count_ck <= count_ck + 1; +-- clk_10Hz <= count_ck(22); +-- +-- output_inhibit <= output_s_inhibit; +-- output_external <= output_s_external; +-- +-- end if; +-- end process; +-- +-- latch: process(clk_300MHz) +-- begin +-- if rising_edge(clk_300MHz) then +-- if input_r = '1' then +-- input_q <= '0'; +-- elsif input = '1' then +-- input_q <= '1'; +-- end if; +-- +-- end if; +-- end process; +-- +-- fsm : process(clk_10Hz) +-- begin +-- if rising_edge(clk_10Hz) then +-- case (state) is +-- +-- when reset => +-- input_r <= '0'; +-- count_delay <=delay_value; +-- count_width_inhibit <= width_value_inhibit + 1; +-- count_width_external <= width_value_external + 1; +-- if input_q = '0' then +-- state <= reset; +-- else +-- state <= del; +-- end if; +-- +-- when del => +-- if count_delay = x"00" then +-- state <= wid; +-- else +-- count_delay <= count_delay - 1; +-- state <= del; +-- end if; +-- +-- when wid => +-- input_r <= '1'; +-- if (count_width_inhibit = x"00" and count_width_external = x"00") then +-- output_s_inhibit <= '0'; +-- output_s_external <= '0'; +-- state <= reset; +-- elsif count_width_external = x"00" then +-- output_s_inhibit <= '1'; +-- output_s_external <= '0'; +-- count_width_inhibit <= count_width_inhibit - 1; +-- state <= wid; +-- elsif count_width_inhibit = x"00" then +-- output_s_inhibit <= '0'; +-- output_s_external <= '1'; +-- count_width_external <= count_width_external - 1; +-- state <= wid; +-- else +-- output_s_inhibit <= '1'; +-- output_s_external <= '1'; +-- count_width_inhibit <= count_width_inhibit - 1; +-- count_width_external <= count_width_external - 1; +-- state <= wid; +-- end if; +-- +-- when others => +-- state <= reset; +-- +-- end case; +-- end if; +-- end process; +-- +-- +-- +--end Behavioral; \ No newline at end of file diff --git a/oldfiles/vulom3/bus_data_com5.vhd b/oldfiles/vulom3/bus_data_com5.vhd new file mode 100644 index 0000000..861f5a1 --- /dev/null +++ b/oldfiles/vulom3/bus_data_com5.vhd @@ -0,0 +1,699 @@ +---------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 09:54:15 07/11/2007 +-- Design Name: vulom3 +-- Module Name: bus_data_com4 - Behavioral +-- Project Name: triggerbox +-- Target Devices: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Data communication to TRB +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: Whole datastream with 16 bit summer usead as error check +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity bus_data_com5 is + PORT( + clk_300MHz : in std_logic; + clk_100MHz : in std_logic; + gts_pulse : in std_logic; + cal_trigger : in std_logic; + bus_busy : in std_logic; -- not used + bus_ack : in std_logic; + bus_retx : in std_logic; + latch : in std_logic_vector(6 downto 0); + latch_dsc : in std_logic_vector(6 downto 0); + scaler_pti1 : in std_logic_vector(31 downto 0); + scaler_pti2 : in std_logic_vector(31 downto 0); + scaler_pti3 : in std_logic_vector(31 downto 0); + scaler_pti4 : in std_logic_vector(31 downto 0); + scaler_pti5 : in std_logic_vector(31 downto 0); + scaler_ts : in std_logic_vector(31 downto 0); + scaler_vs : in std_logic_vector(31 downto 0); + scaler_dead : in std_logic_vector(31 downto 0); + bus_inhibit : out std_logic; + dtu_inhibit : out std_logic; + ecl_bus_data : out std_logic_vector(1 downto 0); + ecl_bus_clk : out std_logic; + com_run : in std_logic; + dtu_bus_t : out std_logic; + dtu_bus_ts : out std_logic; + dtu_bus_td : out std_logic_vector (3 downto 0); + out_inhibit : in std_logic + ); + +end bus_data_com5; + +architecture Behavioral of bus_data_com5 is +signal count : integer range 0 to 300 := 0; +signal tag_counter_trb, tag_counter_dtu : std_logic_vector(15 downto 0):=x"0000"; +signal cal_trigger_s, cal_trigger_d1, cal_trigger_pulse, cal_trigger_pulse_d, bus_busy_s, bus_busy_d1 : std_logic := '0'; +type state_type_a is (ready, start_sequence_0, start_sequence_1, start_sequence_2, start_sequence_3, + start_sequence_4, start_sequence_5, start_sequence_6, start_sequence_7, + normal_code_0, normal_code_1, calib_code_0, calib_code_1, + xfer_0, xfer_0alter, xfer_1, xfer_2, xfer_3, xfer_4, xfer_5, xfer_6, + xfer_7, xfer_8, xfer_9, xfer_10, xfer_11, xfer_12, xfer_13, xfer_14, xfer_15, + wait_for_busy, hold_busy); +signal state_a : state_type_a; +type state_type_b is (tag, latches, scalers_0, scalers_1, scalers_2, scalers_3, scalers_4, scalers_5, + scalers_6, scalers_7, scalers_8, scalers_9, scalers_10, scalers_11, scalers_12, + scalers_13, scalers_14, scalers_15, checksum_0, checksum_1, finished); +signal state_b : state_type_b; +type state_type_c is (idle, begin_run_0, begin_run_1, end_run_0, end_run_1, norm_event_0, norm_event_1, + calib_event_0, calib_event_1, tag_low_0, tag_low_1, tag_high_0, tag_high_1, + tag_prio_0, tag_prio_1, wait_last, count_incr, wait_for_trb); +signal state_c : state_type_c; + +signal xfer_buffer : std_logic_vector(15 downto 0):=x"0000"; +signal latch_s, latch_dsc_s : std_logic_vector(6 downto 0):="0000000"; +signal gts_trb_r, gts_trb_q, gts_q_d, gts_dtu_r, gts_dtu_q : std_logic := '0'; +signal checksum : std_logic_vector(31 downto 0):=x"00000000"; +signal scaler_pti1_s, scaler_pti2_s, scaler_pti3_s, scaler_pti4_s, scaler_pti5_s, scaler_ts_s, + scaler_vs_s, scaler_dead_s : std_logic_vector(31 downto 0); +signal com_run_s, trb_run, trb_run_s, bus_ack_s, bus_retx_s : std_logic:='0'; +signal ack_accu, retx_accu : std_logic_vector(3 downto 0); +signal gts_from_trb, cal_trigger_from_trb : std_logic:='0'; +signal trb_go_norm, trb_go_norm_s, trb_go_calib, trb_go_calib_s, trb_finished : std_logic; +signal dtu_start : std_logic; + +begin + + delay : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + scaler_pti1_s <= scaler_pti1; + scaler_pti2_s <= scaler_pti2; + scaler_pti3_s <= scaler_pti3; + scaler_pti4_s <= scaler_pti4; + scaler_pti5_s <= scaler_pti5; + scaler_ts_s <= scaler_ts; + scaler_vs_s <= scaler_vs; + scaler_dead_s <= scaler_dead; + latch_s <= latch; + latch_dsc_s <= latch_dsc; + bus_busy_s <= bus_busy; + bus_ack_s <= bus_ack; + bus_retx_s <= bus_retx; + end if; + end process; + + + input_gts : process(clk_300MHz) + begin + if rising_edge(clk_300MHz) then + if gts_dtu_r = '1' then --gts latch for trb bus + gts_dtu_q <= '0'; + elsif gts_pulse = '1' then + gts_dtu_q <= '1'; + end if; + + dtu_inhibit <= (not com_run) or dtu_start; + end if; + end process; + + + input_cal : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + cal_trigger_s <= cal_trigger; + cal_trigger_d1 <= cal_trigger_s; + cal_trigger_pulse <= cal_trigger_s and not cal_trigger_d1 and not out_inhibit; + end if; + end process; + +---------------------------------------------------------------------- TRB comm + + fsm : process(clk_100MHz) --TX lenght: 3.1-3.2 µs + begin + if rising_edge(clk_100MHz) then + case state_a is + + when ready => + ecl_bus_data <= "00"; + ecl_bus_clk <= '0'; + bus_inhibit <= '0'; + trb_finished <= '1'; + trb_go_norm_s <= trb_go_norm; + trb_go_calib_s <= trb_go_calib; + if (trb_go_norm or trb_go_calib) = '1' then + state_a <= start_sequence_0; + else state_a <= ready; + end if; +---------------------------- + when start_sequence_0 => + trb_finished <= '0'; + bus_inhibit <= '1'; + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + ack_accu <= "0000"; + retx_accu <= "0000"; + state_a <= start_sequence_1; + + when start_sequence_1 => + gts_trb_r <= '1'; + ecl_bus_clk <= '1'; + state_a <= start_sequence_2; + + when start_sequence_2 => + ecl_bus_data <= "10"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_3; + + when start_sequence_3 => + ecl_bus_clk <= '1'; + state_a <= start_sequence_4; + + when start_sequence_4 => + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_5; + + when start_sequence_5 => + ecl_bus_clk <= '1'; + state_a <= start_sequence_6; + + when start_sequence_6 => + ecl_bus_data <= "10"; + ecl_bus_clk <= '0'; + state_a <= start_sequence_7; + + when start_sequence_7 => + ecl_bus_clk <= '1'; + if trb_go_norm_s = '1' then + state_a <= normal_code_0; + elsif trb_go_calib_s = '1' then + state_a <= calib_code_0; + else state_a <= ready; + end if; +---------------------------------------------- + when normal_code_0 => + ecl_bus_data <= "01"; + ecl_bus_clk <= '0'; + state_a <= normal_code_1; + + when normal_code_1 => + checksum <= x"00000001"; + ecl_bus_clk <= '1'; + state_a <= xfer_0; + + when calib_code_0 => + ecl_bus_data <= "11"; + ecl_bus_clk <= '0'; + state_a <= calib_code_1; + + when calib_code_1 => + checksum <= x"00000003"; + ecl_bus_clk <= '1'; + state_a <= xfer_0; +--------------------------------------------------- + when xfer_0 => + checksum <= checksum + xfer_buffer; + ecl_bus_data <= xfer_buffer(1 downto 0); + ecl_bus_clk <= '0'; + state_a <= xfer_1; + + when xfer_0alter => + ecl_bus_data <= xfer_buffer(1 downto 0); + ecl_bus_clk <= '0'; + state_a <= xfer_1; + + when xfer_1 => + ecl_bus_clk <= '1'; + state_a <= xfer_2; + + when xfer_2 => + ecl_bus_data <= xfer_buffer(3 downto 2); + ecl_bus_clk <= '0'; + state_a <= xfer_3; + + when xfer_3 => + ecl_bus_clk <= '1'; + state_a <= xfer_4; + + when xfer_4 => + ecl_bus_data <= xfer_buffer(5 downto 4); + ecl_bus_clk <= '0'; + state_a <= xfer_5; + + when xfer_5 => + ecl_bus_clk <= '1'; + state_a <= xfer_6; + + when xfer_6 => + ecl_bus_data <= xfer_buffer(7 downto 6); + ecl_bus_clk <= '0'; + state_a <= xfer_7; + + when xfer_7 => + ecl_bus_clk <= '1'; + state_a <= xfer_8; + + when xfer_8 => + ecl_bus_data <= xfer_buffer(9 downto 8); + ecl_bus_clk <= '0'; + state_a <= xfer_9; + + when xfer_9 => + ecl_bus_clk <= '1'; + state_a <= xfer_10; + + when xfer_10 => + ecl_bus_data <= xfer_buffer(11 downto 10); + ecl_bus_clk <= '0'; + state_a <= xfer_11; + + when xfer_11 => + ecl_bus_clk <= '1'; + state_a <= xfer_12; + + when xfer_12 => + ecl_bus_data <= xfer_buffer(13 downto 12); + ecl_bus_clk <= '0'; + state_a <= xfer_13; + + when xfer_13 => + ecl_bus_clk <= '1'; + state_a <= xfer_14; + + when xfer_14 => + ecl_bus_data <= xfer_buffer(15 downto 14); + ecl_bus_clk <= '0'; + state_a <= xfer_15; + + when xfer_15 => + ecl_bus_clk <= '1'; + state_a <= xfer_6; + if state_b = checksum_0 then + state_a <= xfer_0alter; + elsif state_b = checksum_1 then + state_a <= xfer_0alter; + elsif state_b = finished then + state_a <= wait_for_busy; + else state_a <= xfer_0; + end if; +----------------------------------------------------- + when wait_for_busy => + ecl_bus_clk <= '0'; + ecl_bus_data <= "00"; + state_a <= hold_busy; + + when hold_busy => + if bus_ack_s = '0' and ack_accu /= "0000" then --ack accumulator + ack_accu <= ack_accu - 1; + elsif bus_ack_s = '1' and ack_accu /= "1111" then + ack_accu <= ack_accu + 1; + end if; + + if bus_retx_s = '0' and retx_accu /= "0000" then --retransmit accumulator + retx_accu <= retx_accu - 1; + elsif bus_retx_s = '1' and retx_accu /= "1111" then + retx_accu <= retx_accu + 1; + end if; + + if retx_accu = 10 then + state_a <= start_sequence_0; + elsif (ack_accu = 10 or com_run = '0') then + state_a <= ready; + else state_a <= hold_busy; + end if; +--------------------------------------------------------------------- + when others => + state_a <= ready; + + end case; + end if; + end process; + + + fsm2 : process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + case state_b is + + when tag => + xfer_buffer <= tag_counter_dtu - 1; + if state_a = xfer_13 then + state_b <= latches; + else state_b <= tag; + end if; + + when latches => + xfer_buffer <= '0' & latch_dsc_s & '0' & latch_s; + if state_a = xfer_13 then + state_b <= scalers_0; + else state_b <= latches; + end if; + + when scalers_0 => + xfer_buffer <= scaler_pti1_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_1; + else state_b <= scalers_0; + end if; + + when scalers_1 => + xfer_buffer <= scaler_pti1_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_2; + else state_b <= scalers_1; + end if; + + when scalers_2 => + xfer_buffer <= scaler_pti2_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_3; + else state_b <= scalers_2; + end if; + + when scalers_3 => + xfer_buffer <= scaler_pti2_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_4; + else state_b <= scalers_3; + end if; + + when scalers_4 => + xfer_buffer <= scaler_pti3_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_5; + else state_b <= scalers_4; + end if; + + when scalers_5 => + xfer_buffer <= scaler_pti3_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_6; + else state_b <= scalers_5; + end if; + + when scalers_6 => + xfer_buffer <= scaler_pti4_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_7; + else state_b <= scalers_6; + end if; + + when scalers_7 => + xfer_buffer <= scaler_pti4_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_8; + else state_b <= scalers_7; + end if; + + when scalers_8 => + xfer_buffer <= scaler_pti5_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_9; + else state_b <= scalers_8; + end if; + + when scalers_9 => + xfer_buffer <= scaler_pti5_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_10; + else state_b <= scalers_9; + end if; + + when scalers_10 => + xfer_buffer <= scaler_ts_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_11; + else state_b <= scalers_10; + end if; + + when scalers_11 => + xfer_buffer <= scaler_ts_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_12; + else state_b <= scalers_11; + end if; + + when scalers_12 => + xfer_buffer <= scaler_vs_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_13; + else state_b <= scalers_12; + end if; + + when scalers_13 => + xfer_buffer <= scaler_vs_s(31 downto 16); + if state_a = xfer_13 then + state_b <= scalers_14; + else state_b <= scalers_13; + end if; + + when scalers_14 => + xfer_buffer <= scaler_dead_s(15 downto 0); + if state_a = xfer_13 then + state_b <= scalers_15; + else state_b <= scalers_14; + end if; + + when scalers_15 => + xfer_buffer <= scaler_dead_s(31 downto 16); + if state_a = xfer_13 then + state_b <= checksum_0; + else state_b <= scalers_15; + end if; + + when checksum_0 => + xfer_buffer <= checksum(15 downto 0); + if state_a = xfer_13 then + state_b <= checksum_1; + else state_b <= checksum_0; + end if; + + when checksum_1 => + xfer_buffer <= checksum(31 downto 16); + if state_a = xfer_13 then + state_b <= finished; + else state_b <= checksum_1; + end if; + + when finished => + xfer_buffer <= x"0000"; + if state_a = wait_for_busy then + state_b <= tag; + else state_b <= finished; + end if; + + when others => + state_b <= tag; + + end case; + end if; + end process; +---------------------------------------------------------------------- DTU comm + fsm3 : process(clk_100MHz) --TX lenght: 470 ns + wait time (currently 2.5 µs total) + begin + if rising_edge(clk_100MHz) then + case state_c is + + when idle => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"d"; + count <= 0; + trb_go_norm <= '0'; + trb_go_calib <= '0'; + gts_dtu_r <= '0'; + dtu_start <= '0'; + com_run_s <= com_run; + if com_run = '1' and com_run_s = '0' then + state_c <= begin_run_0; + elsif com_run = '0' and com_run_s = '1' then + state_c <= end_run_0; + elsif gts_dtu_q = '1' and com_run = '1' then + state_c <= norm_event_0; + elsif cal_trigger_pulse = '1' and com_run = '1' then + state_c <= calib_event_0; + else state_c <= idle; + end if; +------------------------------------ + when begin_run_0 => + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"d"; + tag_counter_dtu <= x"0000"; + dtu_start <= '1'; + count <= count + 1; + if count = 4 then + state_c <= begin_run_1; + else state_c <= begin_run_0; + end if; + + when begin_run_1 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 9 then + state_c <= tag_low_0; + else state_c <= begin_run_1; + end if; +------------------------------------- + when end_run_0 => + trb_run_s <= '0'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"e"; + count <= count + 1; + if count = 4 then + state_c <= end_run_1; + else state_c <= end_run_0; + end if; + + when end_run_1 => + trb_run <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 9 then + state_c <= tag_low_0; + else state_c <= end_run_1; + end if; +-------------------------------------- + when norm_event_0 => + trb_go_norm <= '1'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"1"; + count <= count + 1; + if count = 4 then + state_c <= norm_event_1; + else state_c <= norm_event_0; + end if; + + when norm_event_1 => + trb_go_norm <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 9 then + state_c <= tag_low_0; + else state_c <= norm_event_1; + end if; +--------------------------------------- + when calib_event_0 => + trb_go_calib <= '1'; + dtu_bus_t <= '1'; + dtu_bus_ts <= '0'; + dtu_bus_td <= x"9"; + count <= count + 1; + if count = 4 then + state_c <= calib_event_1; + else state_c <= calib_event_0; + end if; + + when calib_event_1 => + trb_go_calib <= '0'; + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 9 then + state_c <= tag_low_0; + else state_c <= calib_event_1; + end if; +--------------------------------------------------------- + when tag_low_0 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= tag_counter_dtu(3 downto 0); + count <= count + 1; + if count = 14 then + state_c <= tag_low_1; + else state_c <= tag_low_0; + end if; + + when tag_low_1 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 19 then + state_c <= tag_high_0; + else state_c <= tag_low_1; + end if; + + when tag_high_0 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= tag_counter_dtu(7 downto 4); + count <= count + 1; + if count = 24 then + state_c <= tag_high_1; + else state_c <= tag_high_0; + end if; + + when tag_high_1 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 29 then + state_c <= tag_prio_0; + else state_c <= tag_high_1; + end if; + + when tag_prio_0 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '1'; + dtu_bus_td <= "0000"; + count <= count + 1; + if count = 34 then + state_c <= tag_prio_1; + else state_c <= tag_prio_0; + end if; + + when tag_prio_1 => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + count <= count + 1; + if count = 39 then + state_c <= wait_last; + else state_c <= tag_prio_1; + end if; + + when wait_last => + dtu_bus_t <= '0'; + dtu_bus_ts <= '0'; + dtu_bus_td <= "0000"; + count <= count + 1; + if count = 244 then --change this to increase wait time (44 default) + state_c <= wait_for_trb; + else state_c <= wait_last; + end if; + + when wait_for_trb => + if trb_finished = '1' then + state_c <= count_incr; + else state_c <= wait_for_trb; + end if; + + when count_incr => + gts_dtu_r <= '1'; + tag_counter_dtu <= tag_counter_dtu + 1; + state_c <= idle; + + + when others => + state_c <= idle; + + end case; + end if; + end process; + + +end Behavioral; diff --git a/oldfiles/vulom3/clocking.vhd b/oldfiles/vulom3/clocking.vhd new file mode 100644 index 0000000..7c22363 --- /dev/null +++ b/oldfiles/vulom3/clocking.vhd @@ -0,0 +1,168 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 9.1.03i +-- \ \ Application : xaw2vhdl +-- / / Filename : clocking.vhd +-- /___/ /\ Timestamp : 02/25/2008 15:07:58 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-intstyle /home/davide/Fpga_projects/vulom3/clocking.xaw -st clocking.vhd +--Design Name: clocking +--Device: xc4vlx25-10sf363 +-- +-- Module clocking +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity clocking is + port ( CLKIN_IN : in std_logic; + CLKDV_OUT : out std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic; + LOCKED_OUT : out std_logic); +end clocking; + +architecture BEHAVIORAL of clocking is + signal CLKDV_BUF : std_logic; + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + signal GND_BUS_7 : std_logic_vector (6 downto 0); + signal GND_BUS_16 : std_logic_vector (15 downto 0); + component BUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + component IBUFG + port ( I : in std_logic; + O : out std_logic); + end component; + + -- Period Jitter (unit interval) for block DCM_ADV_INST = 0.044 UI + -- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.146 ns + component DCM_ADV + generic( CLK_FEEDBACK : string := "1X"; + CLKDV_DIVIDE : real := 2.0; + CLKFX_DIVIDE : integer := 1; + CLKFX_MULTIPLY : integer := 4; + CLKIN_DIVIDE_BY_2 : boolean := FALSE; + CLKIN_PERIOD : real := 10.0; + CLKOUT_PHASE_SHIFT : string := "NONE"; + DCM_AUTOCALIBRATION : boolean := TRUE; + DCM_PERFORMANCE_MODE : string := "MAX_SPEED"; + DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; + DFS_FREQUENCY_MODE : string := "LOW"; + DLL_FREQUENCY_MODE : string := "LOW"; + DUTY_CYCLE_CORRECTION : boolean := TRUE; + FACTORY_JF : bit_vector := x"F0F0"; + PHASE_SHIFT : integer := 0; + STARTUP_WAIT : boolean := FALSE; + SIM_DEVICE : string := "VIRTEX4"); + port ( CLKIN : in std_logic; + CLKFB : in std_logic; + DADDR : in std_logic_vector (6 downto 0); + DI : in std_logic_vector (15 downto 0); + DWE : in std_logic; + DEN : in std_logic; + DCLK : in std_logic; + RST : in std_logic; + PSEN : in std_logic; + PSINCDEC : in std_logic; + PSCLK : in std_logic; + CLK0 : out std_logic; + CLK90 : out std_logic; + CLK180 : out std_logic; + CLK270 : out std_logic; + CLKDV : out std_logic; + CLK2X : out std_logic; + CLK2X180 : out std_logic; + CLKFX : out std_logic; + CLKFX180 : out std_logic; + DRDY : out std_logic; + DO : out std_logic_vector (15 downto 0); + LOCKED : out std_logic; + PSDONE : out std_logic); + end component; + +begin + GND_BIT <= '0'; + GND_BUS_7(6 downto 0) <= "0000000"; + GND_BUS_16(15 downto 0) <= "0000000000000000"; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKDV_BUFG_INST : BUFG + port map (I=>CLKDV_BUF, + O=>CLKDV_OUT); + + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_ADV_INST : DCM_ADV + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 3, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 10.000, + CLKOUT_PHASE_SHIFT => "NONE", + DCM_AUTOCALIBRATION => TRUE, + DCM_PERFORMANCE_MODE => "MAX_SPEED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "HIGH", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"F0F0", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DADDR(6 downto 0)=>GND_BUS_7(6 downto 0), + DCLK=>GND_BIT, + DEN=>GND_BIT, + DI(15 downto 0)=>GND_BUS_16(15 downto 0), + DWE=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>CLKDV_BUF, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + DO=>open, + DRDY=>open, + LOCKED=>LOCKED_OUT, + PSDONE=>open); + +end BEHAVIORAL; + + diff --git a/oldfiles/vulom3/compile_vulom3.pl b/oldfiles/vulom3/compile_vulom3.pl new file mode 100755 index 0000000..2e70115 --- /dev/null +++ b/oldfiles/vulom3/compile_vulom3.pl @@ -0,0 +1,143 @@ +#!/usr/bin/perl +########################################### +# Script file to run the flow +# +########################################### +# +# Command line for synplify_pro +# + + +use FileHandle; + + +$ENV{LM_LICENSE_FILE}="1709\@hadeb05"; + + + +$PLD_DEVICE="xc4vlx25-10-sf363"; +$TOPNAME="vlogic_1"; + + + +#set -e +#set -o errexit + +system("env| grep LM_"); + +#$c="/opt/Synplicity/fpga_861/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/fpga_8804/bin/synplify_pro -batch $TOPNAME"."_syn.prj"; +#$c="/opt/Synplicity/fpga_89/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +$c="/opt/Synplicity/fpga_901/bin/synplify_pro -disable_rainbow_dongle -batch $TOPNAME"."_syn.prj"; +#$c=("( netcat -w2 -l -u -p 6001 < data_for_synbatch_6001.raw >/dev/null 2>&1)& /opt/Synplicity/fpga_89/bin/synplify_pro -batch $TOPNAME"."_syn.prj"); +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +my $fh = new FileHandle("; +$fh -> close; + +#if ($r) { +#$c="cat $TOPNAME.srr"; +#system($c); +#exit 129; +#} + +foreach (@a) +{ + if(/\@E:/) + { + $c="cat $TOPNAME.srr"; + system($c); + print "bdabdhsadbhjasdhasldhbas"; + exit 129; + } +} +# +# Command line to synthesize +# + +#chdir ".."; +#$c="xst -intstyle xflow -ifn $TOPNAME.xst -ofn $TOPNAME.syr"; +#execute($c); +#chdir "workdir"; + +# +# Command line for ngdbuild +# +#$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf ../$TOPNAME.ngc $TOPNAME.ngd"; +$c="ngdbuild -p $PLD_DEVICE -nt timestamp -intstyle xflow -uc ../$TOPNAME.ucf -sd ../ $TOPNAME.edf $TOPNAME.ngd"; +execute($c); +# +# Command line for fpgafit +# +$c="map -xe n -logic_opt on -retiming on -timing -power off -equivalent_register_removal on -detail -u -p $PLD_DEVICE -cm speed -pr b -k 4 -c 100 -tx off -intstyle xflow -o $TOPNAME"."_map.ncd $TOPNAME.ngd $TOPNAME.pcf"; +execute($c); + +# +# Command line for Place & Route +# + +$c="par -w -intstyle xflow -pl high -rl high -xe n -t 1 $TOPNAME"."_map.ncd $TOPNAME.ncd $TOPNAME.pcf"; +execute($c); + +# +# Command line for genarate programming file (.bit) +# + + +foreach (<$TOPNAME"."_pad.txt>) { + @a=split (/\s*\|\s*/,$_); + if( ($a[2] ne "" && + $a[2] ne "Signal Name") && + $a[13] ne "LOCATED" + ) + { + print "error, pins were assigned automatically:\n$_\n"; + exit; + } +} + +print "_pad.txt tested for automatically assigned pins\n"; + +#$c="bitgen -w -intstyle ise -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No $TOPNAME"; +$c="bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DisableBandgap:No -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No $TOPNAME.ncd"; + +execute($c); +# +# Command line for generate .stapl file +# + +$c="XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch ../impact_batch_vulom3.txt"; + +execute($c); + + +#ssh depc152 'cd ~/files/vhdl/xilinx; . ~/bin/xilinx_setup; XIL_IMPACT_ENV_LPT_COMPATIBILITY_MODE=true impact -batch conf_xilinx_impact.txt ' + +# +#to download file on ETRAX chip +# + +#$c="lftp root:pass@hades18;put RPCBoardContrller;exit"; +#execute($c) + +chdir ".."; + +sub execute { + my ($c, $op) = @_; + #print "option: $op \n"; + + print "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print "$!"; + if($op ne "do_not_exit") { + exit; + } + } + + return $r; + +} diff --git a/oldfiles/vulom3/delay.vhd b/oldfiles/vulom3/delay.vhd new file mode 100644 index 0000000..dda2a8a --- /dev/null +++ b/oldfiles/vulom3/delay.vhd @@ -0,0 +1,60 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 7/3/07 +-- Design Name: vulom3 +-- Module Name: delay - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 16 clock cycle programmable delayer +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity delay is port ( + clk : in std_logic; + to_be_delayed : in std_logic; + delay_value : in std_logic_vector(3 downto 0); + delayed_pulse : out std_logic); +end delay; + +architecture Behavioral of delay is +signal shift : std_logic_vector (15 downto 0) := x"0000"; + +begin + + process (clk) + begin + if rising_edge(clk) then + shift <= shift (14 downto 0) & to_be_delayed; + + case delay_value is + when "0000" => delayed_pulse <= shift(0); + when "0001" => delayed_pulse <= shift(1); + when "0010" => delayed_pulse <= shift(2); + when "0011" => delayed_pulse <= shift(3); + when "0100" => delayed_pulse <= shift(4); + when "0101" => delayed_pulse <= shift(5); + when "0110" => delayed_pulse <= shift(6); + when "0111" => delayed_pulse <= shift(7); + when "1000" => delayed_pulse <= shift(8); + when "1001" => delayed_pulse <= shift(9); + when "1010" => delayed_pulse <= shift(10); + when "1011" => delayed_pulse <= shift(11); + when "1100" => delayed_pulse <= shift(12); + when "1101" => delayed_pulse <= shift(13); + when "1110" => delayed_pulse <= shift(14); + when "1111" => delayed_pulse <= shift(15); + when others => delayed_pulse <= 'X'; + end case; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/downscale.vhd b/oldfiles/vulom3/downscale.vhd new file mode 100644 index 0000000..43aea9e --- /dev/null +++ b/oldfiles/vulom3/downscale.vhd @@ -0,0 +1,74 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 7/3/07 +-- Design Name: vulom3 +-- Module Name: downscale - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 2^16 programmable divider with output shaper +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.vcomponents.all; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity downscale is port ( + disable : in std_logic; + to_be_downscaled : in std_logic; + downscale_value : in std_logic_vector(3 downto 0); + clk : in std_logic; + downscaled : out std_logic); +end downscale; + +architecture Behavioral of downscale is +signal reset, internal, to_be_downscaled_d : std_logic := '0'; +signal accu : std_logic_vector (15 downto 0) := x"0000"; + +begin + + process(clk) + begin + if rising_edge(clk) then + if disable = '0' then + to_be_downscaled_d <= to_be_downscaled; + else to_be_downscaled_d <= '0'; + end if; + + if to_be_downscaled_d = '1' then + accu <= accu + 1; + end if; + + case downscale_value is + when "0000" => reset <= to_be_downscaled_d; --bypass + when "0001" => reset <= accu(0); + when "0010" => reset <= accu(1); + when "0011" => reset <= accu(2); + when "0100" => reset <= accu(3); + when "0101" => reset <= accu(4); + when "0110" => reset <= accu(5); + when "0111" => reset <= accu(6); + when "1000" => reset <= accu(7); + when "1001" => reset <= accu(8); + when "1010" => reset <= accu(9); + when "1011" => reset <= accu(10); + when "1100" => reset <= accu(11); + when "1101" => reset <= accu(12); + when "1110" => reset <= accu(13); + when "1111" => reset <= accu(14); + when others => reset <= 'X'; + end case; + + internal <= reset; + downscaled <= (not internal) and reset; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/eco_delay.vhd b/oldfiles/vulom3/eco_delay.vhd new file mode 100644 index 0000000..94186ff --- /dev/null +++ b/oldfiles/vulom3/eco_delay.vhd @@ -0,0 +1,51 @@ +---------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 17:03:24 03/27/2007 +-- Design Name: vulom3 +-- Module Name: eco_delay - Behavioral +-- Project Name: triggerbox +-- Target Devices: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Fixed delayer with fixed output pulse shaper +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity eco_delay is port ( + clk : in std_logic; + signal_in : in std_logic; + signal_out : out std_logic); +end eco_delay; + +architecture Behavioral of eco_delay is +signal chain : std_logic_vector(31 downto 0); +signal internal : std_logic; +signal signal_out_s : std_logic:='0'; + +begin + + signal_out <= signal_out_s; + + process (clk) + begin + if rising_edge(clk) then + internal <= signal_in; + chain <= (chain (30 downto 0) & (not internal and signal_in)); + + if (chain(22) = '1' and chain(31) ='0') then + signal_out_s <= '1'; + elsif (chain(22) = '0' and chain(31) ='1') then + signal_out_s <= '0'; + end if; + end if; + end process; + +end Behavioral; + diff --git a/oldfiles/vulom3/impact_batch_vulom3.txt b/oldfiles/vulom3/impact_batch_vulom3.txt new file mode 100644 index 0000000..5e3fdc1 --- /dev/null +++ b/oldfiles/vulom3/impact_batch_vulom3.txt @@ -0,0 +1,6 @@ +setMode -bs +setMode -bs +setCable -port stapl -file "../trigger_box1.stapl" +addDevice -p 1 -file "vlogic_1.bit" +Program -p 1 -defaultVersion 0 +quit \ No newline at end of file diff --git a/oldfiles/vulom3/new_downscale_ck.vhd b/oldfiles/vulom3/new_downscale_ck.vhd new file mode 100644 index 0000000..4c518d4 --- /dev/null +++ b/oldfiles/vulom3/new_downscale_ck.vhd @@ -0,0 +1,113 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 7/3/07 +-- Design Name: vulom3 +-- Module Name: new_downscale_ck - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Provides clock downscale, plus calibration and inhibit signals +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity new_downscale_ck is port ( + downscale_value : in std_logic_vector(3 downto 0); + clk : in std_logic; + downscaled : out std_logic; + output_disable : in std_logic; + scaler_reset : out std_logic; + cal_inhibit : out std_logic; + cal_trigger : out std_logic); +end new_downscale_ck; + +architecture Behavioral of new_downscale_ck is +signal accu_1 : std_logic_vector(21 downto 0); +signal accu_3 : std_logic_vector(15 downto 0); +signal count, count_d, clk_10kHz : std_logic; +signal accu_2 : std_logic_vector(15 downto 0); +signal delay_1, delay_2 : std_logic; + + +begin + + process(clk) --pulser + begin + if rising_edge(clk) then + accu_1 <= accu_1 + 1; + + case downscale_value is + when "0000" => count <= accu_1(6); + when "0001" => count <= accu_1(7); + when "0010" => count <= accu_1(8); + when "0011" => count <= accu_1(9); + when "0100" => count <= accu_1(10); + when "0101" => count <= accu_1(11); + when "0110" => count <= accu_1(12); + when "0111" => count <= accu_1(13); + when "1000" => count <= accu_1(14); + when "1001" => count <= accu_1(15); + when "1010" => count <= accu_1(16); + when "1011" => count <= accu_1(17); + when "1100" => count <= accu_1(18); + when "1101" => count <= accu_1(19); + when "1110" => count <= accu_1(20); + when "1111" => count <= accu_1(21); + when others => count <= 'X'; + end case; + + count_d <= count; + downscaled <= (not count_d) and count; + end if; + end process; + + + process(clk) --10 kHz clock generator + begin + if rising_edge(clk) then + if accu_2 = x"3a97" then + accu_2 <= x"0000"; + clk_10kHz <= not clk_10kHz; + else + accu_2 <= accu_2 + 1; + end if; + end if; + end process; + + + process(clk_10kHz) --calibration pulse + begin + if rising_edge(clk_10kHz) then + if accu_3 = x"0000" then + cal_inhibit <= not output_disable; + cal_trigger <= '0'; + scaler_reset <= '1'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"0001" then + cal_inhibit <= not output_disable; + cal_trigger <= not output_disable; + scaler_reset <= '0'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"0002" then + cal_inhibit <= '0'; + cal_trigger <= '0'; + scaler_reset <= '0'; + accu_3 <= accu_3 + 1; + elsif accu_3 = x"270f" then --10e3 + cal_inhibit <= '0'; + cal_trigger <= '0'; + scaler_reset <= '0'; + accu_3 <= x"0000"; + else accu_3 <= accu_3 + 1; + end if; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/one_clock_long.vhd b/oldfiles/vulom3/one_clock_long.vhd new file mode 100644 index 0000000..bf79b3e --- /dev/null +++ b/oldfiles/vulom3/one_clock_long.vhd @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 7/3/07 +-- Design Name: vulom3 +-- Module Name: one_clock_long - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: One clock cycle pulse shaper +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.vcomponents.all; + +entity one_clock_long is port ( + clk : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); +end one_clock_long; + +architecture Behavioral of one_clock_long is +signal internal, signal_in_s : std_logic; + +begin + + process (clk) + begin + if rising_edge(clk) then + signal_in_s <= signal_in; + + if en_clk = '0' then + pulse <= '0'; + else + internal <= signal_in_s; + pulse <= (not internal) and signal_in_s; + end if; + end if; + end process; + +end Behavioral; + diff --git a/oldfiles/vulom3/one_clock_long_test.vhd b/oldfiles/vulom3/one_clock_long_test.vhd new file mode 100644 index 0000000..2c7ed35 --- /dev/null +++ b/oldfiles/vulom3/one_clock_long_test.vhd @@ -0,0 +1,96 @@ + +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:54:36 03/13/2007 +-- Design Name: one_clock_long +-- Module Name: /home/davide/fuffa/one_clock_long_test.vhd +-- Project Name: fuffa +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: one_clock_long +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.std_logic_unsigned.all; +USE ieee.numeric_std.ALL; + +ENTITY one_clock_long_test_vhd IS +END one_clock_long_test_vhd; + +ARCHITECTURE behavior OF one_clock_long_test_vhd IS + + -- Component Declaration for the Unit Under Test (UUT) + COMPONENT one_clock_long + PORT( + clk : IN std_logic; + en_clk : IN std_logic; + signal_in : IN std_logic; + pulse : OUT std_logic + ); + END COMPONENT; + + --Inputs + SIGNAL clk : std_logic := '0'; + SIGNAL en_clk : std_logic := '0'; + SIGNAL signal_in : std_logic := '0'; + + --Outputs + SIGNAL pulse : std_logic; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: one_clock_long PORT MAP( + clk => clk, + en_clk => en_clk, + signal_in => signal_in, + pulse => pulse + ); + + tb : PROCESS + BEGIN + + clk <= '1'; + wait for 1.42 ns; + clk <= '0'; + wait for 1.42 ns; + + END PROCESS; + + stim : process + begin + en_clk <= '1'; + signal_in <= '0'; + wait for 12.78 ns; + signal_in <= '1'; + wait for 14.2 ns; + signal_in <= '0'; + wait for 14.2 ns; + signal_in <= '1'; + wait for 1.42 ns; + signal_in <= '0'; + wait for 14.2 ns; + signal_in <= '1'; + wait for 14.2 ns; + signal_in <= '0'; + wait; + end process; + +END; \ No newline at end of file diff --git a/oldfiles/vulom3/scaler.vhd b/oldfiles/vulom3/scaler.vhd new file mode 100644 index 0000000..f709a22 --- /dev/null +++ b/oldfiles/vulom3/scaler.vhd @@ -0,0 +1,59 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 8/3/07 +-- Design Name: vulom3 +-- Module Name: scaler - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 20 bit counter with reset +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity scaler is + Port ( clk : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(19 downto 0)); +end scaler; + +architecture Behavioral of scaler is +signal scaled : std_logic_vector(19 downto 0) := x"00000"; + +begin +process(clk) +begin + if rising_edge(clk) then + if scaler_reset = '1' then + scaled <= x"00000"; + elsif (input_pulse = '1' and scaler_reset = '0') then + scaled <= scaled + 1; + end if; + end if; + + +-- if rising_edge(clk) then +-- if (input_pulse = '1' and scaler_reset = '0') then +-- scaled <= scaled + 1; +-- elsif scaler_reset = '1' then +-- scaled <= x"00000"; +-- end if; +-- end if; + +scaler_value <= scaled; + +end process; + + +end Behavioral; diff --git a/oldfiles/vulom3/scaler_s.vhd b/oldfiles/vulom3/scaler_s.vhd new file mode 100644 index 0000000..dfefdad --- /dev/null +++ b/oldfiles/vulom3/scaler_s.vhd @@ -0,0 +1,68 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 8/3/07 +-- Design Name: vulom3 +-- Module Name: scaler_s - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 32 bit counter with reset +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--library UNISIM; +--use UNISIM.VComponents.all; + +entity scaler_s is port ( + clk_300MHz : in std_logic; + clk_100MHz : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(31 downto 0)); +end scaler_s; + +architecture Behavioral of scaler_s is +signal scaled : std_logic_vector(31 downto 0) := x"00000000"; +signal r, q : std_logic; +signal input_pulse_d, shaped_input, scaler_reset_d, shaped_reset : std_logic; + +begin + + process(clk_300MHz) + begin + if rising_edge(clk_300MHz) then + input_pulse_d <= input_pulse; + shaped_input <= input_pulse and not input_pulse_d; -- 1 ck shaper + + if r = '1' then -- flip-flop + q <= '0'; + elsif shaped_input = '1' then + q <= '1'; + end if; + end if; + end process; + + process(clk_100MHz) + begin + if rising_edge(clk_100MHz) then + scaler_reset_d <= scaler_reset; -- 1 ck shaper + shaped_reset <= scaler_reset and not scaler_reset_d; + + if shaped_reset = '1' then + scaled <= x"00000000"; + scaler_value <= scaled; + elsif r = '1' then + r <= '0'; + elsif q = '1' then + scaled <= scaled + 1; + r <= '1'; + end if; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/set_width.vhd b/oldfiles/vulom3/set_width.vhd new file mode 100644 index 0000000..070698e --- /dev/null +++ b/oldfiles/vulom3/set_width.vhd @@ -0,0 +1,69 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 8/3/07 +-- Design Name: vulom3 +-- Module Name: set_width - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 16 clock cycle programmable pulse shaper +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.vcomponents.all; + +entity set_width is port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); +end set_width; + +architecture Behavioral of set_width is +signal reset, to_be_set_delayed, q : std_logic; +signal shift :std_logic_vector (15 downto 0); + +begin + + process (clk) + begin + + if rising_edge(clk) then + shift <= shift (14 downto 0) & to_be_set; + to_be_set_delayed <= to_be_set; + + case width_value is + when "0000" => reset <= shift(0); + when "0001" => reset <= shift(1); + when "0010" => reset <= shift(2); + when "0011" => reset <= shift(3); + when "0100" => reset <= shift(4); + when "0101" => reset <= shift(5); + when "0110" => reset <= shift(6); + when "0111" => reset <= shift(7); + when "1000" => reset <= shift(8); + when "1001" => reset <= shift(9); + when "1010" => reset <= shift(10); + when "1011" => reset <= shift(11); + when "1100" => reset <= shift(12); + when "1101" => reset <= shift(13); + when "1110" => reset <= shift(14); + when "1111" => reset <= shift(15); + when others => reset <= 'X'; + end case; + + if (to_be_set_delayed = '0' and reset ='1') then + width_adjusted_pulse <= '0'; + elsif (to_be_set_delayed = '1' and reset ='0') then + width_adjusted_pulse <= '1'; + end if; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/set_width_special.vhd b/oldfiles/vulom3/set_width_special.vhd new file mode 100644 index 0000000..08ef7fa --- /dev/null +++ b/oldfiles/vulom3/set_width_special.vhd @@ -0,0 +1,79 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 8/3/07 +-- Design Name: vulom3 +-- Module Name: set_width_special - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: 16 clock cycle programmable pulse shaper specific for output +-- (it can handle pulses wider than 1 ck cycle) +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.vcomponents.all; + +entity set_width_special is port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); +end set_width_special; + +architecture Behavioral of set_width_special is +signal reset, to_be_set_delayed, q : std_logic; +signal shift : std_logic_vector(15 downto 0); + +begin + + process (clk) + begin + if rising_edge(clk) then + if reset = '1' then + q <= '0'; + elsif to_be_set = '1' then + q <= '1'; + end if; + + if q = '0' then + shift <= shift (14 downto 0) & to_be_set; + to_be_set_delayed <= to_be_set; + else + shift <= shift (14 downto 0) & '0'; + to_be_set_delayed <= '0'; + end if; + + case width_value is + when "0000" => reset <= shift(0); + when "0001" => reset <= shift(1); + when "0010" => reset <= shift(2); + when "0011" => reset <= shift(3); + when "0100" => reset <= shift(4); + when "0101" => reset <= shift(5); + when "0110" => reset <= shift(6); + when "0111" => reset <= shift(7); + when "1000" => reset <= shift(8); + when "1001" => reset <= shift(9); + when "1010" => reset <= shift(10); + when "1011" => reset <= shift(11); + when "1100" => reset <= shift(12); + when "1101" => reset <= shift(13); + when "1110" => reset <= shift(14); + when "1111" => reset <= shift(15); + when others => reset <= 'X'; + end case; + + if (to_be_set_delayed = '0' and reset ='1') then + width_adjusted_pulse <= '0'; + elsif (to_be_set_delayed = '1' and reset ='0') then + width_adjusted_pulse <= '1'; + end if; + end if; + end process; + +end Behavioral; diff --git a/oldfiles/vulom3/trig_box1.vhd b/oldfiles/vulom3/trig_box1.vhd new file mode 100644 index 0000000..0df2182 --- /dev/null +++ b/oldfiles/vulom3/trig_box1.vhd @@ -0,0 +1,895 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 9/3/07 +-- Design Name: vulom3 +-- Module Name: trig_box1 - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Triggerbox +-- NOTE (1): To enable TOF/MDC part comment lines (a) and (b) and uncomment (c) +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity trig_box1 is + port (clk_50MHz : in std_logic; + clk_300MHz : in std_logic; + clk_100MHz : in std_logic; + ECL : in std_logic_vector(16 downto 1); + ECO : out std_logic_vector(16 downto 1); + IOO : in std_logic_vector(16 downto 1); + TIN : out std_logic_vector(16 downto 1); + LEMIN : in std_logic_vector(2 downto 1); + LEMOU : out std_logic_vector(2 downto 1); + INPUT_ENABLE : in std_logic_vector(7 downto 1); + DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); + BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); --(4) enables branch, (3 downto 0) is the width value + WIDTH_OUTPUT : in std_logic_vector(3 downto 0); + MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); + MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); + OR_ON_OFF : in std_logic_vector(7 downto 0); + SCALER_PTI1 : out std_logic_vector(31 downto 0); + SCALER_PTI2 : out std_logic_vector(31 downto 0); + SCALER_PTI3 : out std_logic_vector(31 downto 0); + SCALER_PTI4 : out std_logic_vector(31 downto 0); + SCALER_PTI5 : out std_logic_vector(31 downto 0); + SCALER_TS : out std_logic_vector(31 downto 0); + SCALER_VS : out std_logic_vector(31 downto 0); + SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); -- x"yz" y= mdc channel select, z= tof channel select + SCALER_MDC : out std_logic_vector(31 downto 0); + SCALER_TOF : out std_logic_vector(31 downto 0); + SCALER_RESET : in std_logic_vector(7 downto 0); + PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); + DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); + SCALER_DEAD : out std_logic_vector(31 downto 0); + TS_GATING_DISABLE : in std_logic_vector(7 downto 1); + SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_MUX1 : out std_logic_vector(31 downto 0); + SCALER_MUX2 : out std_logic_vector(31 downto 0); + CAL_TRIGGER_DISABLE : in std_logic; + COM_RUN : in std_logic; + DTU_ERROR : inout std_logic; + hpv : inout std_logic_vector(15 downto 0); + hpw : inout std_logic_vector(15 downto 0) + ); +end trig_box1; +architecture RTL of trig_box1 is + component one_clock_long port ( + clk : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + component delay port ( + clk : in std_logic; + to_be_delayed : in std_logic; + delay_value : in std_logic_vector(3 downto 0); + delayed_pulse : out std_logic); + end component; + component downscale port ( + clk : in std_logic; + disable : in std_logic; + to_be_downscaled : in std_logic; + downscale_value : in std_logic_vector(3 downto 0); + downscaled : out std_logic); + end component; + component set_width port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); + end component; + component set_width_special port ( + clk : in std_logic; + to_be_set : in std_logic; + width_value : in std_logic_vector(3 downto 0); + width_adjusted_pulse : out std_logic); + end component; + component scaler port ( + clk : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(19 downto 0)); + end component; + component scaler_s port ( + clk_300mhz : in std_logic; + clk_100mhz : in std_logic; + input_pulse : in std_logic; + scaler_reset : in std_logic; + scaler_value : out std_logic_vector(31 downto 0)); + end component; + component eco_delay port ( + clk : in std_logic; + signal_in : in std_logic; + signal_out : out std_logic); + end component; + component new_downscale_ck + port( + downscale_value : in std_logic_vector(3 downto 0); + clk : in std_logic; + downscaled : out std_logic; + output_disable : in std_logic; + scaler_reset : out std_logic; + cal_inhibit : out std_logic; + cal_trigger : out std_logic + ); + end component; + component beam_ramp + port( + clk_300mhz : in std_logic; + clk_50mhz : in std_logic; + input : in std_logic; + delay_value : in std_logic_vector(7 downto 0); + width_value_inhibit : in std_logic_vector(7 downto 0); + width_value_external : in std_logic_vector(7 downto 0); + output_inhibit : out std_logic; + output_external : out std_logic + ); + end component; + component bus_data_com5 + port( + clk_300mhz : in std_logic; + clk_100mhz : in std_logic; + gts_pulse : in std_logic; + cal_trigger : in std_logic; + bus_busy : in std_logic; --not used + bus_ack : in std_logic; + bus_retx : in std_logic; + latch : in std_logic_vector(6 downto 0); + latch_dsc : in std_logic_vector(6 downto 0); + scaler_pti1 : in std_logic_vector(31 downto 0); + scaler_pti2 : in std_logic_vector(31 downto 0); + scaler_pti3 : in std_logic_vector(31 downto 0); + scaler_pti4 : in std_logic_vector(31 downto 0); + scaler_pti5 : in std_logic_vector(31 downto 0); + scaler_ts : in std_logic_vector(31 downto 0); + scaler_vs : in std_logic_vector(31 downto 0); + scaler_dead : in std_logic_vector(31 downto 0); + bus_inhibit : out std_logic; + dtu_inhibit : out std_logic; + ecl_bus_data : out std_logic_vector(1 downto 0); + ecl_bus_clk : out std_logic; + com_run : in std_logic; + dtu_bus_t : out std_logic; + dtu_bus_ts : out std_logic; + dtu_bus_td : out std_logic_vector (3 downto 0); + out_inhibit : in std_logic + ); + end component; + signal pti1_one_clock, pti1_delayed, pti1_ready, pti1_downscaled, pti1_self_coin : std_logic; + signal pti2_one_clock, pti2_delayed, pti2_ready, pti2_downscaled, pti2_self_coin : std_logic; + signal pti3_one_clock, pti3_delayed, pti3_ready, pti3_downscaled, pti3_self_coin : std_logic; + signal pti4_one_clock, pti4_delayed, pti4_ready, pti4_downscaled, pti4_self_coin : std_logic; + signal pti5_one_clock, pti5_delayed, pti5_ready, pti5_downscaled, pti5_self_coin : std_logic; + signal ts_one_clock, ts_delayed, ts_ready, dead, ts_self_coin : std_logic; + signal vs_one_clocks, vs_delayed, vs_ready, vs_width_set, vs_self_coin : std_logic; + signal clock_downscaled, clock_ready : std_logic; + signal cal_inhibit, cal_trigger, out_inhibit, beam_inhibit, bus_inhibit : std_logic; + signal global_timing_signal_out, or_out : std_logic; + signal pti1_and_gts, pti2_and_gts, pti3_and_gts, pti4_and_gts, pti5_and_gts : std_logic; + signal lemin_s, lemin_s1, mux_out : std_logic_vector(1 downto 0); + signal mdc_tof_or, mdc_tof_or_width_set, tof_or, tof_or_delayed, tof_mult_2, tof_mult_2_one, mdc_tof_trigger, mdc_tof_trigger_width_set : std_logic; + signal eco_s, eco_out : std_logic_vector(16 downto 1); + signal tof_one_clock, tof_del, tof_s, tof_s1, mdc_s, mdc_s1 : std_logic_vector(5 downto 0); + signal tof_mux, mdc_mux, pti5_mux, ts_mux, mdc_one_clock : std_logic; + signal scaler_pti1_count, scaler_pti2_count, scaler_pti3_count, scaler_pti4_count, scaler_pti5_count, scaler_ts_count, scaler_vs_count, scaler_dead_count : std_logic_vector(31 downto 0); +signal self_coin_delay_1, self_coin_delay_2, self_coin_delay_3, self_coin_delay_4, self_coin_delay_5 : std_logic_vector(3 downto 0); + signal scaler_reset_internal : std_logic; + signal dtu_bus_t, dtu_bus_ts, dtu_bus_tb_s, dtu_inhibit : std_logic; + signal dtu_bus_td : std_logic_vector(3 downto 0); + signal gts_to_databus, cal_to_databus : std_logic; +begin + +-------------------------------------------------------------one clock long + one1 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(1), + signal_in => ioo(1), + pulse => pti1_one_clock); + one2 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(2), + signal_in => ioo(2), + pulse => pti2_one_clock); + one3 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(3), + signal_in => ioo(3), + pulse => pti3_one_clock); + one4 : one_clock_long port map ( --directly connected to the or of tof, so ecl input n°4 is unused + clk => clk_300mhz, + en_clk => input_enable(4), + signal_in => tof_or, + pulse => pti4_one_clock); + one5 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(5), + signal_in => ioo(5), + pulse => pti5_one_clock); + one6 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(6), + signal_in => ioo(6), + pulse => ts_one_clock); + one7 : one_clock_long port map ( + clk => clk_300mhz, + en_clk => input_enable(7), + signal_in => ioo(7), + pulse => vs_one_clocks); + one_mdc : one_clock_long port map ( --used only for scaler + clk => clk_300mhz, + en_clk => '1', + signal_in => mdc_mux, + pulse => mdc_one_clock); + tof_generate_oneclock : for i in 9 to 14 generate + one_tof : one_clock_long port map ( + clk => clk_300mhz, + en_clk => '1', --tof always enabled + signal_in => ecl(i), + pulse => tof_one_clock(i-9)); + end generate; +--------------------------------------------- + multiplicity : one_clock_long port map ( + clk => clk_300mhz, + en_clk => '1', + signal_in => tof_mult_2, + pulse => tof_mult_2_one); +--------------------------------------------- + one_ck : one_clock_long port map ( + clk => clk_300mhz, + en_clk => '1', + signal_in => clock_downscaled, + pulse => clock_ready); + +-------------------------------------------------------------------------delay + del1 : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti1_one_clock, + delay_value => delay_register_1(3 downto 0), + delayed_pulse => pti1_delayed); + + del2 : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti2_one_clock, + delay_value => delay_register_2(3 downto 0), + delayed_pulse => pti2_delayed); + + del3 : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti3_one_clock, + delay_value => delay_register_3(3 downto 0), + delayed_pulse => pti3_delayed); + + del4 : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti4_one_clock, + delay_value => delay_register_4(3 downto 0), + delayed_pulse => pti4_delayed); + + del5 : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti5_mux, + delay_value => delay_register_5(3 downto 0), + delayed_pulse => pti5_delayed); + + del6 : delay port map ( + clk => clk_300mhz, + to_be_delayed => ts_mux, + delay_value => delay_register_ts(3 downto 0), + delayed_pulse => ts_delayed); + + del7 : delay port map ( + clk => clk_300mhz, + to_be_delayed => vs_one_clocks, + delay_value => delay_register_vs(3 downto 0), + delayed_pulse => vs_delayed); + + self_coin_delay_1 <= '0' & width_register_1(3 downto 1); --automatic delay = width / 2 + self_coin_delay_2 <= '0' & width_register_2(3 downto 1); + self_coin_delay_3 <= '0' & width_register_3(3 downto 1); + self_coin_delay_4 <= '0' & width_register_4(3 downto 1); + self_coin_delay_5 <= '0' & width_register_5(3 downto 1); + + del1_self : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti1_downscaled, + delay_value => self_coin_delay_1, + delayed_pulse => pti1_self_coin); + + del2_self : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti2_downscaled, + delay_value => self_coin_delay_2, + delayed_pulse => pti2_self_coin); + + del3_self : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti3_downscaled, + delay_value => self_coin_delay_3, + delayed_pulse => pti3_self_coin); + + del4_self : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti4_downscaled, + delay_value => self_coin_delay_4, + delayed_pulse => pti4_self_coin); + + del5_self : delay port map ( + clk => clk_300mhz, + to_be_delayed => pti5_downscaled, + delay_value => self_coin_delay_5, + delayed_pulse => pti5_self_coin); + + tof_generate_delay : for t in 0 to 5 generate + del_tof : delay port map ( + clk => clk_300mhz, + to_be_delayed => tof_one_clock(t), + delay_value => delay_register_4(3 downto 0), + delayed_pulse => tof_del(t)); + end generate; + +-------------------------------------------------------------------------scaler + scal1 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, --pti1÷5 before inhibit + input_pulse => pti1_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti1_count); + + scal2 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => pti2_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti2_count); + + scal3 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => pti3_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti3_count); + + scal4 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => pti4_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti4_count); + + scal5 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => pti5_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti5_count); + + scal1a : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, --pti1÷5 after inhibit + input_pulse => eco_s(9), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti1_accepted); + + scal2a : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => eco_s(10), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti2_accepted); + + scal3a : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => eco_s(11), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti3_accepted); + + scal4a : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => eco_s(12), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti4_accepted); + + scal5a : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => eco_s(13), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_pti5_accepted); + + scalts : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, --ts, vs and dead + input_pulse => ts_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_ts_count); + + scalvs : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => vs_delayed, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_vs_count); + + scaldead : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => dead, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_dead_count); + + scalmdc : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, --mdc and tof + input_pulse => mdc_one_clock, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_mdc); + + scaltof : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => tof_mux, + scaler_reset => scaler_reset_internal, + scaler_value => scaler_tof); + + scalmux1 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => mux_out(0), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_mux1); + + scalmux2 : scaler_s port map ( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + input_pulse => mux_out(1), + scaler_reset => scaler_reset_internal, + scaler_value => scaler_mux2); + +---------------------------------------------------------------------------downscale + dwsc1 : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => pti1_delayed, + downscale_value => downscale_register_1(3 downto 0), + downscaled => pti1_downscaled); + + dwsc2 : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => pti2_delayed, + downscale_value => downscale_register_2(3 downto 0), + downscaled => pti2_downscaled); + + dwsc3 : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => pti3_delayed, + downscale_value => downscale_register_3(3 downto 0), + downscaled => pti3_downscaled); + + dwsc4 : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => pti4_delayed, + downscale_value => downscale_register_4(3 downto 0), + downscaled => pti4_downscaled); + + dwsc5 : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => pti5_delayed, + downscale_value => downscale_register_5(3 downto 0), + downscaled => pti5_downscaled); + + dwscts : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => ts_delayed, + downscale_value => downscale_register_ts(3 downto 0), + downscaled => ts_ready); + + dwscvs : downscale port map ( + clk => clk_300mhz, + disable => out_inhibit, + to_be_downscaled => vs_delayed, + downscale_value => downscale_register_vs(3 downto 0), + downscaled => vs_ready); + +-------------------------------------------------------------------------------width + setw1 : set_width port map ( + clk => clk_300mhz, + to_be_set => pti1_downscaled, + width_value => width_register_1(3 downto 0), + width_adjusted_pulse => pti1_ready); + + setw2 : set_width port map ( + clk => clk_300mhz, + to_be_set => pti2_downscaled, + width_value => width_register_2(3 downto 0), + width_adjusted_pulse => pti2_ready); + + setw3 : set_width port map ( + clk => clk_300mhz, + to_be_set => pti3_downscaled, + width_value => width_register_3(3 downto 0), + width_adjusted_pulse => pti3_ready); + + setw4 : set_width port map ( + clk => clk_300mhz, + to_be_set => pti4_downscaled, + width_value => width_register_4(3 downto 0), + width_adjusted_pulse => pti4_ready); + + setw5 : set_width port map ( + clk => clk_300mhz, + to_be_set => pti5_downscaled, + width_value => width_register_5(3 downto 0), + width_adjusted_pulse => pti5_ready); + + setw7 : set_width port map ( + clk => clk_300mhz, + to_be_set => vs_delayed, + width_value => width_register_vs(3 downto 0), + width_adjusted_pulse => vs_width_set); + +--*/*/*///*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ --read note 1) + mdc_tof_trigger_width_set <= '1'; --(a) +--*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/* + + setw_mdc_tof_trigger : set_width port map ( + clk => clk_300mhz, + to_be_set => mdc_tof_or, + width_value => branch_en_with_mdc_tof_width(3 downto 0), +-- width_adjusted_pulse => mdc_tof_trigger_width_set); --(c) + width_adjusted_pulse => open); --(b) + + setwout : set_width_special port map ( + clk => clk_300mhz, + to_be_set => global_timing_signal_out, + width_value => x"6", -- fixed to 20 ns + width_adjusted_pulse => lemou(1)); + +------------------------------------------------------------------------------------------output + delaygen1 : for i in 1 to 7 generate + delay_out : eco_delay port map ( + clk => clk_300mhz, + signal_in => eco_s(i), + signal_out => eco_out(i)); + end generate; + + eco(7 downto 1) <= eco_out(7 downto 1); + + setmux1 : set_width port map ( + clk => clk_300mhz, + to_be_set => mux_out(0), + width_value => "0010", + width_adjusted_pulse => eco(8)); + + delaygen2 : for i in 9 to 15 generate + delay_out : eco_delay port map ( + clk => clk_300mhz, + signal_in => eco_s(i), + signal_out => eco_out(i)); + end generate; + + eco(15 downto 9) <= eco_out(15 downto 9); + + setmux2 : set_width port map ( + clk => clk_300mhz, + to_be_set => mux_out(1), + width_value => "0010", + width_adjusted_pulse => eco(16)); + + inst_new_downscale_ck : new_downscale_ck port map( + downscale_value => downscale_register_clock(3 downto 0), + clk => clk_300mhz, + output_disable => cal_trigger_disable, + scaler_reset => scaler_reset_internal, + downscaled => clock_downscaled, + cal_inhibit => cal_inhibit, + cal_trigger => cal_trigger); + + + lemou(2) <= '0'; --now calib pulse is coming out from lemo n°1, this output is unused + + inst_beam_ramp : beam_ramp port map( + clk_300mhz => clk_300mhz, + clk_50mhz => clk_50mhz, + input => lemin_s(1), + output_inhibit => beam_inhibit, + output_external => tin(12), + delay_value => delay_register_beam, + width_value_inhibit => width_inhibit_register_beam, + width_value_external => width_external_register_beam); + +--------------bus communication + + inst_bus_data_com5 : bus_data_com5 port map( + clk_300mhz => clk_300mhz, + clk_100mhz => clk_100mhz, + gts_pulse => gts_to_databus, + cal_trigger => cal_trigger, + bus_busy => ioo(16), --not used + bus_ack => ioo(15), + bus_retx => ioo(14), + latch => eco_out(7 downto 1), + latch_dsc => eco_out(15 downto 9), + scaler_pti1 => scaler_pti1_count, + scaler_pti2 => scaler_pti2_count, + scaler_pti3 => scaler_pti3_count, + scaler_pti4 => scaler_pti4_count, + scaler_pti5 => scaler_pti5_count, + scaler_ts => scaler_ts_count, + scaler_vs => scaler_vs_count, + scaler_dead => scaler_dead_count, + bus_inhibit => bus_inhibit, + dtu_inhibit => dtu_inhibit, + ecl_bus_data => tin(11 downto 10), + ecl_bus_clk => tin(9), + com_run => com_run, + dtu_bus_t => dtu_bus_t, + dtu_bus_ts => dtu_bus_ts, + dtu_bus_td => dtu_bus_td, + out_inhibit => out_inhibit + ); + + --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ + hpv(14) <= not dtu_bus_t; --this is a "firmware patch": the vme connector + hpw(14) <= not dtu_bus_ts; --for dtu is reversed (mistake in pcb layout) so + hpw(10) <= not dtu_bus_td(3); --all the i/os must be inverted + hpv(10) <= not dtu_bus_td(2); + hpw(12) <= not dtu_bus_td(1); + hpv(12) <= not dtu_bus_td(0); + hpw(8) <= 'Z'; + ---------------------- + hpv(15) <= dtu_bus_ts; --with this connections all the dtu signals are + hpv(11) <= dtu_bus_td(3); --on one debug socket (hplv or hplw) that can conveniently + hpv(13) <= dtu_bus_td(1); --plugged to a logic analyzer. be aware though, some signals + hpv(9) <= '0'; --are inverted + hpv(7 downto 0) <= x"00"; --unused + + hpw(15) <= dtu_bus_t; + hpw(11) <= dtu_bus_td(2); + hpw(13) <= dtu_bus_td(0); + hpw(9) <= '0'; + hpw(7 downto 0) <= x"00"; --unused + --/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ + + scaler_pti1 <= scaler_pti1_count; + scaler_pti2 <= scaler_pti2_count; + scaler_pti3 <= scaler_pti3_count; + scaler_pti4 <= scaler_pti4_count; + scaler_pti5 <= scaler_pti5_count; + scaler_ts <= scaler_ts_count; + scaler_vs <= scaler_vs_count; + scaler_dead <= scaler_dead_count; + + tin(16 downto 13) <= "0000"; + +--------------pti5 & ts mux + + mdc_tof_mux : process(clk_300mhz) + begin + if rising_edge(clk_300mhz) then + +-- case tof_one_clock is --multiplicity 2 detector + case ecl(14 downto 9) is --multiplicity 2 detector + when "000011" => tof_mult_2 <= '1'; + when "000101" => tof_mult_2 <= '1'; + when "001001" => tof_mult_2 <= '1'; + when "010001" => tof_mult_2 <= '1'; + when "100001" => tof_mult_2 <= '1'; + when "000110" => tof_mult_2 <= '1'; + when "001010" => tof_mult_2 <= '1'; + when "010010" => tof_mult_2 <= '1'; + when "100010" => tof_mult_2 <= '1'; + when "001100" => tof_mult_2 <= '1'; + when "010100" => tof_mult_2 <= '1'; + when "100100" => tof_mult_2 <= '1'; + when "011000" => tof_mult_2 <= '1'; + when "101000" => tof_mult_2 <= '1'; + when "110000" => tof_mult_2 <= '1'; + when others => tof_mult_2 <= '0'; + end case; + + case pti5_ts_alternative(4) is + when '0' => pti5_mux <= pti5_one_clock; + when '1' => pti5_mux <= tof_mult_2_one; + when others => pti5_mux <= 'X'; + end case; + + case pti5_ts_alternative(0) is + when '0' => ts_mux <= ts_one_clock; + when '1' => ts_mux <= tof_or; + when others => ts_mux <= 'X'; + end case; + end if; + end process mdc_tof_mux; + +--------------mdc & tof scaler mux + + pti5_ts_mux : process(clk_300mhz) + begin + if rising_edge(clk_300mhz) then + case scaler_mdc_tof_select(7 downto 4) is + when x"0" => mdc_mux <= mdc_s1(0); + when x"1" => mdc_mux <= mdc_s1(1); + when x"2" => mdc_mux <= mdc_s1(2); + when x"3" => mdc_mux <= mdc_s1(3); + when x"4" => mdc_mux <= mdc_s1(4); + when x"5" => mdc_mux <= mdc_s1(5); + when others => mdc_mux <= '0'; + end case; + + case scaler_mdc_tof_select(3 downto 0) is + when x"0" => tof_mux <= tof_one_clock(0); + when x"1" => tof_mux <= tof_one_clock(1); + when x"2" => tof_mux <= tof_one_clock(2); + when x"3" => tof_mux <= tof_one_clock(3); + when x"4" => tof_mux <= tof_one_clock(4); + when x"5" => tof_mux <= tof_one_clock(5); + when others => tof_mux <= '0'; + end case; + end if; + end process pti5_ts_mux; + +-------------- tof & mdc logic + + tof_mdc_logic : process(clk_300mhz) + begin + if rising_edge(clk_300mhz) then + + mdc_s <= ecl(6 downto 1); + tof_s <= ecl(14 downto 9); + mdc_s1 <= mdc_s; + tof_s1 <= tof_s; + + mdc_tof_or <= (((tof_del(0) and not mdc_s1(0)) or (tof_del(1) and not mdc_s1(1)) or + (tof_del(2) and not mdc_s1(2)) or (tof_del(3) and not mdc_s1(3)) or + (tof_del(4) and not mdc_s1(4)) or (tof_del(5) and not mdc_s1(5))) + and branch_en_with_mdc_tof_width(4)); + tof_or <= (ecl(9) or ecl(10) or ecl(11) or ecl(12) or ecl(13) or ecl(14)); + end if; + end process tof_mdc_logic; +-------------- final and-or logic function + logic : process(clk_300mhz) + begin + if rising_edge(clk_300mhz) then + + -------------------------------------- gate select single + + pti1_and_gts <= ((pti1_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(1)) + or (pti1_self_coin and ts_gating_disable(1))); + pti2_and_gts <= ((pti2_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(2)) + or (pti2_self_coin and ts_gating_disable(2))); + pti3_and_gts <= ((pti3_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(3)) + or (pti3_self_coin and ts_gating_disable(3))); + pti4_and_gts <= ((pti4_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(4)) + or (pti4_self_coin and ts_gating_disable(4))); + pti5_and_gts <= ((pti5_ready and (ts_delayed and not vs_width_set) and mdc_tof_trigger_width_set and not ts_gating_disable(5)) + or (pti5_self_coin and ts_gating_disable(5))); + or_out <= (pti1_and_gts and or_on_off(0)) or + (pti2_and_gts and or_on_off(1)) or + (pti3_and_gts and or_on_off(2)) or + (pti4_and_gts and or_on_off(3)) or + (pti5_and_gts and or_on_off(4)) or + (ts_ready and or_on_off(5)) or + (vs_ready and or_on_off(6)) or + (clock_ready and or_on_off(7)); + lemin_s <= lemin; + lemin_s1 <= lemin_s; + dtu_bus_tb_s <= not hpv(8); --dtu trigger busy + dead <= ts_delayed and (not out_inhibit); + out_inhibit <= lemin_s1(0) or beam_inhibit or bus_inhibit or dtu_inhibit or dtu_bus_tb_s; + global_timing_signal_out <= (cal_trigger and not out_inhibit) or (or_out and not out_inhibit and not cal_inhibit); + gts_to_databus <= or_out and not out_inhibit and not cal_inhibit; + end if; + end process logic; +---------------- outputs + + assign : process(clk_300mhz) + begin + if rising_edge(clk_300mhz) then + eco_s(1) <= pti1_delayed; -- latches before downscale + eco_s(2) <= pti2_delayed; + eco_s(3) <= pti3_delayed; + eco_s(4) <= pti4_delayed; + eco_s(5) <= pti5_delayed; + eco_s(6) <= ts_delayed; + eco_s(7) <= vs_delayed; +-- eco(8) is mux 0 + eco_s(9) <= (or_on_off(0) and ((pti1_downscaled and ts_gating_disable(1)) + or (pti1_and_gts and not ts_gating_disable(1)))); + eco_s(10) <= (or_on_off(1) and ((pti2_downscaled and ts_gating_disable(2)) + or (pti2_and_gts and not ts_gating_disable(2)))); + eco_s(11) <= (or_on_off(2) and ((pti3_downscaled and ts_gating_disable(3)) + or (pti3_and_gts and not ts_gating_disable(3)))); + eco_s(12) <= (or_on_off(3) and ((pti4_downscaled and ts_gating_disable(4)) + or (pti4_and_gts and not ts_gating_disable(4)))); + eco_s(13) <= (or_on_off(4) and ((pti5_downscaled and ts_gating_disable(5)) + or (pti5_and_gts and not ts_gating_disable(5)))); + eco_s(14) <= ts_ready and or_on_off(5); + eco_s(15) <= vs_ready and or_on_off(6); +-- eco(16) is mux 1 + +----------------- multiplexers + case mux_selector_1 is --0x5c + when "0000" => mux_out(0) <= pti1_delayed; --0 + when "0001" => mux_out(0) <= pti2_delayed; + when "0010" => mux_out(0) <= pti3_delayed; --2 + when "0011" => mux_out(0) <= pti4_delayed; + when "0100" => mux_out(0) <= pti5_delayed; --4 + when "0101" => mux_out(0) <= ts_delayed; + when "0110" => mux_out(0) <= vs_delayed; --6 + when "0111" => mux_out(0) <= pti1_and_gts; + when "1000" => mux_out(0) <= pti2_and_gts; --8 + when "1001" => mux_out(0) <= pti3_and_gts; + when "1010" => mux_out(0) <= pti4_and_gts; --a + when "1011" => mux_out(0) <= pti5_and_gts; + when "1100" => mux_out(0) <= ts_ready; --c + when "1101" => mux_out(0) <= vs_ready; + when "1110" => mux_out(0) <= or_out; --e + when "1111" => mux_out(0) <= global_timing_signal_out; + when others => mux_out(0) <= 'X'; + end case; + case mux_selector_2 is --0x60 + when "0000" => mux_out(1) <= pti1_delayed; --0 + when "0001" => mux_out(1) <= pti2_delayed; + when "0010" => mux_out(1) <= pti3_delayed; --2 + when "0011" => mux_out(1) <= pti4_delayed; + when "0100" => mux_out(1) <= pti5_delayed; --4 + when "0101" => mux_out(1) <= ts_delayed; + when "0110" => mux_out(1) <= vs_delayed; --6 + when "0111" => mux_out(1) <=tof_mux; --pti1_ready; + when "1000" => mux_out(1) <='0'; --pti2_ready; --8 + when "1001" => mux_out(1) <='0'; --pti3_ready; + when "1010" => mux_out(1) <='0'; --pti4_ready; --a + when "1011" => mux_out(1) <=mdc_tof_trigger_width_set;--pti5_ready; + when "1100" => mux_out(1) <= ts_ready; --c + when "1101" => mux_out(1) <= vs_ready; + when "1110" => mux_out(1) <= clock_ready; --e + when "1111" => mux_out(1) <=mdc_mux; --vs_width_set; + when others => mux_out(1) <= 'X'; + end case; + end if; + end process assign; +end rtl; diff --git a/oldfiles/vulom3/trigger_box1.stapl b/oldfiles/vulom3/trigger_box1.stapl new file mode 100644 index 0000000..0bf6624 --- /dev/null +++ b/oldfiles/vulom3/trigger_box1.stapl @@ -0,0 +1,3106 @@ +NOTE "CREATOR" "Xilinx iMPACT Software"; +NOTE "DATE" "2008/04/28"; +NOTE "STAPL_VERSION" "JESD71"; +NOTE "ALG_VERSION" "1"; +NOTE "DEVICE" "UNSPECIFIED"; +NOTE "CHECKSUM" "UNSPECIFIED"; +NOTE "IDCODE" "UNSPECIFIED"; +NOTE "USERCODE" "UNSPECIFIED"; +NOTE "TARGET" "UNSPECIFIED"; +NOTE "STACK_DEPTH" "4"; +NOTE "MAX_FREQ" "1000000"; +ACTION RUN_XILINX_PROC "Run Xilinx Procedure" = XILINX_PROC; +DATA MAINDATA; +INTEGER I = 0; +INTEGER D = 0; +ENDDATA; +PROCEDURE XILINX_PROC USES ADJUST_DELAY, MAINDATA; +BOOLEAN X = 0; +IRSTOP IDLE; +DRSTOP IDLE; +STATE RESET IDLE; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' //Loading device with 'idcode' instruction. +IRSCAN 10, $03c9 + ; +DRSCAN 32, $00000000 +, COMPARE $f167c093 +, $0fffffff +, X; +IF (!X) THEN GOTO F; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' //Loading device with 'idcode' instruction. +IRSCAN 10, $03c9 + ; +DRSCAN 32, $00000000 +, COMPARE $f167c093 +, $0fffffff +, X; +IF (!X) THEN GOTO F; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +' // Loading device with a `jprogram` instruction. +IRSCAN 10, $03cb + ; +D = 1; +WAIT D CYCLES; +' // Loading device with a `bypass` instruction. +IRSCAN 10, $03ff + ; +D = 21000; +WAIT D CYCLES; +' // Loading device with a `cfg_in` instruction. +IRSCAN 10, $03c5 + ; +D = 100000; +WAIT D CYCLES; +' // Check init_complete in ircapture. +' //Loading device with 'Bypass' instruction. +IRSCAN 10, $03ff +, COMPARE $0010 +, $0010 +, X; +IF (!X) THEN GOTO F; +' STATE RESET; +' // Loading device with a `cfg_in` instruction. +IRSCAN 10, $03c5 +, COMPARE $0000 +, $0000 +, X; +IF (!X) THEN GOTO F; +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +' WARNING: This STAPL file describes a data shift of more than 16K bits +' which might exceed the capacity of your run-time environment. +DRSCAN 7819936, @Kfk30000000@@l@@lAPggP8000003080010000E20000G000006081020GPqfC0e004GcFGo +1D00GI00000C0m00400060C0W2040006080WqC82421YW09G05G03m@3W@dV@F@x@yp@pV@F +__@uV@7Vy@ud@dUz@ql@dU_@qt@7U@@m@_Fym@3VCX88P0000GYa6a3G280G0YbC10081000 +0m0020050MhM00000W408820421u1001051uHW0I0wj18D0O638cY1_10G_Gr12baGB0080c +K06GH90D28KT0wiuGcfeQmB5g0uV1OaY0Rqm3000Ci600YKmF0008NWu10ywZ39IUoWaBPu@ +HA_FaZ@@8v@EM_VZc@puv@BY_lYf@dew@8k_@Xi@ROx@5wm60mTTxaHjxf7Z@vnCeL0mc0u2 +W4Q_yd218fPWP000mJJ008f0LgvqZc34A3L21002qtW1J0OGfhd0u60OoLv006001008TsJ0 +00WX400emM30001yERQW100QnL5001WzeA700G008W0tzg2OJ5Wi8U8xpy10W00000f103I1 +WYnat0008Ax00WcK@VKQ3Qy8XyHC0208GA0FKDX70160MaUC20080000020W00000808GA0I +ydZ7Y300QFMkyZP850Awx_XLKI300140000900GfXRmtr608W0000W8002000G47OZ100_Zm +mJ34G0000WG001000WmkDtWK0C00600800000A0VdZHI1cP00W00000H102040145m100040 +20E00O00000410100W0G4000iVD6000ej200aPjPA0G0824004W0W000000202288W000080 +GG2000GG110010010WnoN100cZkjD310G8HG4040G000H001010005140G000KaK0I000000 +51Wzxh0u51mWzZfg50m@B2Fuf20@ZPcWdggi8cPQHuhoY0yVA0C00004y00GgvLm8008Qzn0 +G1C1W2O2m5m4W9W90J000c00K010a2038000@O73002rXX@@Nw@t5@@Rvdv3E648e192QmcV +6as43L@l10WFd@@r2010GCX904008fm4IXBXt1D0002m@WU0_A1OJFmYKWXD4V8IXJu800CP +6OJDcmMa60020OkH36QAX_3z00mB_@@l1W000WG0KEbj0wv1u@@t0O210808CsFL000ofL00 +u@@q0WP61000400G0220Wm7L10G8y@@izkf1hD238S3W@@J30082H000WE006c8044404IXA +E200_@FD0W8600020OW00WIa0I00m@@d00e@y@@w0G62y@lAW0E0cIjk1IR1H00m@@o104Gu +KrM_@@@@@nWDW00MI0WmbLPTXM_@@70mig00Ww1UL10er30e00m@@d0080Phtt0060A000r0 +00m@@g02S0u@@q000mZP00WuWdf0GaR18E07@ULRhINyQB@@l10q6W6m99py42tsuCgR9yQI +004QrfE9PcdGFxjG0200100mCuI00004088GYxg0WN08xTO0W00C9F9Lrd0010WVmDOTj402 +6046E3G000QjV3000Cq700wlFXvtPG0000008000085qb00G008WG001000G80SBE3nvpm2_ +C0G08Odt7cbt0000W0600gltZD@P00muq@@9yS73pUR084000010B0p004020000e002khbX +8RP8uU6YWt04020Lmp0G00000W00O01I0N50i505@V200G00801D5xH692DFj4000mu100Ka +2O010023lbcwV00somVsRieD30100Y97Z@@t000WIY@21U70eBnYgusZmmjfxU3000GfM00O +hRF002000009cyAw8dXqyJeck74800G5048CyP0020aXk1006O3bSZtzDeiV30Y004Jk4TqR +GrtIiyF3@LpGOuda_v306K0QxZaAlP8cy40004i_U2Fb@Gux600f00W000001emmV00G2GOu +Xa5V2000uID73000G0W8000K0082000I1G2v9W800WK00KA0C0AX82008GEw9iLl10100000 +X010W00Y0GEuC46k1f0mGOuO46V200SC@pUZQsDOvI3I8F10008f0mm1L600G0P1d700G000 +00H1aW38e0GWC00W0020We0220001W3e10004000XXp0G04WiOO8qU3000Grpl1WrK0_@l2m +0W000O0030000WHW0000GK0WOoD0u00100W0W4m1NqRmYi6000000K0GveFG2g00000001G0 +000W00080010201W0000KOu60411CCS30H40a2W1XXB10040W000000ObF00KXN80004Y6m0 +00800G2082G004WA9XS38100y@@38G001004000060000X0W2I008Gt4823VcG_D0040000V +w@@n02YWG2vR4Jk1eG0210Wc46EO0DQ0_@l200m20uV0mCpKfg@1NuBIbgM4W4oVmYOcf5X7 +002m@@@R0m00WiwJ00G0000040e900W9mT000Z0008CSOA4mWFTJme00m@@L000A0J0KG2vR +0O20G13002u200W0e000Wc62cR@310KLVKf6000GArSH1jp044aA9G@m0RO0W00ypBIs7_Xf +aDe7v700W0000WDRMF01004JC67njHq0ICaS83qY1010000UDdVLnejUyNT236NH7IdiecA0 +CV0YJpZPnO8IXJ6ks000WW4000000810G000m0000102002lCBHaF646k7vrnGnVE14000e0 +00000G000WzbR0P00mC0CeME30000E5k7dOR00WeZe7g00008000apdC8YE60080C2C31Wdm +dnFy1d10a00c3nWdrD0020qwn6iVy3LSlnCx604r0eUFCQUeY5jL100AGa2608W00GWG0002 +0041001400204a5U20280MvOZCkJ8wQ3QdGYKtD0400HtTCqJX4jaRGMSCagN20088UdnWcz +C0W0000Y8Y@@D00X0m@@g00OTu@VI001000020004mHr6SZV80001W400088000001000400 +G000X00020W8Y0008dW08004040@@h2BF1W@@b000mm3YF0000404W1W8214200N4x10022H +4H00040_ht00010Xy9X88201880x_V2000IS100ZYI2008YDOCG4000W81W@@t004H4Y8E44 +000VKoGXT900100002400W0W0047xdGmvU00Otx@@G0208040000412000aGdb8G59WC00Wv +W001000i40Wn9D000emcO6WPc100m8W0Oc02o8Gphinx@F0GD1uYrD0200000020A001000C +h2WWGG042p00WW2ONpD00G4OcP001A282000e2000GK0003400W0eaB30004WW01200500G4 +00001BsRmEZU0000pa00GkVUyub100400e80056400000885W@@z00095000000904200040 +002X00040004IeGkV0000IoCX000000Gzv@@O001400G0000Gg@@DWK00000GWQyh0K00mc8 +FG040OHR6W100080006O0GOuF4Y63N@l1O95W@@h00X00G010X100NdQGFf6S3x9ZbRW0100 +CGn040Y280bWW6C2vG930W06Cgh100m10100dpN5PX9XU10W@@h00802000K020200010004 +10O0eN79YarW4rV000800044000502001488g0400126001000482000082W04Fg4h2v100P +jHQz000W0400mGXRXD000sM1000E00141005sWGGOsBKP2G1WKl040000233F1G00000KHoS +X40nA0@@B108m00200Q00008040000056G000y50O30LaRmqj9KYi1050W_@d104U0OMr0Ga +xO2000ow000p00WkXJ000eAcfmVa3UL20er50v0y@V2eA00c_V3000SXli100m@stC00U000 +0uJ10wh20uv18000Cy1e_OFW1000301WtWV0@0x000_100W3000S100q1u0W1mE2ZmmD0040 +00G000W0mXj520WqpnCg0000n103000W083W1G720WC40v3a0000qIoJ8Q03ol81000000WC +5WgmB0Gh7L000WM7Wmmb00w3kC30HS70KXXJbA3G1w70YsbI000WdtcUBB_@3000uCk39bBa +Yms6000000WU@@d10084jEQm@@BrmaAT@Z1er4Wbz7h2T6UZRc85U0G00Ikw5DRk1P2PGmAF +KK1C00O8xUNY2wheJT340014hk7LjPmazI800000G0Gmv6G004uiN3gz33W000VZRGXx608S +1uIjMwMaa6pJ0100K1_6auj1BdpmjuFKc@6000mNELY2wh8I1Ls9VZPgJ0200mozaSYk100E +zE_tWW@TgKS9wspWj1j1Cn0mvusCcS8Tbn0000XjvD8_V3G800KrlA0002nE00a1ZGR8kHgE +6CdEF00OHJILhMupfW@70DF0i3lJpk@010202040NZyW000W6VK1000le10X2xZQhP38000W +000Oa@44e00a_l1000IMwl500MqXKGLLR60W00000W0W020I100000405K0a8k100100902a +xlA0H80w7t04100jlLn25s00G0000e0G000A004W00GY0@108Y8@Rg2000Kt000F@RGwtCat +FF40Qm00009W00008O10Y00G8W0006001C000O010W500000D80CTqs20WqC0018@@R002GW +3NM2620mjoC8000eTJ32@O60Q400C00AxZXCe@10K80010qyEJ004G0G0Q5G00000OH04002 +0001G0G13800Ws00HSf2PeGWK1O8FgkIB@XQiF100hIYsE100EuGH30E00afe10@00IWB10W +1m802mT00WqsM2f20JBtY67UQLn130W3amso9hwGUztWSnJ0200GSO6C7B9d_Rm@@60aW1OJ +kJ2zcXUlDeXkP0000M57C000GL200KJr6HAi4030W7jF1004mcwC00m9AXyJcA@Xa_DOlyD0 +0W00800ysV300W0izL83np0044WrdP0mR1GsyOKxF3fr6I0z600100001mEu6G0G40210G4x +CaCa100000Y020000P3U6EVF10042XERGJD604400000XF10mGyt00001020agSUW000G7dR +Krl1000C2i910W0W1_R0104WD@J000Am3@FSyV2040A67t04004000000irrdU8402000000 +022OQy4Agl24000HfRmf@9082euoU980000002eSKCG000kVF3a00100000kO0uMV600K0CG +n6NTHLnOR00028243K000KF6INPx10H0WY2DukzDAztWgvDOgV3002000R_0000HrX6iXZP0 +002sotW3kzefy400000Ao1uN@4_KtWI50xBmD2y@Xu_D0000g1X0WsLTQr@A_poWUzDW00WG +6R94DF608000010yyl100ax7fFXWRo9CVI000Y43N2vHRm3_I0000iZU3YXC12000440000X +02G010W0WG4GFKGhJ00010G00GA20erU3000Xail1lmNnut60H100000W80G0000yS000000 +WG0f0000WGC09aaRKG040000W08000000IftCixj40004W000000C02000000K0W0000A8Z1 +8108W1n0amalE100W2800O0_60W00W00000408K000R_B1K040104X02400054G2Z0e@R308 +D4X40000GPeY0008O10020uM6qWGSr2080mnG64GT5W082Ykt000W000G2W00C200W4a1GmN +q6qdI2R87LMS60G208aV3001200000140Gl_IW084G00q000G010G40002000H0W6000GQ3A +0G41GQ30201Y1m000G00e10kzugDaR9t_40yi0i8zO6200W10000G00600mbt60004u4T3wb +c10CGa4Go89WCWG0D1n0o0g1Y4434f00008at1HI0lZa0o0E1a44383868I0MjmW@h1hxQ32 +fx1L500_F8cnCLCZPm3t@0ulWmCJ110000kILLG0u@WO6pK1W@1FSCJLL220004p0CPN_Jzp +m1qC4Vj70008P900CNNEzaRmPIW10m3gLTdU3@azrPOsuG0tr04jLEzax1000n5eD0200041 +0WVpP0000OizL4rI29f_m2wXyak1NvRmyq6yFj1zfdm@xO4Hf1xrpW841WHxJ0020Gbz600G +00GW0000203020hyRGMhF00uGw@V3knnWG@TIW40020000404@@dW010WsrD0WG00C00WGiP +OUR308000GW0uz@70d50i@79t18HhXdaLl1zhQGemL000040G0800020W04V9K1000MS000V +zRGO@ayJO5N@BK3@FaJl1G48088000141000CsG65DhV2BxaGs@XG00GW002mMvL00We0008 +Y0GG40GWa4100Oem0akDItR7IVwO0020000GmxaCaNl1RJR0000K5300Tgho6zC4PVBbuN10 +00Zqtt0000OL@6000svCpMYktZPet0200mzn9y@l1088100m4q7V2P@p00W0G000p220XH10 +YWP000eV1mhdjCSQ2xoPmHzC000A8Y@MG002akL2raaGr@6Oa0000000XH00bW100008O200 +4dcA5Qx100W80828FnZ100GW5MPu3Q38bG0000002G1000GaVkb88S3000h_UJBh_Rmiu6iJ +@3pZRGMsO0W0020W8skzF000G0CA0008AW3yz0Wf3GnNaW800P0Q30200000G08Y00408W0C +UuKV3Ur73000Gf0@0u010O000I0004012200800WWmZ2I4lk12100oNY4W020W2000082KF1 +3lvdGW_600O08LELkut0200840080A00aQ@600cjw5lbE@POPx4k@tWgjt8GL6_@F1KO0W00 +uN000W00201G0010000a200@@p000m6W00BI0000ET0CfE900W4G00020088Wk4c8cXJmD00 +KO0200mioFf3w4W900ymk40UU000@Guk0m0_1m0000crfL10C3@@@OW8Y0000GL2rO0000Pt +Q9Y5t00W1O0W9mT0007ly3m000W1W1S8d100aKhpc4WC000O00gdpWH0Iu@V6G50002mE8hS +F0006a@@90G4t100i2Cy305q70M1000WE0r9srZj21000KA00mfvobJ_3xvx1009@Qh3fVst +s_N2W9F055RpGIUqcy6dcRm@tCi5l7000WRDPZquv9XS32esWcKJ01020010W8OC8aUCwZdX +fcD000F@_yO0201uYU30010iO530040_ftWJdhubE3080000K2W000GNw6yLE300W00208G0 +00yhL3QA@1W000pZdmg_90mQ0u@VC80G0zET201008W00aFk10808EdcX8TV00010002800W +04K04000CSgV2208000102080000GOxv6SHF6m0002@tWc0C00005H10Whfh040WHd@60020 +OC83W000yGd14060knkbMzDOo@4G200G0000G20Gys9qkV2JMN100Wyn_t040000W0WVxV00 +W0m7@Cqwl1v_pmjx9KWU20100AtFXHjVG00WGj@X0o_080zAgdtWbvPuiR34000CRV2Y000A +_ebiPJe6@420dXXyn000O1r10WL_nu5M3MXt004004W0802X40000CSVFcZdXUzJ8hU6wztW +41F10000006lcJy0004GUyC80002000K0wUasl10020gCKYUmJOwzM0Ku0CC@68W0G004008 +80m0000W0000W00zidm9q6Cql400WWW000iGl100W8wed10008G0002toWTXD000GGcz9qJF +6Vq_m@@90014PaQ3W1100001400C00000a0038GX2040WOW002000q3zO0080004W0000miy +DunJ3W000qyT24004cmZaw@J00mVt5@O4Qb1020150202000GWK00404801e07vR00800091 +0@qNHdA6K1d1@@p00a2WSsC0800mUz90A00O9uG0nt0qI864G80Y6m0000H000e0008000WY +G00mw76030Wu2E3_@@10043080WI@pWfsCuxr7W102ya@30104cys3F200NyZ1C00020W8bD +a0O200000CK0000880aql1PkOm@@L0W22OcC6W00000W202e0mg_9080WCB_4Yst02008@_N +10W1nAth8aX400H0000W10000O60WldDGC00mP@64_76Pv62006082001hO0W00WwhDed_4M +_N2WK70r@Bn1j9im83lq_GX@O002582S6G80010080520800b0010WzXR010000s0400000A +00L7t61IbWb10Wv@b0560OnR60020000G800000O2D00040e904ql10000G088P500ua@M00 +y000000W16GsrC0000Swn46_l200v9p@B100mV1820J1c00000U00008v0GEv1000G600Gjg +V5WnVDey@AESt0w00000000G80a0N2000m10L00080r0002100WodC02030804WKfO8uV90R +L0i_l40O00w4m0088860304200f000WG000g000O0A000e2m50000mFu@VFyl@0000KW200G +r@I004Hy@@7YlR3000KU700Arp3Y3Uc20Hk5Wu_B000G0aJEH000WIF0ZYtxLTdK7E3bI@mO +yF00000q31m2pRaGU200G0AOBd5tdS7TIkE_1G000Nxd0002WbqV000FSALXqwk1pxV200W0 +00G04400MiEXlKO8zV3m000iHj40W20Uf63GXA0D5xnAwCKa_3ZflHOgIqDh100W0800GqNl +10GG0oyF10W203r@GNzCuVG0usT9wUtWvOD000CGkz9S9W1Pi7I@06yEQ2nWdm5II4yz6txd +00WXbFZheSV36wtWRmnOUUCI_tWpWPuxV60G00G50001000008eMwJ000G10e0WWwn0Ox2u6 +_R80000200GW490044StZadC8vI6_VaY@3vu@FI_lZb@tev@CUQ@3JFsvtWZ_DegRI00akan +DLW020wKJ2004W0008sHE1W010W00000W0aYF3Dm@mAy60oT1ORQ9U1j21000bKZnYvFKJQ2 +0000t0dXE0C000I0002WpzJexfD_Qs0000Cq500c5@XxIFPJxDkzgY64U0002Kcv6SRF3zcN +100vrTjRfAJIG4028414W000008G0a8I10G001W0000G0WG080010021G000G000X820K100 +000G4GWDfDuKw400G08000G000Ony90wk0uNT30AG0y@l104102_s000020010W000qtR2G0 +W06Dd410C2004002o024G01G032W300G50A0P2G02C80641H0W8e000K008020005eW00K00 +000208244G8280C000001000050008008G00K80144000WG40028042G000000IzuR000HK0 +000040GIGrWayb0W0G0400WjqPOET60W020W080X00021YGGGeG60208004100W02418Y00O +00W0048000428200200G000060001000W80W21G80u5K30Gm00WG00W0100000GG0000ki00 +10aOh1@@d00G4000G000G001010W00uu2300008W00G0000000404017wl1W0GKY000802G0 +002048W202310WW0I0290400910aGK0G02K00GW040m1001aG0412000010004000XEoDeS@ +4G10GW201000008D50G010W02001G0WG00080008G0GW000004WggpZMXPeOO60W8400W00W +0W0G04aLhD0C000W06Wm9OW000800012mW0lvQGYz60800OcR6I@r00060000815000400OE +N3000a4@F65ch21W1020W00H43G80O020G08G4014001W8809000404_@l1G140W20000001 +0WCmHr600048rV9W000010000Mz1000000240002ojtWrvDW400GU09804GOP@M0G02A0W20 +80001003G2400000032000100101000a0H0C1a0000092acj1lnRGq@U0eE0uUV30G810002 +40e0sRx9iCQEW1WWEan0W8W1H@R0000280480m000081iZk1V@RGOy9a@V2rrRGSxC0000KB +0WGe@900G0101000020042008106UdXh3y8gV6m0J4GnW02HHX1I01828092ImW88n100G4X +WW00EO0H2H0W204402m2Y0WGm005002Y000G1010W0000Dul10840knF11000460000mV301 +W0080000G2a000eIg8C2H49840OCZ7UzEX65814034194G4GGW2a2i4324002100WKC5H045 +W2800a0W2841H0O0004Y08008052080X_@t0a800GW00Yxd180W0F_R08t10000005200828 +Shl1G4HA040A200euo_48W00Kjk7@@p00WC00002WIA00008G41000000P1H00W20800f808 +00403WK000m00WDXC08285Y00WwHC0a0W0f0000002WI000000H0fW4008W00GA0004a6000 +00GGAW0Ot@40W12100000W84f0000W00aY000WGIjzj1Rpg2GK000K400100W00080G0G000 +4GG0410G0W0140004810000G000204WWW2000HG44046l1tTR0G00000120H10W0Pa10G000 +mLQdy6yaa1x@RW9m0000000034820080001GY00CG0WKh9ft@404O080G0K1W1860A4G0K80 +X8c00W81k10G000441gWz@D038Wc0G080G0002080C0B4Ql1004000G14sZ1221C060G0E00 +0Ke80E0008040o8606Cm000030u1O02eH803B0G12000823012404GInN5G8ae001e9W0002 +14444H08400004340800a4C009X0A842Y000008G06000004GO00grq42wt00008400G0W2G +200840040000O_200400GwfmWQLJ0G488180mbKJupwMGX0W20oD1G00810040001CXG00G3 +4u0010Gl0mLH600A5000082eq0000eQ080odr0GG0101uLGW0020WCP_A3040KW0201ul000 +WFRGG080WyL0400002010000Rq34ij25i1O0W_B210000XW040e00400eU100Ixz40yJ5000 +018CmmNJE01000tT00tf200u00St1_XTsfI0JuBJ00000mN0000000VP2GXdg0000Gax5ft0 +uf3m@@600o9700eAWMF0WNL0W700E_d100W1yF00o1@40S000WB0006W30C0M1w0g100K300 +06000W10003G10LjR0CqL000O00003I1m0w30H0T0C08000y30003000W000W08003WH06Wx +000t1000000EfK000WB0006030C0t1O0e000S7000E000e900mFm106WV0C0t000s1zbhYW2 +uE70mNc0exS0Y82000N0kx0005000m3v@R000e20000W8Y0y3004bS2JSNH7v90088000mFc +100000eg7000F4xA0goK0C3mm@Cm03086kPkiEXoctebiJ0sy0i@jMXGpmts9CcT2008023M +YckPeiR30000fV00OYxA00W04pV2Bpeoezm4O39004fJKFgJoD8CB3000008088zP6w_FX3k +VexyAgEt0Gm90rQLHa2CKAN5@@Z10402e0022020104G0GWGWWG840O40e008002C0020000 +304000G44mRrD0C00KcR6000W8r03000GjtE30010000GhV0Gejx4cTlYnw8PNl700G86yk1 +0100000Y00I11GWW8214KW4e04000fA080G824A02CG1C000G900GWW08A0H084G822404KW +20W20000800GK0040W00G10000xlG000WG8000G4000100X0WxiD00W0G1w60400uaU36LtZ +0wJ000G80340884W0400110G1120400C8SG4G000WG4a0900821034001804I200040GG00W +W00e0G002G20008011X00001C02000GOM13000120000iu0W000WRuCulE3ImFXF6Dey_4cN +@400000208400002000400080W8H000010OG2I01G0022000W8204G4C004W058W0400I000 +08802800WG22200001OG0u6130G80000W00010000QwA000W08000G010W8J93EeNYgwse9E +9002201080WW000C40020W04W1A5q00028000200080002480000H2Ge0005lRmpx60W10Oo +V3_T@100amrAOmByCSpv6LqdmYX6yAV502GW10O0010u100004044020404IXG8W08000004 +04GG020000o0000000060X0000W0W022002HpNHv_6mqq1uXT66wt010G0V_@Gfz94zl1rAi +1001040000090G400m2W0220G08000001009000W000404480W80W000W40W0W0400HKqk10 +G0G0020koV23wR008000800000mWE00Cy@30W10Est00W01BKeIr@90G0WOfV300WGaqG200 +02G00W0280G0000010aj@I01K0nQ_C4AP500kGJfl20400nuRmF_9000W8_@4YoV3000DY84 +b0aKWG8W806GK51841Y40G023k458I8Oe220H4ZO04K0M0Ee024DQ8H0G00yA130000eG02G +m00W020WMyDG000000GWYLD0a03W000WT_J000C200eK10G8G0040001451300G0_@8X6xz0 +XG080O4244CHO10W44D0W4880G0004H10008W8000e0080A0G0101090G8a6Gem004016C0W +100008GJBI0W000000jpH0WG@P00GWmm@60180enV908000040eoE3400HCkF6005e2Rp0I1 +9a00GcWaK0G0000AI95Y0W0P8eK8300W02WG80O00002fa200GWCOIA00908G40a20W00G0G +Wh1C0K00G@@600W5lrK380100004WG00001008840W0000Y021000Oym4Iar0014000W00WG +0000IOCLC4000Syc1C20Ge00eeX0018Y400002W0Y8008Wm0810044G00W10G1000080H400 +4G1045K0261Gy9600GGuCr4YYp0mJE0G000002W080000WWHql643d1G030000WyeB3RyQ00 +01WvuCu@VC0mW0881n0032000K04X1W4Y10H4HGH0A0200082Fm2K8WWme1Z0006W1mC4004 +0GW0O0101oW1e8W5G00YWw@V30WW5W8000044GWK68T0WgrL3040500W32Ju102W0802PObj +_00110C000XyQ008000G1W@@Z100WH00C4GGG9102100011WC010X80211A88020aW000002 +5e000000028e200W880C0I485000WW8GY0Vb01G00G40000xjJKm04W80000GJ4PmTLU43t6 +00010k90bxc10W23G08Wx5AC0e0mkN42003050180GnD000GV1560800@5010u0W0G040Ku2 +001vlG830000q000040G0001080000GA0000WG9160G00G3000W0000040eW6422uUX2GYbp +WuUO0400000LaAZD0G0G10000WI00@@B10S000CH000Gt10W000018WN3000tv00kp10WBS1 +0000000W2wZasWtGD0n53mWA6y@F6o100_@t300WPL98n@@Re000WY000C060O0S1vkPGMS6 +000u2u0e9mFG5XV00Up000m1000C000O0E0y6S7W1uE0WsP000CBf1WG70m48300W9u@V300 +aX56d1W040e98YG7mD00WVGiS6000a1u0W0G4000H00v4R00G000W0m003WG00W7n66000L1 +0ea3WxE000000K0mieD0Wg0WVg80VDXVO200010G8Y0000000C0u7L0mNc000Aum30000Wi0 +0_@F18Y80G4H000000050u@@4UYqWr9au@@Ps1FXAb896E60700iFk7hcx4004WUhJO@S3Aq +qWBqh8oR300CvFikM@@Z4m45Wje8P7_Y0002yYa1nddmYy6aVb1PxX1000U4300zu55001W5 +gC000000G80G00000H800802040m000m_MC0100u6_4wgu10008080G000000WTT203ontWo +xJ86S6ohhbWnO0e000001000010050012008100000800W000GW2000002000G0ya@40010S +pF60c70M0FXK_Pu1z4YGE10080f8ZHy@FKhj1G0Wec_t0048000000800300GOrD3MSt0500 +008006kFXynIetj40401080000008610Wb0I82R6ALWXdyDe2R3gj7600G0000900E4SLa1n +qP0c00W1kJeX@4k64300et3@R0002000W4D4CJhzLa8@3ntdWG00WkdtOWEC0h1048oOb_dW +0000000GW410sK_X1Gt000OZF10W4zUuzaVAzFXH_b000020004W901G450cJlYFuIuoV600 +Ca3W04OOL3c8aXEFlI000GIy6ySv6RbB1mT5WbKZY000mFZ94cA3000CoTt03CH0pP@m8z60 +010uiH90000nS00OBE30008amV2NPsIHDa4Fl10W4400082LCW1GG0nI_LiPa1tD_00WeM0G +005lzmhf9qCxFBz@0e00000010GA0080YaaZ40001000m21e00029001000840L@d0OE4G00 +02010XoscXs@DenU3Yc5c@pD81TC00W0010q8vo7000W00H00080mym606GWOMQ32nF1h110 +08000061K5d1ltdmYy6SRKE@fzmwi6Sbl10W00Xe1Oa@@300A0000WG082w@V3MspWh@D00m +@4A00eZSVuQq4guUckEs008004W100G0002820601ScS5L3bmm@C0y408Oq7k9udQLJ8b@70 +0GY000001002W0W2o0000b20UCd10GW00000G0H40G00mB00mvfC0000dUK20000K4040je_ +0008X3fifhC3Y_j200wh000000L1CsV8003CMzF1000NTka0O00WGf5wgL3o8k20W00003WH +04Wx000emS6010000G6eoL3000G000m08000mE2WL@J0KuOIUY60S0G87x7s3WXDiB200u0@ +100mZ8u20k840H0aslAmq@0gUZd2q630mY@AzdSjDLpVbmj@60I00uq@A0Tx0avz99m1sdsO +00002E00G0FpSYJEXV@misCC5F600cs_rwazrL9gy4Q@E100101nQ00G0000I0G0W02GdXGj +D82T3wsl2mJ60@6BnAJyykk1040000W02001OqO3__t0008WG00OIutWroDusM3whJYahU8Q +w4sQKb@hn0400800000044zmR000900100rkPGv@600GK000044G088001@@R000Wa7_D0G0 +1mttO00GNRRxJAvMYbsV0000KQtCqOl1Rrd0008Wv@D0m00mrzFiOF3nfN1uE4Wi7GgH_D_z +_XkYQ1000Xm00WQuOB5qP0W10dKWeW@U0gVBgAJzug@DQel2000qW600w6He_z3Pqv4sntWM +6n8ryA0086aKWJRjzpc@L0yn0OMFd2wV320209@dmwyRqfl11wd0000C8300r4WKdS9qzu6v +zdmJrR01008wI600WBSQxF5fzG0eL000W2W000W20WwNJuS_4A_NYe0Ce_V600j0CqZG4082 +M1yahviny00mEmW1008W403mF@F8100uhV9GW00_ul4000EVyyd0vO0140G_0LSPZeXlP091 +0WL_D0400000HWe0me9E3o2xXzjDezlV000WO080eHEL00u1ivjA002SkgMh8b4AwV30DC04 +gjMttRm9@L0001OLy4IotWIgn00005g00WJonuFh4_CtcJBzuzy4Yyt0W000NLZ1006qZjtu +iyP_v_X4eD8VlPg@d1GH80B_nJkXcHF00uTzDIitWAxFfZuM6ttWay910mMVsEX0W00uRVI0 +002qgQBrph2mW0WzdG2010OCapaaV8000Wy100azW700020001aN5LTl9wcsgGyk1ulieENm +_40t30G0HR@a0iz1uElVYd5C000GM3002f0F0008HM_Gu@L00ewOzFgAyL5G040Z_72Gi2W0 +uQ95Aa00000GG08QcJC2004F2UploGr@R00usONhwMdt000A0NF420000G860d@VIiSLKaZt +0e000060aFx3X_NHQk64Gt9no9Hmzy000O_Dhzg7t9000KfKAKqG@VJ_RPdpZ510W_Z@40Wt +z_ygqtk1J9SInw6aGk4G0000G004NV23sdm8x6aMU5WV00gr@a7t3vu@7A@tWLvV8_S38000 +iDV2jp@GPuI000WH_00mWsdaOF3fJ4rzyR00GEfVPLoUmZiCYQ@@40Xd0SIu3DyLngur5Yl1 +00WPXD00qhD9pF_M0_6y@l100WtoUdaRhMgcDg000G20000001IwForSl1000G3aoWqxhu6V +300m000WH8UCIMWDgpfD00G@xCxR000G8aYwIYt0XG20000280000Eq1OP7F0WG00I00uHnt +Qns011000004000GJN00O_LFm000qcnU200000Ss4JR80W80Yz0lGyD0S93maiRaBN2RhL70 +A0000G2000me740KSy6G000000K00000WD0GTbxjnj100H0_@N20G015bZ700G40000U8000 +0000C398mV3sek20OC00020500WiZwU000uO900y@@6a100000000AyVspekzN500Vw@WKqs +rR4HDCjXpGXu60MR0uGR9AJVZ1j9fny7MOhbzwPe3T3000mBC008k6Xo@lB00g@@QAnzsRSf +uIjpg2eb2W36QPAiD0G004TTB7y72400000G0000eBxh550007_YKOud001000WFJ@Wg000G +OxXhkilYa_J0uX0mLwsyc_3PFCpW@guJ00erVFYougy_L10mnvLUibFlD0Z3GUSaXZVJeXQ9 +Y2GYK0euGUx100WBQ00u3pA2es0W000nUdGK0Ri3HN00Ib30IY_xDeSy7Y2gYyWuv@VLc5_X +dXt8A09o3GbR_@f8E3w0mXe0E9F0L_@@@vjF4O43mcLyixy@vM@@jt@ddFdW40050000m00u +@V3w0m010O0f0G10G0G1000001800000m0W850Ag48Xa2SIW402Y09G00088I420001Y0H80 +816OA0K45m9pvJ5892019I200004aW0000W4H220HI0oK0e8AWJ2n@@@@dl6U302W0000000 +00500000W20N0amiyd00060000000XWX4h0KF1m@@CeU2085W72vCawvD0m30Guu90600uUS +600080O00u@V6W0m0a2m3_0Q200000G017z5q40000V100df1PI16000e01WJVI1cH020eWI +IE@N200zmZp9Amz3WXv5ARMm28rWdPHgvrP_xF400zaJfzVDrRisV2J0amZ@O0000sr00GV3 +dqQEI0002YeFXHwJOszD00SWbphYD_Z1Ol5W928SU_wETT908cZN58Ae97WZy1Bf0XmA00ay +VNbjB400ci5KqAi4a0050ie0Ol_84F00WHPwg@5XIAGhatD0000oGD21QN0usCpIpW7A100x +Zq528000q00b_o30WEY5Rv70G000W042008tmPGqCymU00uiSj00u1S9lG002SMLlkEoJef_ +4o_V3GZE0@RnMjxp000WB6k765sC000mt_h20W3ZywJRRiS0SC0iT4Xpgdm9PI000WnY00m4 +U8zg0IjnPm@j6004000GQr4XjaEN2PpLHAW94O899kX1100W40881H36ap0f3007IeIVYCy4 +tIttx100bcEWMwtkh01o04_F38001Me7I00W0Q200U8qffz@@@@C100mQU008yq40004S_m@ +@@d3807W@@J0008KI1Y20C0u@@910S4MJD33tQG39G2C01u@V60100cDdGpDv40004D200rE +p0A40000811ltOePFaaMHBx75Ol0WnCO0O70mun@@@lD00wS_@NKG1A0ft9HHSRKWy3FoPsR +zfzxSE00migr3ZLEhuCR9gxibGpPOIJ3wqaX6tDeyS90QZ00010wCqG0500CokGbhp0002eV +5huhK9000WmQ00eUr4o6tWd_Jutq7W0G0CVg40140QUS6000004G0dVjY23b00GGMmu90001 +000G0000eeOJeH360004yc33fIQ0000YfDUOVVFohNYwKPOaSC0v@0iUV2l_l1O00Wgu1RUz +A000100004c00mMuGcPF302000WLcy8gG1vp02G0Wvpdv3RF0UE0CjzFnCcGzwvG000Ot@A4 +0008W008RM3MzkeCFjX000002G00400Nopmou90902G80000WuG0400pZd3021WM_Duh_4Mw +tWemX100WmuzI0040000011000GCC0PRBqkw9KdPBFucmEx600H0u@V60WG0008000884000 +0y2007k@3140WrTbOSzJgbsWBih0600040000W1000_qMSd70W0000046WtW8hVG100GUha0 +000w7v4caF1042000011m0Gy4Y1W8N00500yCVE004000W02000200Auy@miwp3nYB1004Ww +eCmh00G@uvyiS20080wqt00G0080006Kb40010DDRGLp6W010u2t42WB120080_50004RY01 +0SbrSGW80200Q00002004WsoDuhl4_@F48200F0Sm@@L000mC0keI5812000W000AXF40G00 +001000005Bk16000Uxc1O000m0i300u6000000Wzi100WK18v@@Ao3m0o020O24100G44a09 +fJr20C3000000fT0_@leE1C8yHm_@F10900huA4020Xhen0400mpfOKAE3hQO0800000FEDX +pGM@jyEi11@@GtuK1Uk1OLvVMTdXZtJ000GGTzIifi100800G00a7U5FenGNy602G000001I +10WBcJuCpb8000sIl1vXdmsp6GG00O4S36b8XBxD0W00uauO00mWVWy4cH@XGZU8MQ90800i +CT2xqd00080012000000G400000G00W00110002001406QB110G0010008012040100220G8 +WogD0014nTr600G00A0044004e02000000HL0CQj10840A@sWjfge@Q9ApdX3oD86R3YJtW_ +qD0008000W40200viP0004200800W020W0G000000a00000000140W0000W00G8001a0m@@6 +020400020004YDzD0c00GAD901008rZ42UdXhtPOm@4G000irD3O000ECrWhuC000Gpt@6G0 +008tK3g@tWwtJW00H000G00208@CM10W0008000W00080000mwRCU3UG7ZE@au5o4IdFXlw9 +fJI9kyN5G3A07e7oP_mq5e10400MHF1040W0001I18XWRDW802GrF60000fP@4Y28Xl_J000 +CED1000202fQnGuwOqoY1lYRpz46yN@6DMmmmzF00eZVyV6sF_XTuDe8UFUuNYlQJ00W000G +002000n8y044GW9@bG020GleFaDQ20wV0M@@110007i@pR76040000W0Gd@604a1PeX40202 +ypl18040Y6nWfyJe303cS81W000000100003B020800KpT90006100GqnVL0110u@V9YzoWb +1t8zg4MMsWFGC0100GNd9Kpl140H2UYyXr8J00WBTg9CK@V5LjE300I90G20TZQWI0000184 +G400eaI0820W4Y010000H00WID0O0W0820410K20000a100W00082000280410G40WYWn001 +00WAR0002000WK20000cGGe9Ib0020mu5CKAk4dVom@@6WG000140WW0mKYG000000100402 +0C000G0200K08Y180000W10002K85W40A040050W8W0GA090K0C00400500K0001000WT808 +G0000140000G02W10PdA1408eInzuDt7026m00700W0010000W4m0ZRP0fW00OK442020001 +W9YHG0W4410811G0S000a80100W0GmW1G112G004004003W000G0000100G002048W4000Me +10NG0020WW10I8l9irh4d1Q0G00X@@D0500m@@CqQA3TwO000G00110001e010000W00W9G0 +8000GG4OW00H0AG000040G48e01020G0W008800001A104020600CG00100G0g0440G4080G +120GG440000Wn000040KHX1008000Y02041OKO90010000381NI00L20G0Gb981020800W80 +W3W000WYWER8600_241W00K80G40uGIX00mLW394000N1H0GC0A40410TI8000a9m10200GY +W80v1m0000M1HZ0840WP2W0Slk1e00000a4KlE300029000002eW002GbuI0000A1H3gGd10 +i00_700yFLL1UggoYOcf5XFJB2m@MaPcX90@30@XF5030VLB2W@N4ymJ50_7JP2FLH1yW@nC +JCZPcM4pCj8p00000JL92W@1000Gb@y70000t@F6E6lnR0000y@@z000S000030K0J0l0c0C +HC1OY00m41W2E205uD0AmFmL0JWx8@06H00kZ0e041G1O2W2u7m5mRmF2JWV400ceK0C005m +4WBWfy0IG1000mLw80K0N00040E0K1O200e20m@@C0011000uHqv6u00006000003WNth0m4 +0GywQDgF3000rjU00y@lGJpR0400XNALfdsD00qF4RxFTSlHct6C2f100000081M2d1zDR04 +00gqyD00G20G00W0zDOnA3oZp00W04HFR0Wm3W_dVe9y4o1FXZ_DeXQ32axaDY89OFLIIrZ2 +pJ8tzDwu6ZVAD8IX4000GGG00G004mws64fG2008GpenW7rD8HU302008002enB300uqD@@3 +8040Ed@XPjP8GEL0040CJg1hZzmOS6CuE301G80808sJk450Q00000m41000000W40C3l100 +0Gk1@aynb8BS6W08000G20W8W00G04W200001G0080040010a0e0G80W008000G10A8_gX10 +8200G48G00020100KG10040000a00080040G08040000SA508G000008000G002442000080 +G0haBHRQ9KpU8@fR0010G08G0000000Wq4YV20W204094000040G00084WmyJWm00m@@6W00 +Wu8@4000G00110000000jh7mJ000G0484001C0NpBHKy6S3k4HgX108000004G0818004y_k +1W008YxtWtQC00000W0W0YG0080000440020u11e000100080X@_R0200YC3C01000uC600G +000GG8M4mWLgO8x1UYXxaFuDewz40009q6X4000uq100C4kJJqRGjh6Crl10G00W0a004100 +G02mAG6000GeqV3oYBXXzJ02200408WA@JW000006SB00100W306mv1G000XuHoQw9alh7jl +@GYO9y@V20001YvN2000GvcR0ul5WZr_fy@70024iOF30480YrpWxwJ8Bk4kpA1W000nmPG1 +_IG0000000Bx10aEtPOi0X8WYW4_M2x_R0040441200IG008800200fRD300812000a0020G +200022020G000000W21ODE3Iwt0Z400001000e@20WG0081mVCgSOeA8000000y002000200 +800m@@J003I00400I000roRmn@6G1288A_40020K3Y1d8R00p00K000a000Ujt00001000I2 +fGb8Ga0002W8000Af40W0001aI0004C120e40W0n4uC00c09b00I84G20G90004000WK20H0 +W40G9000W4AG0e4000100WIA1010000f4W00G4000A000W5g0W00001294000W400G4100a0 +G0e40000002GDpPGP@XK5_3a10G1004W00230Q01241080KH9mn0W0WWjED01A0Wm0W04G00 +05021010G10m090G0H0800001WG1G0G8G02P0OcK300mmLpf1O00500X0W00410W1ntx6a5d +1C000cyF4G820x@d000u8K09WG0GG4G400020G001X3815WH0GW0W004mH820100W0W10G26 +011800G001mHG8Y08000GX83GG01m0mHW0E03101G4W000800W82W0W2G0A000KP51Mm0080 +002020YW00We0m4Fr33Wx1011WzhbW40000122G0000ZAma0008GG4GW0110800404440041 +500041020H680100400142IX00Y0GW48W0W10110amuJ0O0fmD_6000WbI0000Wg020W8400 +0ADrWpyJ8BE3_@76qP1n00mNW8043W200Y0G7BA000_2S9mbWY10H0GdDA400z2TIWOW0a98 +20Y18We0I0DM0C0Gz5210G0W00040qW6210eD000WbFKG080WzN84000020XG0032804el24 +00000k805TU8W100osz100GLXlbGkR600@N4pPkOuR9a0N2oSHLfwYCd2G2M40@b8y0qqV20 +Q900000Wg0000000Gs0WUzp100u@x@6aOP200000mH0e0l1G1S1k2y6S7n5uE20mT405e80A +0N0KG2S6mFmF20WVKMS645W10k8kI1810e900WBm1WcWv0T0dH00g10000000ep0000N000k +07080k3u2O410uE00027t080C0Xlv1082WPFau@@A0mFLiuV5Uk80YOFX2sV00GCJ@_600uv +Y700mrtKDWB33@RGdl9aX53V0520000WgD0bv9HSyy0080yUV3W080Cll100G00008908009 +00mcn60G80PPV3A0t0808022000G000020CFS9000WuL10000Wa000004002010WG02y@F30 +G20ATVckfVuqU3000020G0ekR66f@400ISvdlnHlp00009s930G00_cl1RRRW08040W0GrxR +00W0402000W80cws00W0W0W20_PoWLrJOWV36Wt0WIC20000WX0000040024002WWQXQ9dvD +A8r008WWxzN100GmGVD0W000005G00WW400100W8qdC30408001G0000aB00000G02002t8R +GwRLK7c7FL@010040200G104400004K0500000005002G0GW0000W00XG100004W8aN0C00W +W0G008AW00000010G0204808W00Gu11W00000G800W8048000m4D4W00e010000800M80000 +G03404W0WEyD0204G204CYl1pjdGpzU4yk10W00G1002008u6S30800Eel100W0180000201 +W00H5y6020000L110002010002000000200W100240000W20e0G2G100WWF0010I00008000 +e0PyR0140acuJOsT3kTAXQf8PTU30100W00004G0LRm6yYh1xuQmlz60010004A000K0G00W +0W000012009004C4001000M01VAPmiy600872100008H0000800K2G000W0208o_4G000KYO +2ZYZHxGXaKV2HhP00W000G140W4000G00WKW00W010024W008W400dasWYqCWG02000WWjxD +0Gd2mTz6ysl1W000110GiJj1xMHoUvLK5U2tfd0YI0W4zP00002G01001200420g2q0e4000 +1W80200WWW0HW000200W98C00W0100OA50W0o8W08000K1i10GG20m00aoS83yHICbC0004X +100000080W000081_yFX_@DuvV30G010WWW0010OX66izP200sMNgXXE@DeDQFI4t30002vu +nGozCShU2joR0040YVsD0G01000004WG004W8010002002aG0G3z6iwe1WwT0YztWGZVOR_S +0W0YK0U2XzRm6y6020002004W0000020054088800501G8000e01G031W803aH02LXa025g0 +GA0W06800424001W0H002H00005q0W4A2W0K004020G0000200620e0ewNt0002mFtUiCV2Z +mPWf0200002g004KC0020000080200Y1002A00G904442601W01000G040G080400G1100n0 +A631080KI00W000100024000mo600004G1G8G80f3Q0I0008X009Xx100020e00WG00_@l20 +W800G9b0000024L210014b0W4tC8yR30WI00I00000e4080We0C00c14b000800GPlP0WLI9 +0008400X02000040WI0008L2000W02G9X8200000K2a0000004A10000000W204cF64e4IW0 +00W010uNnAo1t0P1GOCW0We0060K088nj40W0AW0000090008G480009WR00oW008208420G +W8020020140004010mG00W004004000WMkA000G084m0000004210SVJ800WW00080mW0000 +GGqzLO08YWY800OA80G0W30eW203W0WdW005000600G1G0G0WW00m8800c04O0GYG00EWOO0 +20W0GXX100800J0020a00G00y0K00008K0G000K10W9040005EE0OG0G089e8Y10000O2000 +K02G000oVAXkzt0G10G6@L008100K240W088042088080Y00208W5G100402G0Y802AH000Y +SDe1Wg00tPr00020AG4088WH0WA0Y00W0H00WpRD088GW0000GI3G0100G200jYl1W0HGkrt +WrwJ87SCsdaXtzP00qP2210GlW80HWRG2S6W21050iR2X00S0008420AO3XWWzNeW5W30sVH +800E0804X005MW0GOtBKO3m1WLl84004031WG0WIJ848e@2000UrIfB050czY000C0O48210 +AeXGWm_B8G2WVIr30Gu10000q000aol4HWR0ufILgYPc_7ymj8uXBH00uyV300ei300gUhz4 +IEp00hE0000@e20000000Y0W8y3000W8000CCx_F100N60F00000000CG4_00Ges2100EA1E +30U1Ud0N2Au00YTp00uDmAmFmT00Wx000m1000l100S1E0y6y3m5u7a2G2000@0E0O0i3y3u +d00mF000000WvuJ000S100y3O0uDmFmFWR000@000m00009181UC8800G4F200F4GHuj0000 +2G0000yra7@J00Wo_NS6000O70000tT00W6V00bz0u@@Gm@@XGy00eg30WWyDm8L7WxE0000 +0W000G1A0WaJTH7SPmmlL4Rc1b@Ani@Cay@300e@R2_XXzDeLn4gtcaI_V00W02AH00m0400 +4G001W00G0WwbV30800zTk10080100020e0us63oxc100201HRGog6CUk1W6A0clpWjaJeuO +6gttWk2W10048000uiaVuEv4_u@XuTz00W00000UZ200R9CpCyU0KGGwzN3008G0080e5I3k +6s0W004DxP0010AW080ldRmk260001000080W100040VHm000ZapkDOBz4oMmWRvP0W01G0j +g0000400A40100W0284400G000040G40002800aD_D020G20008W4W0nrR00008XA0200020 +0K0002e200W00900000040G06SF10C708100YWt00200000100WG00100W0G01000W000000 +0H004I028u903YjN2080090d000W00C80204050010WG442W0W0020WW00c1a000A00aeqmG +021e00G1m2G0HeW8W8W0K98HC300e201084920010304IKO4001WAP01000eC214G10G0000 +03T024OK19u00C0200G20ZI5e654C000m01G00m0C440428kAd105G00081O200G0X0XG140 +0480050GcHq00044080018000W02H0000W0G0K101008WG2E2Clc1K00W0iW002004We0002 +122101O0O45W4022004018C10481G00801W1002GO4WH0080182LG000005201K00O00000K +408465G8X0W40100G00144042C610020004W40G00G4jl1400H8480002O000G020Y800024 +000kNt000010a0080001020W0G8010WZ2AC01008100G200401001WY00008200m21644002 +0020e000I0W0G0WWW201091H1100W8081080G10G10g80000200802GUlt000000J8G0200U +dj1W800WQ0o0500002029010022W8201040mG00XX0G00100YQpD00G0200040030tvRmqT6 +a_l1800000G8_zk1vUb01W00000Y00100W000G01fEU3G000G4000000Ioy6001920008G00 +10802nypGux60H00yti4s_t010000W4008Y000000Q00000W4W80OG8G044W0aH9900WW00C +00W80G2100Y0W012007OO00004G0C0000000Ge10W8W00000G00W40020300114000200040 +W48G00900B80cjtWY_D00J24000O04W000821840000G2940004m8W0G0010000X00W40H81 +A2010m__DuI03kMV3G400ttp0000aCxCuz@4A@pWjnJOhU308W0z2P2lxR0040W6@J0Gd3GO +_9000W080580W0WCZD00200280006000010W0W0igV2HsBntrC004000Y0m7@C04000G00Gt +e60W108iV3000411000400000800420G0000040shl1Zid002000W00000e89W9CgT2TZQ00 +G4WBnC0O00nOS600W4OdV304104Dy65iR0285WKaDWW004418GO002240010g4218W12W0W0 +140G02K00G28022001008000a600H0X0GGK8W8C0012G100Z1G10024W000400C000210000 +TCG66404W0000OG4W0G641Gn802eaGA8300200K10eK00g21AW004XGP810AW0001100200m +00G0mKuF4qG2000W40YY8A440Y0404900000800OGwft0100WW02200W0GG50401010Z0082 +802K00110090CW128000242808Y20W0W800Wm0100Wemu@60KR0000I00X00G40W00000We0 +0229G08G00GcA00006840WWWGe2c12B0G104010002TrdmVcCSOV20808400G000WWI01000 +8G0e410WWe40401G0W000e4WW4H084WK2000G0000b08MS302Y08XGKgo23I1m00f40G4049 +WI000CZG00e4000Ch0049aR0400H0e4a00W0009A1000002e4b000000WK20210W080b0080 +000KGXnyDG900GCSC00200025Ihx900W801Y050W1040400044001o0Wm00m4G00C00OG010 +G11W900Y0500e0002880600X8Y00e0WX1418W802A00X040W10m04G00A00GH0040000xK00 +0e00G2G002003841Ae000100G00nob008W0A0W0W000I1mW6@DODV3YXZ10100m00W0000G0 +4W04m2e8W0000ZW0W0000GO90GK12600e00GW0o4W408G001W0CW0H1046G8M0800440O0K1 +009C4W08e4i0m200L0006GW0C0802004Xe5He0211000w40mH4001Y008G0W862011G04G88 +067e000WG0220008008O06G20GK0XK0i10e000048_rx3L_R04404H006002040048I40000 +000HG4e008G048180G0BG440081W80840Le0W00GY011400200Y0n0080W0G40X2gar0G000 +040H000W08g4G208mZg6uv410400088G8G000GX08X4100X2500001X0W20GY50044H088e0 +H00f02G8_9G080eWMC020102I010al2W00S0HC8G20g8H00WLJW3140GOu6e00GCCS3y2TMW +OW0CMy4GdD5300V1T2GOYu60W408MS30uB000Ot3TsGS2v6GW21WW0G3R8648@25y0S8YbBX +ivCmB4O00100D0001@R00A0000G2@@p0W0W250000j1000000WVK10000lEwV0000egg5I4F +10yFLgYPCbvYOAp5PMuBoCcN40@3E0_dggmCuXRHggoYCNLsu6WAuX70_pCCpSHKLrYO6000 +ziP6EU2egA0XPc920J0ecU3yJ50uk300c020C30Z3aL105000u200e3mXlPW300O51G1XXR0 +k0kWmmh8HS6K0N0a8k1AoFmp6t00000ix80KWt0aD73nozGsS600060008Osj60a141000GC +SC00C000G0E30e5200063Ww530000r10000W90000udA0uBL0mT7004ndV0hE00eYs_DmF00 +mOt6m@@zZAu3eg308P70Y65WTj00JuBp18GE600KW000kp100000mV@300O7ei500000G100 +00W0kx00yr4W8U0vk300CG000c0W@@3000WlfxZ10mCWbtUuRx4omrW_jDOJU6oytWeYJ000 +2nS09KOC301U0628XAvgOspAYtt3G000G0280W4000W0000XGHu602W0000440000010W002 +004W0SBU2000802406Uc10000ZZA100400160000GnH80uMS3008004G00801PNQ6000020G +0q7U9CYc1NPdmj_C4sS2BtToqj9qtF3X_Rmf@I080000Wpr_y9iWk1p@Rm@@LyCd7Rcp0022 +4010A000O000G110000001H01A000Ge00WAooWorD0GG0oOS608800W00OTq60G0Xe4V3000 +G088040000055WYqD00W0200420014W00Godt0G00G9kRmDWCKrT2zqdmmw9ajl10G2000W0 +W103080488008000f042G4A0WW10028O1q_36008240G4GdT60A80G00H0K08WGHD0W00020 +6WJXDe0V3000GvT00O4S34280S5k1@WR0200G0e019PQ004W0008Y610000W00G0WWW00Y00 +0G0AA0400102G0W0006WG00010200040WG08OX00HG15W002034WR1J0W00CGH14800020K0 +W1W0200bI018CG01K18W00GGG9201GO80M9080G050e42000400WeWGG402002AG85000roA +1840iK000a00Gm0aH0b40WaeG0K6W28m032044Wgee002Z08C8KOG810096W0X4WC80B0000 +0825200G8Yq1j1000001C02m0040O0800bO00Wm02B800eWGG0108W00W140WW000XA002e1 +34040C0W0W0000XAX00A000CG0WG0000W42O0K10iE14R014080210G0Y0880000G00I000O +YK1020GYW008GGW02840WO0082G0I001004X0801W00400000H00181880C0100003021110 +2000a4W0000W00G00022100m000W010200004010023100WW0W4000880020000100W00OW0 +02m88080001000Y4004WH000A02G0C048002O8Y2G0022W0000G010588020010000e00800 +G802WG080004r31040GG0000200110H0200Y0G10860G0980104I0r8m00Gg02WAYW0034G3 +C02Y0WG80W820041014WG6A480004W00W0008052G02W010H044WY010G400W0400000139Q +00W02G2100100G4000G80G0Wan9U6aml120000001004W00242001WsxD8DF3W0WGW300000 +mbm0G00W008m0G00240020GG0Y0310G4I0000000801001001m000002040a00010C196ie1 +20G00aW00500ugC3UEo0G000W0G00I0000009oV300022G0e4041mc_6G00000H0e0WG000X +0vIRmty908100808mz@6C@I2vMRWXm10cXW8004W00W1000101K00000001010002804200W +21000202HaW_DWGI0000000W84040040080004000W0H000000600010WW2GC00u2c404400 +0880G040008000090100X0W0C533DpRG5X64EN20084A_FXeFC00008w1000184G00800WK0 +G00Qyy40202020eOzJ308009G20H0e00000iTwDexg40200ySd1WK080000821286_7kmt02 +0G8GG0m0001K2b10800oaZXjkD0000809002000400000002G80vZF300O2DjW1010200G00 +2W00G00102a00G9W4060Mst000W000800G81GGG0000000GWYBoD0080qx@6W20G3W04GB@6 +0008I800000081G4G0G40848304G01GW622GK4020G02HXW2040G001208000100G80HTQ00 +4104G506WAGm00We60400004002002KG24eX18000qdb2IY8WGb26AW16WG04GOW4XA0HG08 +0aW0E0Y21W00eW000406e0Ym200OG09XGGLaG0002E2I8G5HKWI4k0G010O18200001C1W06 +1WK80e00821W4GG82x_t0002000K2007280116GG8aG9K00084Y0a0C31GW6W00300WW00W3 +@D04048000O080Wv@P0010040200G200008000WNl0GX01508G0C010M0CWX00CG02q0C0dG +G0GA20H5XGeWO0OW0W2400W9H1aI8XG60WWAm4W0G0uSU305Y000W000331G140Y2080142K +J4G004100Xe0X0000004K20810c880b8400002KI9Y000G805O200020OWI4000002Af4000 +0WeXI0WG08Y0We40G0000YIK2I00004H900000120K2000Wx0000000AH98100020b820000 +0GG901000W5bK2W00001Gf1@DWI0000009A9aP0000100Y00C0408g4I00WzyCe8d4Ibp000 +06d1Q0000128008004000GW02000085O108004GQ4220820000801Y00080G40W80004Y5d1 +00010G400X00W0000qx1010000I01haO00K010e0880Y20000W02q00001580200W8003200 +000WW80300m1@680800044440801002d@R0H0G000X08m8012200004000K001M04W10Q051 +G00Y3GM4XWO4A0E00108Wu82W0WS1OEG06WWWi2G3028000W2G_et003840004W1m0m9Y140 +8C001e8000yYQ0O02441M00W0WM02Y00C1O08000O0G0908W5W50202Y4W320W40mWH8N004 +07AYe00000GC2m2O0E41W0iGR28010WGW1W800014WOnz60002420W0008K00GG012W0A08q +he1080080202e40109G000eWiED000W8001200Y5I400G01M000W008000404W0H2011000y +700040G210W41H200G2H40G2801060480001441840009808C00G2404W0KA810404Y84002 +092Wafl1W400001041W120200000Y40e09000GR0800E0840W005sWGG8tBKO3W10Sl04006 +021Y00W0R8488z2AC1K0m_B420G10XWG80eW140IYuF4Bk1U1000LxKm6m10vl04007042YG +0W2Rm98ix5AC1e0GUg06aGk101zNG19W21sVXG000884400008XIG0qA4MUZ1FiR00W00002 +uM1000000udA0G5@u7LOITZ10000Wli10lQ40KWpwEXl0000uk3vIBHOu6C203KHT0Y5t000 +0WGm4000W00Ksz5mgxE700815000000KT0@e2005e0wl@100u3Or200g40YW0000K0g@FG1b +TSt@1FaRWx00000000uB0u@@_oa@fIt1ml@3WT6000m000e3u0mRG7WEWVGEu6000q400e3m +1GJWVWV0T0023t00m500mFm10NW76_3Pln0000000AIvYR0T07W4uI8G03I58XK0O00_1E0m +0S7e3W200mT0008000WW000Cy00K1O0C3u200u6SES20700gwd1tT00EuE0000k3yO0000uE +m1e_F@D000yb900WK@V008YF0000G4H0d@R0Oc9R1W@@0uk304mg300y7WL70yxF0y30000m +0yr4W30000cL0GhV6u200cw1Sd3i3Hu3H4@@p00W7600Axyr4p0000Wgw3m@0000W0WFeDeq +iGYXxXOKD8tV9CF0042t6PXJoWvF0G9000G008W0Wc_D00G080X01G080LkQ080020050fIR +GhN6ivl1W10e008G0G00O5R30X40aWk10C0000ur5_V2l2O0004aMpD0WG0GMs6yeU2n@Rmm +P9K8f1bgp0011G000W020GkcbXImb8Ik7oCdX9EPuu@40sc049U5dh3Jnk9Kkj1018GQMt00 +008W00WW0G0saa10040020010G04800uCJ6Czj1fnR0GW0808A000001081y8l10021000Gg +J008TU3oht0010W@oR0804awsD0000ngx6CmT2txR0GW0W5_DeRS3_Rt0G000XrP042000m0 +0000000I8W440uTS3000We80083G3Ekt04101bBR0WeGXPaD02800210WzQCuyU300eJ1400 +008801201008008GKoUs00WG0K11KK0M00GO0G4W2W0GW008000AaY000000aKG80m400001 +040080WICsWFbD00WW000G14WW026a000382KQ004W28025410090G48828500H0X00K04H0 +446W00040028W0GO20AW449KK84000213XGC8W2010m8W02I2804Y29802H00000UP011WGA +K41G815e004GW88012AG18g058W14000mG0H0000020WW28000I014X02feX6410WW04G010 +W010W04020e00GG188406001WW2000000GC080mH1n00012Y0o0020084CJ030010W1CG105 +00oeY00K0840028000typ0a800WO2GCK4S00W8091000YA008m408Y8C010024G008000006 +r052W05600G80O00000W5G1018G0000uGW47088L24000500400WGW800200GGG101220441 +0003000W08W04WW00000G0220G800000W10WsQm0810000120Y8000005G000e0000200001 +8sPt00G00m280Ets021240G200G00080O040200n220002tbO00GI00218040000SK000004 +GC82e01m014WW04018W0G1r00008WG000A49W00044CG0K00001218A2A151e810K4C4G120 +0G00000208W200011800C0K1k1X@d010000202@DBH306SjT2m000ImE10180JfR0W000014 +0HYR00000G0c0mW00805002000100140WH00050021006J01W4481W0W00480140m2008W0z +kl10G24002002050000G9s6001010820cn00200080W0004020002404GN@Fqro3nwQGYo90 +W0600W4000GeaYC00080000aZzDmx09Gz560111K020040080G0000c0044080021000100G +001190004480G04W4001200W8001G00000G0400000G81H040GG0a0000086NtWIFC8_V3ku +rWlkJeLT3W1000Wm2evV30008ClX1FzRG70C0W400001000EZVtDW00090G0G001002080W4 +0KGk1080a000412W1G040040004040G00G00WWa_k1010WX014C1k10040080aqzj10W200G +G04eG51lR0880WqnJOnM6MqnWrBJ08G0000G080000uR0MoqWhmD0600010002140W010014 +000W0W10000000G00Y0018GW002Y0W0020080a280203aR08G0WGvD0000Mvm60100i7P3E8 +qWnpD8US30G0000W00211010G02000DwRmpy6800240WW0001A000402WG02G2100AP6V382 +Y4108K2008015Q088018OG1G0452q8208A18WmW3050eKGmH1a4G84250900800G0O00WWf8 +005000240GG0M1YY08C012002141G8I0G6422820Y0G0o2000H010Y0aud1060010W0090Gu +8V300WG000G68G1005110m40XCR00000882W240G003018W8ioB30000XL20000U10mW8808 +HG4OG008024K128G12b01121O504X010GQ0Y206A08XWAH28XQ48UeIXAYW0d0A0W1Y04B98 +020WG0W010W0B0Oq02m0W2996S00400H0000G04bK200We02I900002qi4e4800W8IXIA190 +G422f4000G0PM8A1000G4Ge0b00086G9K200003c14b0000410KI9000Y0e4b08001G4GWI0 +000W4002G0IG9b000002HK2H0400824A1Y00000eaI00WG0W8A100H00Y0YI0O0000CAH908 +000005010000a0G92120000WKgtV342088102W2Y0000204G000m0G031A0008PMS30A04W0 +00W10X12K000G000W05000W2008000O0G0a000004200GW2000GH014000C000IWCK002K40 +4000W0h00000104GW25zd002W02000noP000004e04e000GA100000084G05020YG8020000 +9000204ALE3c_t0AW800G10O014Z0u00286422m84445091B01GKWb0G00OHWW0043OXX028 +_0u5G8AHH1G100e8G05106iW00887Hu2200JW82WH00024006WQ00mC150w0401000mQ0098 +GW040m41000kG0040E0W0GKC509G2W188e002G0808W011H040WIG00rWI8G4JWO4F05G830 +4Y4V_R00O02000W0K00Y_t04G0G802W00a0G08W2A000G204W000280G09KW02001a001000 +090W00008W08IiZi18G000528000009M60I0000Gn10G200G0OHW001b0GW000006U00GGeG +20000A49UZ4W00W0IW0aWG1001028g00I20001GI0XHa004G90W00002200G08YW8qlk1ZxR +002W00Z080002055paxc148004ZG0Wo00GCe@2A3G41m_B420HI181i@2b2Ga0GQ3010H200 +H8KA09Ga8OFAW7000mHPA99G03YXp0KO150XzNGXDW30sVXG0080864010bCXHG0_BKm4G50 +vl04000142200W8Im880v5A00081SUt60400044G00GCXskt000h_3wFuk30O5E6000@e20G +4_00Cr100m3KspkR000HNg00mK7000WV_xV00m@G4l0ukV1uF0000040mg3W@V40KzF00800 +MT0yNL00Ax0G4c10mgxtqS9ex0yt@0000e2O0300u1ei50UuH9UE000uj85mFWBWc0@4@0_9 +H2yJYa0d491yEI2u7u4mRmJ1u1w0k0y6qHY2O320000YvJ0f0U300y3u0uTYSF00@070K1k3 +q1Sd00u9YR0d100s1E0K4y3e3W100mF2004000mO0006040g0S1g0m000e32W0C100eI0KLL +V1m@0mVcfIL11km3YPL540_F8cnCL0uVm3F5W7G5pC3ymL5LL540yF8gMLGW7_WmCpK1W@nK +cCJbg22JP64p00008NL11Uu3W@@J5WL7GL30W2C000000ew0yt@1Wl@14Og3@@m7mg50WLB0 +4hM0_@F000GK@rt0G5@1Hy10x@30@v70@@F0WoEukx0Waz@G8_0ut@1mUbQCqrU5T8zGO@6K +5U2zzdGju90089PnQF0G004Sz99yR0000I0020l@O0O00e5pPepS3020W0000fs830840aag +1zzR0W000020WW00W6TBXK@D0yC3Gau6aQU25tn0800WcED8vx7_8tWKxh00m0m4uFS3_3Bp +oGZwISnc1Fqo0000Sk200LWl100WW8wOeQVI008024G024002006W_sVe8T308000G00zRT3 +ID8XbRD8B_402W008W08u0300W6MTl1W00OEFtWCTPeaN3oG8XnuPOXF3oil28W000510W04 +0Wu000GG000020H000000W00450WWA00000W20WS_J005G440402488W2W00540aFb1phaGg +o60EnH8NS3UPt00YG0000050GW0042001084mW40WG0000012014ci12010W008ark108000 +0800842G0020000880040840WW002K000W50200500030040X0280G6W0WGW0A0W00012GA4 +0H00D208G000W020X08010e0G4G51020G4001HG0G11KW88X40eQ001W21W04WY82000I010 +8044I48e4G4085W408400Ka0808Y80002034204WaK8GW00GC880404014G06G14W028I004 +a0204G00QwtWe1D00W0000W00008G0XG0048GX004m020W006048K003410014_d1G0Ga00o +0aEj1000W4CWC0800062Y0WG44300Y000W1G80A0KG002004W2000K0GCG0004s11011G1GC +0G0G0W40G0W00008244G2I00050A0O0KWOcb0W40WG0e002000GG00GWI00800W041aZF3G0 +0000400m00001W40240011002800100G840y0D3008G000X200g002c20G0000XO004Gqne1 +00G1WA4008Q008000W1W4800We00G0040270000K0nz_60Sg00000880060W0GW0800b080A +0W000210G000280G08000W0000Y200101010W03G008G0K40088W0014mrt60A40K0G0mW79 +008G040810220G00002080W10008W0040m3_C0PG0WG00mQN60G800WW81G8GG00W0004004 +WO00G0unM3cEq0000Kc343A_t000c004080001W8800110GS_900G0W022mddCKn26jxR010 +qeKoD008100000W100800001W0G001eF13Ufp00040W02W020000c1evV3G2W000Y08m@4G0 +G418002W000022000OG00W0k@t000GGG008c9m0aW021tPG9eIyEW1@YY100W01010W400wr +BXqpD8mV30020CmP20020l_t0100W002040400200G0G0mXR600000W800G000mKD0010088 +000a0G000O4020XpsD0011mUy6qul100G1VELYhRm0002a400XuqDeWz4kYB100G0000YW10 +0Cpk10120000G00011080nDW9a3X100G000H00000oq000002XAsD00G81010210400a4004 +40048084x4_IF10G10TcR000WXG4IOJT68W0rW0YB0G00004100020G400W200G0G0GG0000 +041000204W101Y030070e000014406Ae0aA8m2W0W5610W0208u00G02WG048014H08004Y0 +200W1R060W088C014aWH40WAIL258aP080LK2OG18n4Ym0000G10010G020nb8o0000G040Y +HaYXG00880g0O540W8900008280G1W00B00W4010G004W008006G100O0G000004KW00WWG0 +00G0W08a022W020O180028000004004000eG0Y0G000003i0GK40450004008G08W0020gGt +0280A004G080IX00200C40000nntP001000100C410f2L10000Afa800001WI0000GK0We4G +W0W4tCOrR30001axj10G9bG000G01K2008mxE646U2WG9Y0000G00K20001r1000002HYRmA +u6000K2001Gq0600H0WI000G80WmmDusV3000Aqah7fVR00CH140000m0G001241E30000e0 +80Epk18W0n000W0424Pps423t0000WBlP0080000Ye0W000014W05000A002000000X0W000 +9004_M2RvRG_4F0040OEuA000Y010006G000G200n044W0441GG040O0G113000008e8400W +G142m0e0W1W0odX600081180001W0G13HO00801eW8A010400C002BW04422000TP020G44A +80CW2P0H0210m8Q08880E88002Y801C8X0W0e900G0aG1090PtV6000014002A10mlnL0Gi0 +W4GX00G0011402340W0W2000e0G04HiY601H2000080e4800W00010W0200H0X20100H0200 +600008058G00Ga80Y400K0GndNC0N8080H048Y0W08441008001800W4W88H00002@4RW00A +G08820K00Y_t0001GpyQ04H1aPah82S3840030A19ox4ISp000A2844X005cWGGOtBKO0010 +Sl040070A0YG0W29008iRIsR640d1PZR0oV1000knvYRG2S6080eW1402mVXYmmJ0nW840em +2402wU1006yE100008G202WG20000000J00eW0WdBYltT0xk0WehPupw7000@e200e103E3F +10S7SjNB1WP3WmgJ000C1tT00_Q20_o1000W1udAS7000Xu10WbhQ92y4Yy_XOtC0NWVGut9 +000m000WHsR90u208xj40WtWx0T0FRS3000Gug3082y4S06W76k4XZRmLw9000a40000G60W +gjnW30yZA0000uE0FWB10_f200m4FhRWl000tT00_f2000y00W60000uE70exZqDm400Cr10 +0J00000mg5mN000Og9UT3mklW2K00W@0000W8U1eF000Hy1mT700GPVA03sSd1i@F0000krV +00a86CZ14pXy90T00Q1jAE8udDjJO0z4cgt0H000WC000800SlM23eRGDn64YU25tp000MH0 +810BflHCACaqT27AOp1Ud4sk4Wt30MRWgQuJ000HIx@C00I000WIm9y6SZj1XmP0008WoqDO +219000mWI0GA1_DwsxXYp9PPG3k2tWezJ001WoKJ6G01100000L0000008VyR000HG00W2nl +P0000eBwC8gV30W0100G0000ZMT@90051OBS3UVcXBVD00800400ai7E102G0G8G0a800890 +1C000G0100001800044008404G08W1X00000090H00400014041820102W0YI0800O840800 +00010202W0W4G0WI480004000Wt90Y_t0e000000G4WW00O101908000GedOD0004000WW7q +DuSVI0001014W0W041008G3101VjR08000141000200044202H00C0G@@9020W2W20261K00 +W804WG00000ayi1040205W000001000cm100100000090001000K000GIXM900C0G002Gq06 +GW000GW0Gdzdymd1JlRGfy60e0020100020O4028NWPW0G04GW0020104024000000u00000 +100GG02004000qPk1GW440G0000eEeOB608011080uB4348000000G100GrpCSxn94110Yky +1W003HIm0004mhkPuEw44004Czl40MN0sRqZuGQf_V30G0WqmX4N4PmYuCyef1JWQm0_6028 +04W0W0001WYzD00200010000GuE600Etq00200Ffdm60600W0S8z4oHPc6@DOvECMqy10900 +X8y00W0WZnD00GATN66Clv3f0aGb9CqGA95hRGVd9qcm39nd0I000008040000002rTk1tsR +GGD9KWk1HeR0WS7WbvJuM138W0I45e1P1ymldjK1F3202000002021umX4olt00120000GQ_ +q00201W00808050421uOT30800001008000000A9006fIc0100WrvD08e00040WHsD8I1O08 +0001EGu_V308204MV22210UtF1004Y0401g9n0400X000002Y0W0G004W00080002000W000 +0G0K_X100SsR3C10G0001008C12G200W402Ghj6WA0000008200ulPL100850KI941WG882b +08800X40X2X000420Af40WIg01hI4000O0YGe400GA20WIKY8b00a5G9080W8200K2008500 +G9bGaG0824K20W0W0W00A1000QfG0WG000bK21A1W4aG94G0cAHA0e408a5W140080WI4000 +HW800qr3jW02000O04G90220W0BgR0C0W040000161G0G0001D004e000140G010W0082e40 +051W10002001W0008W0HW10WA020W00W901W0000ae100W100W020210G8G908020WXnP000 +a0400808CeG0G0001086iA_Yk2402801Zu40m200W0320O0G2W800m1WYG001H18YY2q44O8 +G61310W4YW26W118W0GY04001I8M0We0W801WO10G0OG00C1Wl0ZW0400080GIW1G000mgWI +O112G06W0G44C0IGW0M8W0A02CG6400140K0002Y441000A0G040mBkd0002ixV38040Ga40 +02012800002K1W4f281000210GG080410C900a0048108I200a002040081W80e000000a80 +04126000W220000940808000068G00G25G44080100180000a0am01a100A1W4200GW48G44 +100000PkNL00b1a3k1480043G0Wo00G4WsGOuC090eM0141MVXUaOG00y5410n0eG0G40qPX +Y00GlGd98400z2Y0WG0A40820wCe000uB0008aBTUWO00qB820Y1e00W80epc2p28X01C0W0 +G3900aMmD88CX000@30000cPk00gQH0y@YW7Ug0m@KfAc1W@B20@NavK0C0yK1FufgA@JLLM +aggi80000eOBBW4yF0_3UggoY0ul5XlABgggMaPcH50@30@10LLbOYqg000E97S30k0Q2yJa +1ud49G69ommbmPHUWpWy0U3G1y3y2uDu7XBmF20WV40Au80K0N0e0@0U1Sb2G2A0000sk71W +2y605m5mBmRWVaVP1yW2y6S7X0uE20WBpu4000008pWegg1XPcn40@JbgW7SX740yF8ubPG0 +u@WKbgOoCc1mVg2W@220@5agXB8LL50000m@fYgsV0Yu3GNxFmI00epT9IxhY9ukgrL3sl_X +nnP00W_H2THTMk11yRmit60X80upy4ojAXLosOly70pH0al39RwbMRVcbYk1zmRGWv60W04Q +zz4AmBX7oVOFq7clqWB@D00GULsIayKWD4020EMlYKYV0080082AW_gU80V60GA0KBQ2hsRm +rV6K4V2p@9HrzIycF3toR01000008004400Y0080G0OFF302e00W0818102W000W0O0000H0 +0000410OLV30G000000X0020520X0ZVGs00Gw2RyqHElzR0000200010402g@F1201440200 +80GiqS2000400029000m00000040W0004W00kVd100UFb6zGa2XK5e7d@R04200000840888 +001iYT200Ges5FXtvDGW0000W0100000C006_F10C00lt@0uR4WC_VO6iGAgebmas0001001 +0W3@Deb46__@1000Kg304QwyA9000Vzd00G0Xw_J000WIHo6ifl1P@RGTA60008OyV300O0K +zV20OylZ45iosQfmx4AJd1Wv10Rd2M6@60WG0egR3ATF12200pdA1800001G0Xu_Wj00WttV +00Y0GE18X0000104GZu68410Ooq40001iSk1Pkm00W000m0000280040izE300cBUv3Za7Gg +2U3Mic10e0000A000101021vC_4m0000800u0T3W0000K00uG@40190ib@35zW4400WE@DuD +S3WGG0H80000400b000000YWG100000005K200000WG90000CZ00e4080000X2AHKm2FWV00 +e0y7oqHYtUo14A0004XWYFD004m05000062100040W10Sml1VxR0W80WEFDuDy4Eyd1002qf +cqoMpg00O0000002E200m020G010c00060G008W020G0UW00e00W8800X001020060Gm8000 +3GG01m0G6zLW1Hy_0Wo0WFUVOrOa0WG0a7i10200WGX0090000008008840000G40E@t00W8 +0G004000400W0y929IS91B2005gp0000ah@DuVvY040mW0200ehG910408RY000K0008010A +C1X0Gg6em4020eQ080080420W0076G0G0@5KO0W00q60400yyE300ClGW00M@U24000000W0 +9H0O8wb0qI10WP2u3T3000KbrU2XXRGJ@F004HCkV90pS04CZM003WH40Wv000m9000C000C +160u2O283u700G68CS3000o0S0m083WHYuC0080VxR6000G1_108Ye400J00000kCZYAvF10 +0WgjehYg3WT@300xz@00WWqloaE68LY5Ya8QV8LaA000meN00eGTUUZxs85o9rMCYKudfnt8 +XS3IX9aEt310002w00Wkylg3N3W002Kql1LgPG3x6yCl1nvRGwy6G0020088ma_L00uXCDvA +6QgeAzPu@V3000Oinl4LnRmq@R0cG1Om_hYXsWX@J0014mt_FaMD300100004S403f@d0000 +S5200frNnjG8DSXG00clJyCgjyDeOy72@EXf@J8506YvcX1ZbG4U1mdeKT_C3px1Jb@F000W +px00GZ2Kzck10004400WCJA3lPRGktCKzT800k73RrfMlDuw_40W00EVV2XVR0001W6xD850 +6sUp30y60VwHLkt600040080GHs9G000uGV3001045m3r9oGoyICax357B481G9000G02WI0 +WC0G90040800002oK0C0080W800eYwC85W7spF1000GlV@000IYSUT200e008000G0100G00 +404G4D0GHX00200WK0CGH00A08G400W10002Y2m040G0f0OGwz90028W8000Y00Wn@J0GI3m +JmH12000K00080007400E0010W80900W00G22G00A000101W1000400OA00G000GGK00XWrl +d0W8000100zf@0000SN200D7xa010200048088000010H0200a00W8000100GG0004400W00 +082000200680W00GQKrWWzC0Y00GjQ6yb@300_EYOs9000S0W000e8820Y1G00W80eJ2100W +C1E0I1m040G000H0070100059506080m00000W0010000WB2GV6@0Ga5WjeTA2S3mCpK1W@n +Kc@3kmN4JPk80vWdW@1FSmJLLM4pCj8yL56U2mCJ0WPc96eq6w100Ajs941G1O2W2m4m5mRW +92JWV400c80K0Hf0O0WBW90J4J0c80I1u1410m9POmq3601W1e@R600eIcksyd7CVp3@FBet +7nRGLyC000d8JVmEMFXcvJ8SU6gdN2Y008l@@0eZ5W6dU8FihQHlYMt91000Yh10000045mF +JM12rxV5G8200800CvE300iQsv7owvb04g3mkd7svF600WmD300aomChThrf@I00OgB9LH17 +C0CbEF@4kqWu6KhH5y500gX@G0880@_N100cqt@b8WJ32OhecNK1WH00402WBmh0KV1mCCOK +iFII0002Oa4W2005jpGafCuL008CSgo@tWpiD8u2I4W000061hKzA00iO6fGNNpVos260410 +uKzA0tQ0yYl4XXNqIv6W0108oTF0080000420G0000XTY010000Glf@1000qC400YzzXmmTw +eQERotWtlPOkVCm400W9W9000Jm0W90O00uyV60D80y503XXJryS@7lt@l3_VxY@FzFm0mNx +Zpy@tG@lDr@NZz@qS@@Cu@BJ_@ne@FCx@@2@@kq@VB_@po@@@@@@@@@@@@@_J@FVTj00G8Kt +_FvyxqVrLaKWAhDxKwk@tlVT0lR0gkugy_H200uaL10WJm7hjVU0Wes5ljeW720IANbzICOX +4U6NO6000m2500U@t600W0RyZna@9C3V2x_pG9x6avV8hod00WGoar55y61GX_HbqV5z_R0G +00WoQW1000H__6CLZAVrOGiE9qyl75wi10W0Wy0E100yItFv0010eMY4_@FXr@Veb43I1uXf +0geqaD0I30i_lDDtZHBGF80008xdSo3m0000yA000Ir@@KXKNg00m@@@aVH8@@@VWKAoC00u +@VU0W00y@FO00yW_ZwJ0000WFK0_@NeRPO0006G204q1030C00J1WYe0O8FWD000G07008Gg +Jo7G2108002A0Z6u11I0882a0100WW8H80004824X0W4OWf0GHK060000W840GU0R0000KI0 +0m@@aaFG52462000W4Dm3Wa804a890000GG220000I49804918J1WYe0C00000110Wy0su@V +Lo7mZe1Ou@@@@@@@@@DUBhA_@F1WV70lnuHW0UaKmO000uT3004db4hUAte3DMyZ1F@q2e70 +W00jPJeM2M3Zg8h88d7000W4vw9lNyJkigKfa400Sq@@t64001vPg2000XiRJep93sxg5GC2 +0@YKtM8g000WW300mOml1000yF49_@V30G6d@@FsYgC0100124Wm@@j0Y71u@@q0GG0y@lD0 +300ok9DG0000800002W8W00u@VL00mAz@lP00G0xzm000040G006sf50480d1P600G0I1000 +00085100018AKEL000GpT00e1Sp008WaGi10I100200SHiA00Qd_@VC0u00800404000C080 +J180X008K08O@@h28W6W@@73G40100004W00880000084aIB00084F00y@FO000A0X010m60 +202400Y080G198400pPL500Cf@@@@@@9uW85WcHA0P0N0Q2o0a1y30983y@lA000e9B00y@F +O00Wm50ymB8LL5um3F0y70KLLG0mC0AxN500H0tv@Vsy210800000hj10WLrQ@@VaoIFXVqD +0eR2GnpsK@0R5@f2420W_fPOfC3c08XXXfwxU3008oTXV5RuBnF_9ioF3ZxdmBkT1_T0OWnJ +0H08qd03hW@mX9Kr8l1000eb800S4PBtanmVzFSCSHzsB10WvxKp55fs2myw@7F@@9pSuZs9 +uJ00u@@6100Gz@@3002W_@@@@@p9zM6000m2U008o@9lSd100BK@@39W41WmvV0a@3Grt@@@ +lDG00000m4a@V200oB6J@@atMj3S3IzUcsID00GJzss9K3UBFaRG01a08008fWS00WG00000 +mK2G3R9qNUB002028udcW_y@@M00Ck@5kD00000W02y@lP0m00ICncyra8BV3wkFA000yq50 +0_@V64G008001wKN2W00GPF4500Mo2zpiK_40Af0yy@d00024100qXF9bq_VQcOiSV20S70M +xjnexPecV3000mW300eiV9Ipu@PuEfYp480000sG0eLoeUvV90008000OZldXfnLPcVj00WW +KkA300C000m4bnJ55Qq8eL1WrCK40G00000K00405yR02CW000G3000eDD00KtA38G00YSv@ +hY2P2O30C0G000W0830Giu600F0OhV6s6lbos@V_V6004idmbDpJBK1ug0gX18J7RQdSfQk3 +nG00GI1rTIlbnKdm@tU00608@R600000id0eY2OYa4ZBTcfux4QuP3000mK600AprZ6VUufR +6oEqWmAufJ@4QrFXrqJ0014m@@600uweRZGQvFXPrDuxS60080z@F3024029ebk6E1qO2GWj +HLpLKg300U2PclkO30oM@yTs082001G0mh6jKmVELVamAQmKbPQ0008O100aVlDRseo@_@00 +uLyZVIQyc1008008004100aEQQW720Imp612G0xn_000GWsse2000Fx00W@@91201m@@9000 +4wHkA0020SB7L00CGkKQ60W10X1YHYWK1ov1uwfP0G008E00eWy7QquA000WS600M4gb6YD0 +40Gm@@f10uz@@VI0080LDk100000C0000W005Q0000jXUNb0090m8_p300Wde00Gnuj000q4 +0082mF0W7XUuLEj00y2y@@C0uV00006000UFM_@Vr@@Eyj7000Cf10W@n39FLp6kFX8uJO_U +300WWNY@3Fl@plpyqBh1RypGRz608P0u@V604G0Kvk4zkhI_QTTalblLQ00Wej_jp400WG@i +6GW01008000H0Wdm@FupV008Q5O_X5Qk18t0058000H00UMmI0010000OjE00amzUbrkHiR9 +008n3000002GWgtCeN4y_@N20006vmR04000mWC0G000002O4KGZ0100000Hywh1000OWC0G +K2W1@@BNpxOyaQ2VxR00W1E00O0@@Z700Ialth0002000080GX1800Gr00002PeW10200R0W +dmp40001E2000000000C@k1lItUO2n401u746k100qAS000030004W1mMu@t5Dd5UFJU0I00 +uYe9SgQR_dZ@V0yS0GJuDcmW40000ZbyXpjyRu@A004_a1T5pj7IjxgKAl1lo@Gpy90000CB +13Ie@XK0C8ZU30u60yIF35rNHRz@ynl700800400Kzs6000G1C00yTF3@_RGp@C48W7dwRJU +wIqtF3n5OGnw900GABPRv0000z0B6RRL18W0WS@J300WuvlCKF_90009V3mWew8CDTC00aH4 +OhSrdN10G0WWvn0qt2Gpxf1008v@V3K8G0yIS2dwd020010004v@RG8_C000WIj00G5moDdi +408G0gItWHtb00GNPMnl5vT542000800Svl1010XU@@1Wp80ZA@MuR9axj4T0um_@900o1OB +@q000W2G000W100000ea_VG100pz46CPg4000uK100K1tRW00GxGdXHwgOCV600SvbdDR060 +00000W2B88Sf4I181I0000a0A00000K20wz@701n0iJUQ000LR0mW@@b0L10mX5UKeUQ000h +100G0i308jR60Wc00000p100GUs6030000W3my@C008OFAT5BMeYll@lVPCgL_1G004fGnGY +SL00mqhFWAYa_aSfPeQwYs_i2maD073Rm5eR4fWMZRbGipR0000o800mdfvSSw3VARGEPRKC +6C@@R00W2po2PhKGR0m30qRSWnh72g00WIZ7Bwj4AbR600v0@@@@@@51004bT00mQ6l5sFCH +lAnT6J2Qd0e5@n00A0alFF0300ET5iaK@10GOHiwWL0V2jad3W@5WFm7xwI3cyt6000q6600 +QBVimtIu@@P00q4_@@LL6jHh@m0Oy18w@k010000G10120urtv000WmP00GlrvV1E30O0000 +40CrLE0O30M2@@mmBjRtY0uq04l_@BhPJt@F008dCM@@@@@@zA@Flp@lBz@wM@Vks@Zxz@tY +@ljv@Nh_@qk@@iSi100WhU00eWo6F@N200VT@@NK0gvCM@@Xz@Vys@@E_@jh@@wy@dk@@@0@ +VFo@l3z@vO@@Du@tnD6@@Vo9x9K7W4000OOC00y@lAlLhoKuvqRW400EaJsdmzpz0GE3GX3Q +TZ@@@@@@ox@dS@@7@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@vm@@D_@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ps8y6y2l1000HQY@X@@J0Cr1m@@o18W0ePU60C0 +00001gUUC000Wp100OJz@@@l20084T@RmP@608O00000280WeUzD8oV90zU0iilSLFO0080W +0AgOz@700007IXSG0001000G000G000G30600048H33000100001000Hd@C00f2us@w08000 +00WO1W200000HY0000004000000GRQOG706y@l100A2_@NE04W08000gI810020004010001 +010imW46CmW@@D0SL0m@@l10200805104040G800G0000W00a00W0W000g00a0200400QJnW +W7I00008T10WIAaZ0000W0008100020Gm0040AY0w@V30008140000018002m@@J00m1u@@l +10X00000GJ660014A5W40400S3W131mm@@60C00u@@tW1000000048000100GW10f0a00080 +O00W31amQ690000DD3s008000024020WG042H00440I0GI0005001P80410W0410S8400004 +28I000a0GKeF9000jx@@t0W0800010200510W2080GL0O0081487000H010a5000W007G0m@ +@C0Gr1u5bt000K040Y0WD0000000i200G008G4000A000G0eN00WK0C00100800040000002 +000meG00u@@q00H41000Wxl7000000iR00G00mC0OY16000COk@300U00300W0M2mW@@P00G +4s@@i10g000o0g100434f028I1WHa2mE050LWE0g0T0H2s1f0OW85WA0AWa0T00EI910z60@ +@@c@10000W@200@540@B80_700yF0y@V0uVG70CGA0CmV00OPA3000W8G00u@@@@@@@@@9d0 +20000WG2000000G2io000Y0t7nGCSCKnL8WWF0YsAA80008800W200bPb10012_@F11W8W9N +b0000a6fOu@VC000GhN00u8Ag0000WG00OD16G0000004eoC6_@@400vIJFG506W00G80a00 +0020W0004G000meU600088_F6050004008MFC_@F10f00pgfrAPCy@VE000eC100y@lJ00G2 +080000W0uaC60G02C0s3@@d0020Y0sCuoE3M2G2089Nzlr5180WIzI0H00HI6OK0Y1@@Z10S +4WE7Z240000G00280000100108qGN2001000A0qbW4Bmnm@@I000W3_00m@@E10O00800000 +400W84PfO000G000Y00W008000G600eq16YsB1G00024000008C2X400c8@@FA0W8000G500 +X400YKG042m@@6e0000800IY6L80000Y0Wm@@R0mW184Cg0a000000W8010008140WG00800 +000H8000018IuCCSIn3400GAXZXBGJ0m00m@@H1W0X020000W40G0W20WG010600400O1E3W +908Sgu3LGomZYFy@l100aN@@dACH60EG6850562C2W01411Xa81n04100OW02000800000KG +jd9yHf1G080@dvXD5O08T0m@@E1W00050010m20000800014621000111W00W80Wi9JOQK30 +40Yy@V2081G00000I00uKX7YuwA4020000JMyq0000400W80uAK00020Wc0GxHCaXf400W4g +1e200qd@@J50g2000000F000Wg0G0308oJ30002i_c4@@J2Wx1W@@T2020004CI2G58403WK +WE0fW81p1HAW0WK0M300G0G001G4K9b100W02yCXJXDuCL30040SBy30000FUnZ@@dXg0400 +200@300_7ymnCuXB8m3NGCxlWKLr@@J0cd1GtU9KBS2nfQmOh600C1u@V600CzVEgPfC@m@@ +j0Yz1OKskgsYa@@39Ggh_@7rJRDOy2XYK8glWD000Guxk948i100400010K4k1000GUfG500 +0W8600AYcA0000420G0Gm8100060010010000GWfDPGJN64sZ4FIX100YXbHlgtO3G400ylR +2hSbm@@m0Qg1O8wh00Y0020W0500080020020008004W0040020010000uurDeQz7Uv6ZGpk +AOD900080W0WuCcP00miKMEL8002000G0W0W08G00004a2PC000WWG00000220119WG40y@l +A4P00_@dA20080p000W0WWY10c80GGW_6W800G00080W00004ap@5IEyCuM00ORxe0000L@k +1GO0000020W0G0001m2y60005OrVO00mlCMUK0020m20102O20080XQW00G4082H00000008 +Y00G0G088000004W8GH_@N5GID0nPI541003G820W10mo8gWK08000W5000088W2414W0a80 +X0I89LeMSF00C8LK081X8010800oYGW029G8Wt@D002142000I1bG0WG0GYI0z6k13@J20Wa +e@@Z220000m010102000C4G00e8408ZU3W140100010O0000884006v_h2ec5W@@T2040rf@ +600G00200004e0080A0W1uW0G0X00GH019802WG00aWWG002aIbdDW9SRI00W8000e4C000S +00230C206G5100G1204420988G00G00ehVs20Wadd@ZY0020WU100080G040005YG100a9GW +0000Gx000400141G0W200G0W_Ik@g0A80u@@h00G00WP00G0800000K0G40000y050YPCmm@ +0100ywV1yB0PXfYF00W@@To00008000O020e2S3G5WX0003GW0KW85WAHAWT0I0C0s1s1y3Y +4W10mbBg000QgDpe00pFNbf100C010G0000287y4eggWBy@1W@11m5Eg00000qL1mOu@t4NH +00yyxYwg85Q7000lS10WA2Twuu4U0VZk2R100HUSYNjNj4vWBnNuLS8k4W650AkEg8KDuOxD +gvEXEk810007910W@@DB5bJkYN200lt@@FsSu6qgOE0uV0ohJhDzDu9S3YVC700Weo000A8j +h7pDuyV6E856000h9fEsNvF4AKB00000HF04LeM00W0001000020G80Ohj6a1P2fzs2510W6 +5CR@V3ogtWLIR10GhSWzQ10040a00002012H0000400WGb002000042I0000GW0v_h2e15Wp +H0320W1W0001080m0G004000002Q5S9Ixr3y200r2hb00W80000O0C20000W0018A9R008N6 +o4OluO000GWkHPuDZM0Ie0KQDF3z7228W0W0qBeK0000e40800uTz40G204vgAXc5re@O00O +Wv_u9100O04100u7000A000e80001l100020H0000ymRNj0u81uTvPo1x400W@oF00YUM883 +00LNRsGkI0004eOT3cckYMsJ00GnzKFiD7s6Zm@mFyC0iB0OCSpQw1cWcPGg00mgUW5qU800 +0W2Q@XK0Cu@V300yIa7LNnxL40e0WTuVxg76UxPZ5gJ0000RQ62DUQBTv3Ps3OSRE3FdlH1w +90M40Oi3y6xy@mIb3Op2Gyaj000CO1W2_@tWE0C006OGA0CqhgzW6002yi50m00dRdW0000C +0002000m002ibgM00UsB_V600m000W0oyp000W0T0OGA0C4tlJ4HD0QGj5042000000G9a00 +000G0G2000001WPA101W020a2W1dz7LqrgqLy30C8000001WW0u38300818000C503cyQf@@ +D00GTKmelbKmCWwS0o2Ygg4QPhjGKD00adlARvR0400000WDK00s005s000O7100000G1000 +00q6400P0qnC3d87IRp60003850Aw@t000GeDjV200uCW008010080eiGyImW0002DNk4XW7 +80p0HGaHw1GAqYee881AHG7U20Zz_GKzR45m31TRGA0I000u@@@J008X000010590m@J000W +000410080S0m000400W0fw110mV204G500WU000000G8I0004H04H000a8am@t8A06424HWG +a0850A00Z3z@l18W00MmC40S801eGrOv3300mbD00Gzw@FFlb087200EWWJ0000um10000vG +07004EJ1WYe0E1d000820Wbz@Vwi@JzlE0WS11tBX1000000qw400wm7300maFaR0810WAzJ +00J2aSA0WK0Iejzk0m7GZ00000mABmfl0D1000uB0w6Soa2C05q00uBef5@_Fnm@FSy@2B@V +mp@3Cz@@M@lls@txz@yY@@kv@hh_@vk@Fky@VR@@sw@Vj@@@@tfPAJ0eK1m@@l5YD3vOJ200 +0y8NbB2V3o0WX6rz000LPuo@@Djw08MxprknVvh08h0m0u@7WUrPFWA0K0Wu@P0000nP@94J +@@lyt2000ml@V08N0mi@G20108Ne7S700y@lY8G00FyH2000R@@@@@@m0W1000G0GWvF000W +O7fDwt@@@@3Si13M1eYCIiX500m@@HLeL2@@N400wp3rUxc@P0SI0iN@y0800sjnZ@08fV46 +00WKrcp9d3eobDFy@lG0960_ZmfAA_fsE3c1X1000eA300sl8j@@j10m_p@@98200eGG300Y +0y@VZ2MP0_@t004SGBBcGf4Hz@FF000uWB00y@V2000Y00080900u@@610m7z@F3W8W01X02 +CEnR@@720e6W@@D00W8200W803AGg82W8400y@lY000m0700y@l1G4H000YAW121091Wu@@D +20e@z@V3000G20000GX006000S240@@t8OV3W@@D00Y0000W00eW80004YlgH000iXFc0800 +0088W8000G000z@VZ00CsZfY148KG50ro@@c1sh1u@@4000820u0GG0G8H00WqCQqD00m@@6 +0uV000CJbgQX0wdin@@t80WWo@@J0L000k0k800SHJwkn@@r12m1u@V300p9300wY0000008 +0@100rmTUUn6y1t61onmCMR00WifmktgikYXnau@V60zU04fTNXU94000GD000zMpMjrUy@V +500s4wRpcAzWvyR6E2aXnjDuly4w0WXm3J0KB0GDfL4Y83@h9400GWwJJW000mKhCisg1tjo +m5ZF0000YY00m@@60101OhERgTSff8Ve7U300i8SVOKb@jHBy9y286lnd0W00W4vJ0CV1mXy +ayVfGbvd0080Wu2t0400nQAF000c6s20G8dFiLY731YKdXRqsR20004800000OzAot70W000 +G018yHdIWy100G0xDinzn9K7P2WmV0wvFXg6BgXXG00200400W010GywO08000200400008G +002000000WB620OaT600010003C0rGo4TZ5NhW2000H00WxtD00080400m0fnen16WG00820 +000WPPQy60002401GGW6m41z900040001G010000000K200W00hWBn@@900042000200G8XG +00000G80000_f80000200I0X0009nkqM_I000GOGV3G000KKm6000000600W0000O00W0000 +002000G87G00W000480Gsk64SLHdVR00A0W@@D000On@@6u0H0000Ge0e0G00000600I@N20 +W880000800W000eWWD80G0W2000000Yg_@t00NW8000AINjbWRtejtD000GKZB6xHRmbZ649 +D3WCN0_@F100W8d0V2000gnMn00481W10WqlV0160800eX2KD0G0G1I840Wc00@@B10eG002 +0e8080o9s0KA0200q6000G362500000J00WoFC04000005Wuzn300G4Y00Ws@VeU6600c1y@ +F9W@V0I@s300WafV@G4u6008010O0Y1a1S60086000ozN200m1000C00000S0m00001zD00W +80000000TG2000W000W0T0030H000k00ExWae0v10_@zCORWP00u@@4QJm0000O8400w18XM +bufQ6L2yj5010000gb@MxD0010VD23e51WHh_9i59I4q3W000hIt20008d300vWhu@@L00eD +zmTXM_1fDln0Ct3mswZ1100000Wmau60440vRCI020004G0u@V3mE200000020W0048000G8 +r8GLP_FijV8he@00Wvu@@JG0200044WG5fwvS38010aU_900800040KRM2WWJ1_lZXC1pvDE +OsP@XLBs0000Yc00W@@Z200WGHyF01400080mjz90200A6u4sjFXswJ8vE600200WPDgAck2 +dlYybUu@@G0Q7040FR3yRW000W9_9vhV3000mPJ00uZ_n8W00qvE3W0WGQqFXC@D0010GMb9 +C@_300egEU4ZWXu1040G4rCCZV2m00200W0224000K4mAQaW00001000Wt1Wo7buLr4_bCd7 +gb000emLw6G90000000402Wr2t08000042WCkJ0O00G8jIW000080001A1WePH22X0mVL600 +0W00A8mLgFSEv3rpQ0C00WmCD000qwcb6yd93000W00010G0GeyQR0880y@l4010400000a0 +Y0300X1a60K40Gfu_mEkC4O9300000XZ0iug7j0MKmt98000YA4W000AW8XV0000OkmI0001 +0G000000YCkD8VO9caEd4ha000G330400s0000G0G00210A400WWEJ00WZRP0120mPk9SMk1 +000Q80000GA000mAF240m9TV000GOP49SPFC000mU0uW@@PGL10000000mD05c5o@@9000eI +410G9y6u0008GuewlqW@@J000S400030004030C0o0S1y30usD600600000TAk7W10000G6w +@V300CZ6Bd1FAp0008W2aCW700GVLH1W1mK000000OW8@L1mb3mw@ibSAC4000000Wv100em +yF10iJ6999HiJUQ@y0000rq00mzp2D6S580000002Kyj10W0000100010gAU3eG00yulA00W +f607cFd3vAw44000SPU200G000W00G000WW0Glv600G00W001010WgoJ0800mMy60400StO6 +0ik0i_l1014OgHtWCtV8dw4kAFaWrVOQT3EstWsrJOiU3UdrW1xJOZV3MLFXUrDus_40000A +D008776MsEaNiPulVCMzt00G000001w8810G080W4008GG0040uA83cJ8XN_be60600K0tsV +20410wxNYuvD8AVX008GqFF3Lhz0410WoWh8iU30Al0iCF3JpR0008XwzH20G2GOz600W0Ao +U300101W0W02G0GPsd000cJo01W00080X0G00WWEwd10400fsdm0sy8040ysT30W0WSaV204 +0agKVZb_V00mnRJR600100800OlS9ajO275a30e02000022000000A0WGuKP3G14000808HL +O0z0C008W0010HKlH11800000880D0G40Y040401080W0G041018G0004006220Q@FXGAC00 +H0mg@CCxl100080000H8D800G08800G00OW1_d00G0G0204ZIdmiqpSjl10410G0W0GO0001 +000eW0mEKC0WGW00X0mS@bePR94040200000WW1000H04028C00000A000WW000100024000 +l6O08W0WWRp100e400W00aG8K00000044373lVN12K0WH_J0008WI80W_@D0yw300W200eaI +W402800084I0000G018108G294GeI0G0900500800Gsvsa3k15XR0210WOuC8XU3I@MYtzP0 +01000G0G01000WG0000WZN500000088000042BNO0000111W022G4m0W0040000A4GLmpS4l +100CmWG0490002WW00O210001m01X0Gm4G8004uFz440400000fK_AUCt000MW622804B000 +0000W0q@@680080000W004W@@J0W0WmjmsGW40040G21W0WmrDG40G000W0GK04dvp0W00WU +@nuxG306Y80W80A6V3YhnWKlDesR3_Et000019yE3G0000040eW4Y10fDWY2000ms0W00qOu +I0xc0ma@Ia8_38K0W00440000GdK10G0WKl040v@R00A0000G2ez0000eD08004001GJSCC9 +UT000xdfE10W1c@@N1g_FWxzd100uC00G60N000P000G10005100G0C0u20Xm5unmzGux6a3 +k19@R000GG0004y800Aps0WHK1000d100g0O00001920000F4000e900WY000Hy60OyW000m +9VD8VVOy@l0000Sd300000800003O00ani000800m@01000000uF0@@@000FWntP00F0GIg9 +mB@0m@2004VK500WPBBhLtyy00GTFpHaY3FaoqpPOC3ENFdgsHgr@wYDtWumVeHSR00u_@G_ +F010GkLNYwrVea@4oEF10100xtcmybX0ew10000qFcLCklAXq@04G0002W00GG0WC01840GG +0088040W3vD08008G2G0000001G0_ut02400ZnR0020WS_buIU34310ibT2DPNHZR9i_U502 +00olz100W0810IQEnW3kD00G1mg@6000060018100W85I00440100WAvD8Rx7_qF100MNxh6 +omtCCy@3b_Rmw@L800G10W00284000002004Iv@XHQVOsVF0J6800002081mUx9aTvCftp00 +08ayoD0G00mjz90081e6jS000GBF00O2TCwpFXyUt8yx400208200OSV300220008ufG30W1 +00HK0eXVU0mGyy@l10W80IZ9700GW200002G0100081H300G0202010W0081Ge5kJuNkS06B +0CrV2N7Bnyy6akV801G0Ndt0eW60lzc080040010020GQbMYeKR10001v000G0000200QhVZ +0a310Y000W8110f040000nW40204gMB3W0408WYW0Hb00000XYwJ8pLO000eEBl10800YesW +wxb0008oLyR000140G020000a8a80fW0c@t0400W0GP40440ga05Q@O3000G000G8c33sA66 +0eD01cRGXvLaYl10030c3ZX@@b00Oe3000H8Y8XWWc0e210G100exR30WIG2040004802G00 +40W0KA40M8F10e00jth2X1000000d1W120002521W000AeYX0pb0Y00000AK0W0000QWkjqW +4uI04X00mG08000G4212cxt600Tx@fx1000ZLqC8bRC00W0020C000002W0000000aW00000 +W40800W000eW0000K001K0W2G0021480C11G0WG2DuJnM0kV0q_V2ZkB1200000824000g9P +300WW2031100W81180040002000001G40H6@t0828000040011I000OiL6g_M5000yI400Ug +FXAxVuPV36LEaD3D000020810020WeH2W10W4qak1000AO0100m6eG5010GR0ex@D000G221 +0W_GL10Gv0200W1pt000040ee4020eQ000Qgl200A0XwR0410E04008K4p00qG300000VzD0 +0000uA0njB48m7Wzt5200@3000UKLLB8G@a9zG0009100G0A0e20101e600GC000m000Wc00 +080700qY0a1000083aVSBAA00IKoWq@h06000P0t00qY0@@N10A000W10000W10L000k0MH0 +0iY0eWDrD01000u1000uh90G0100GH6lk1r2bGU@j00WALu0mCd10000E0h@Z10K5W@@n000 +CW1000000pI600qb000000G0@1GQRBD@l1Ww700a00azF64020MiFXe0sOAECMYtW5yP0600 +G0@9iMD3@Ll1000ME00097NnxrjiXG8pf3Pgt9ijl17uQm@@600a0eyR6Ipt0W000xAx1mT6 +Wv_mO_I3c0ScweJ0W00OOz900400100Imm60G008vT302G0MPh70000100G3S0090nGcnl50 +0H404aO00gY2K00001800X000210040841WW000014103010G02A2ltb0000mymDeyGC00aL +G10000040G00YxZJu@@404084qW1D_r204040G5000K0cSt0010GdeR0W80001104040_@F1 +00C05@J2WUbWHKDeiS90000EsZ1tOq20004W005G00Y50e0000e0241mV@604M0OLM308901 +AG0cG0000W0WB7DW800GNv6ick4VMO0jH0WhpJG000u8zLaVSB02W0sMs0040Y000G00GIqn +_3JCpW4GGWwyV8VU600G0W00000GULJTR4Nl1XuNnZz9000HuB_701120000W0X0020001G0 +0C2000020qdX1GO0000W0yml128W000YWSMe1000G0G00Saa10001cbpWk_Jmef2G2yIqqV2 +h_d040GWj@bO0H3Qt@100200018060OqoP204390800W000W0002000pfkDeL_401008100O +f430008G400u6V600801000MV00G@5Ry@l1W004cgFXqwP8RP3QFM2G001W00W44W00000H0 +00GIZ6010G8hc401GaiHv67IRGG_900uSV1wG04204gl4j5mGt_C000WH01C8G05080S8212 +G00K8WA82Y0G0004W02400aG00GWG4W0280085W0204088808000I100W001010400008e80 +000200G4G00000440W0GG0000WEL0AYT3800000109020OW04OFy4W0000020W2000G00040 +02Dg@0020G42W0AWBHW0WK0X06H0040K805YWW0vRP0490L000A00HH@ot0We020100Uxq00 +0080000100OW0000004128000000800G000mP500O4x7kgB10004600000100a00u@V9GG00 +00100200Ozv6K5C3088be080KxV20G904G200054200000WG140W00G00t3t0Af40blbW000 +840O001CW8K80KBN2008000WmzUE300WGW0008050u@V300KW1004ANS369tWglD0025IA06 +W04W21084X25WNCV0840W00004g010008000WW00G8Bk408001080080mmKr6ywV2000G004 +010G200GWH5p6qKk180000DO0CyD3K000gVa10410003We42000GmOR96oYp02WXI000W806 +OiVF30W26W20120W1K4000B06C04180C00W0200240I4HW320W4W280GW0W001801S029W5W +000G0G4W0000000C00404800W00600000e0W20040W0600000WD10W3vPucI66cq013m1W10 +YW0G00Y00ujT30004A01040410WC06W0000Y00Ekd100A00W040WYG0040G2220240140000 +0Wa00001001000D062182Wm0W0HG00G4000W0028Ivw94UZ1Rqdms_60080EouD0W40aVl14 +140_@d1080A@@RmhH6SPb1Dqd010400y2000080400008000W0iLeH0020Wjjb020G1W0qBe +00000wlG8008pE3000W08Jeb40000D100080G20W00520000b90000i6WI_P000K0200WSnJ +uoS3Gz28002V10C00008X5VC000GX30040@2LA0000wB0z@F30m4007S10OWzb@@3aWcWQL7 +0000WlGL000000mT4100St1@J@@20Yu50mY0WggxXR3000i@@l10rk0wyt04X8u20000000Q +r000000de00Wc@z00W160mCY1xV0eW2merC000mKW00m@@6O00006000p050K1K1K1m000u6 +0006200W100G5W0WY0L0L0g000u20006000e200m5u002mP02WG00061000X000g200Gm70W +1G401mFuH2300KejYF3W0W0008Z4JE3000Ced1000m0eE@4006WO0C0p10qE30006000m000 +W1u00WM4AIX4000t9W@Val0eA0hUN_f20Stz0eA00000200C300K50WN54Y80H82000z0000 +1000G4000OW00eWQyV3WP507@p0ypFWo@POMy4uL00i2_6XjNn@mFScl1vwwHitL0000ChMI +Ywt001W0F3dGypXail1NYdGg76iBk1W000Mto0010WXYRGwu90000iHK3Y6d100Yj00G0U9t +0G080V@RGJQ60G808d33UfsW@YJeew4UltWIuEv_S36G@XxFC86z7cFN2WU90rpTrGPCq1t3 +jERm3xI00001W20GquF000Wbw00H@@600GWuoT3008000W0evP30240Syk1nzomux9aer3x8 +a004800W00m0G00G400f00OsS3050000002W00WG0400Y0GZXRW004XsqC0G08Kds64V_3G0 +0000qi02000004m8eUSOhA0000H08S00011Wa01015K0200W0GIG080200100WW8G01G8208 +0480100a02G0i_U30400yCX106a05000040G0A00Iol6q0d10690kRd14000FPpGYs6yRQ2X +wRGVu90G01G000Go_9W000u@V3002400020Y104G08O044208m008G008W10020O61600W00 +G02mSy60000CpS3000W0G180000uDi6S@l10018000G2E01O5y4cOkYnqD0801GZxU4lT202 +He82011GG00eG01G10WSfDenV304001A10Gm0018G00102K0040404800W000W02GWW88080 +DJOmmL6aLN200GgBwuXGvCeAyDwHF100480W00Yq@140W8000004A108000020mMvI4IJ2rQ +RG3@6C7l1nKOGPrI0sQZunLFwf4c2zD021W0801WMvD0008W0080H00284004040010000G4 +00Y0000240100400G0W00G4GW0010080007sRmaz6SUl100WvXB00A001uuw7000W0002eh_ +7QktW9yP8gzA6Km001041mR0040G2W40028000Y0S@l1821000G0001GukN6G000kia18002 +008010G0y6R3040000GW20000202010000008G000SzM2huRGZ_64NV2VwpGOrL000GubP30 +G001002G0C00020W5_D00G8000001GH000300XG0240001001A00W2vJ0004Pd@6aKV2TgR0 +ua7WGzJ0120mGnC00040004Gzb6azD3lHbGF@L00D800O04G11410O4G4X081000X0K01002 +010H0G0000Y8W08G0A8W0040820100110W0000X0082800C0000Y100H005ER0800010G020 +00000W0C001000a008Wr@J0820000040042000G0G0WK0e1jSQGDbFaoV501000G0CWH20LG +000f8018W0W00uW04210022580W008WGCWW00882XAI89m800116G_86G120GG0m00801000 +1G00Kw5t00G00020000GiY82G09400H00004095_RG8Z6CYc1000WU3rWS@D0G0G04000000 +37_j140000eW200000W8Ay@l1K0W000000050100004K000G10G085009045W1xXd00K0G00 +000G15G40800f4e_V384000Sd0020040KIXavDG8000408anvPO6V3_dt00W0GHmRmM_R005 +0OwM60020G460eoE30G000002u313Q3G20a50pgd00200WWW20W00000O0000rbAG00W0Wxw +D0X40mM@9yPV2G000Q@pWK0OOx_D84200W100004040Y04Ce00CG0400K4VW1GWO24800e0H +0002150O2G0G0080m05AY0000G050022480C108GK0000Gu00880028280W2G10000uA8W0W +0Sf00020011002001000GW0002240600800030120WAW41gst0090000G0Yzt00W50ZyZX00 +Y04041G0K00G000000100GX050440000Y0001G000202080440080G0e0004010420082108 +0G400W0K08WG100G482008pj400000OFH0W0200e0000000010h6910H0000G00020008000 +86ncz60H00040000Y0004101cbmdyI0000G300mWB6q1W180100044CEV28XG00G34W00000 +D0meV6aSk1QW00o3mW@@D0X000G0w5000qEbW20000v500000G0G020G00000L0000000W4f +gM30004G0001Kc0040000920FjR0084Xcnn0U8p3UGc7yW7pc1Fye5Uu1PymZoQX7aX@18p3 +FmZ7UWvP@3FyG6uXl80oSH0y@YOcPCfgg0m@@nKcBYfCN4WK0C0pO2W@fgA0GLLXhR00WHk@ +rDmz00000G600000m3FWm@U0n@10Y@30F_70Uun3ym34vV08w1FGqCpWe@1m3pCZgK50Fu1Y +0K5F60W05101g0K2K4W1g20340WA80AGG0KWY0W0C051A2e0r1K220e60W24005GH0A060M0 +51T0g0g000K10G120W2K405e2GB03WA0604400k10000000wB00002000L01040_980O200W +00002004W108010H060Z040r000C20W00001G002I1mW0dOOt@70G410H43W__310OcV@VFG +oE0@uN0t1p0G4Y00Fe00H8wh9u7m050GPB0u1N0i@F0W3E00AeSt141OW100C30YW70G1D00 +mC00000580K9e00WP000000SQ@H0TOBXk30000000WR0s@730uP0pMFsU_60081EXvDAF2cx +qyuLw4AOZ102000002wYpWbpbugS30Cy0SG93JepGtS9SZU200080800KDT2DOpGpqgaC06J +iN10040000O8300oxBaVp3PmB9Qy6ZE2g8rI6E@N200JXRapGo1X0801e0y4ATNYboDG0801 +00001W0000140080CTh1n@d0e0008000000K_TJ5W620plLny@6SBc1XXRmpe6q7U24G01go +@XSZDOKT3UAt00221Pa@mSXCaAT2@Ru1000Sw00G3zymE@904G08R63_@F1e020pzN101001 +040HAa0014XNSD0400qVpFS4U22600UutWoq31008yR@600W0uTT60090Cwl1xmpGih6a3W1 +NsoGFxL8040000WW000WXvDO0U3AhtWzvguolD0Lc0ab@60G020004KCl10I00gcdXluP00W +000e020000W100cad18W005uho@@60102ue_40m00iWZ1M300kD8aCER1000WW00WTHDOKkG +6eyXU_JOkV60mOoY002uOV9guCXV6OOc93A@dXC2CO7V3kzt00202PQgY0W00H0005_@0080 +W2QDu_@40Yg000000808mIpC4vz3BNnG0dLiVW1fjR04W0WktVeerDMdVZ2uJ0000Ap00W82 +n008G000GWyoCOGU981W0SIU5W000oP911202voZHev602008qU60000G0040000GhI6qNi1 +00kgBQ8XfwPuaV380800000X200W040WFxD0800mM@64Zl100042apWW1J080YW010300GWn +tR0004eV_tW0W4mg3C0000W030020GWIoD000810Y0G000006f0ABpWyCPOdE6gRXXB@J080 +00080edJJG080GbZ90900i0y400000030u3S3gQpWd@PG000000IXwnDek@40500G8bW4048 +010A440800W41000Go70000800142WkhP000G20008010W080084000W40000100A10004G0 +000K200bo83baRGB19as@30002@aFXIua0100mceCG420OUT304280200Aw33000M1000G00 +W0CKWm2qD0042008G104400W020W6X0J0OeMC3GW200G0001400500G0G00z@RGC1Cqdk1W4 +0WgmnWHvIOEV62zd10050070W0W00SvV2000HW0S00Gm200W0008Y0280W200084000_bj0W +W0040AWp@D0008008W109W0W0000aW8020001WW0B080NG10C00WMBr0000100110004Src1 +PyRW20G00G18W0040040spx3jVRmptF0002OSr4cscXH0O000010010000C0700_@F1WW50G +00W4800010W42500400I88MWztR0224G0G1200G400400eWGupO600008I0000W0000I0W00 +08G2Wt2z10a0X40G0wizXp_DW900mZoCWA20000_ok_6080WG9000OJ0000qKe40000eDKnl +1G00WWG0001HW30400051H0G00200410z08000a9m1GA0900010C00Gl_6Kkk1NpRGEWRK_T +5080W1C0000W2AwV3000OcVj10000GLG0i@V2VDa00000000p00000W@BWvmN40@l8cP6S0y +F0y7Um5_Y0m@5XNLBoCcNKLgI50_7pCz0LL5Bd1x@R00c1Wg_J003000a4000180000g5n01 +00061000100KQC3000100022008QN_4M0n00W10003m002WO8H2610y21000000CsY400060 +0080600021O20000m82W2G405W90A0J0N0k0c8C1CPf0y0W9210N4004000W00aFW10GH000 +0WsGV2080yXF0000Wo6m0000W8_ryD8GE9W8Y0KQz3ThRGpwF008rwKT300c000Cm8XzAG1L +14zF38Y80U@F1q500000000O03O0000WHNMSc5UTKRw2JLzI000Wpb00GTQRSVh4XGront51 +0O@9f0I_4ddI3nueSL0DA0C6eA@dVrdzU000Wok00m2LR4WE3fuQ00GWao_J00081002a@@D +W004GlYN10mnje1FcqsWm@D8BT3cJBXeqP8OXk01_0KY@6G0007PqWGLDuDL3G040aOU2040 +WQut00G20DL6Lu_6000WDxXDEX@XFnO8lU30002ypl4tFgoi@d00On@@@DMjtWQpJ0H41W02 +000G0020W000GGirM2Pj9HydEP_d0uiJI4002i@l1010W1W002020000100W4WjsCeoB6W00 +0qDYGvZyWz00WvThOrH3Qjt0W000020WAOtW8xD0000IszF0200001GmSgKLEh1zeSo4@68X +00OaV30WW4q4931zdW004W1S4AxV60Tt0qw@6dRR0001010a0000G004W040Yn0004200083 +10Y140sYpWI_Peb@4cA09000qg100ovR380G000004O100000204G464W00H008G00KW0008 +58GX402080XP8C090Gmp76yAd14e406p5900v3HGNH95684101008aG80WSnD00003W02G00 +G40G90180800O0200GGYu64MX1ZiQ000800202fvi4W82WC@h00090400084000030e40000 +0muhV3G04000G101G01K4810GW801G0W0100050040G0H00WjuPOb2a000GnP008C@A00410 +000JmH0000Y9000OG081sKt0123a00004Y4S802GOOT60081ivoL00goZMs300010802x5t0 +10G10a0W40000I0022002G10WcuPG0G0mUx6G0008oT3kc29WsD0R_B100eWT2J00000Qb1H +W0yBW00000XYG80040000W0W2G0008q4WY5tWK_D00m00000qRfZ2000cR00Wogz00O6X000 +000Gc2W@@50vmZg800eq30mpC0O7K0@@RW700000W0000_zV00Cfl144000W70CXDI00ezoc +T300WcQH0TeZG00S30004000G000m4m0030106Wx000I100G3@901WO200nqFtN5sX1vVx10 +0WgUmJeBK300uPA0L1e1kRdEdA00v6P@IIts9ypk10008MHDXE5_Fgm4iD00y@R8RQdGri90 +8088TNFAOJeujJ000Cq0X5rn63xx758d4WJ@cv2U60001Snl172ZH7Z2PG008vwV0W00qQd1 +x8PmvX85tV200m9FcScydhe7rMM4l5GeE0hZtItyCygeP00WWGA00qD9UbiV20WN_OJpPmbq +0lU0KQnFvj26000SQ100vrR310GaRPDBOlJMR@Xi@DuYqq01704xnCXXRGyic10007s00G7m +j00C1000G00002O200beSrm@F00u1CusP00800001OVV9kF_AWpF0jZaPGA9GC00eEmP00S0 +00G0Us3p0040bJzCZwlHrrK10I0OGROW00001W92002qwQ@7oF300qlRaagqVh8WACUns302 +00WS10QiAa0tD00G2mqrCKUz3vbFJPsaaKW1i200gEua6kVebx7Y1lYwkdvfT900e26GU8Ph +RGvw9C6_OXpz0ek3WqdPe0wPQi8giPbGM00G_5jCOl40010oagB00uDHAGI9yCi3l40404ct +tfGlV0GP3mU4ErqVK000um600aToCTKMH0@N1We2lkVgk9z@QMj40WFQV@d000GPA5y0E90y +htIv7J5000Sq200xM1Je_9KT530080000G00G0wm_e00SeaRbAVs@0e00WhsV00X1GVcK1kX +18f0O6rtWWHV0000C00000022HNJbj00WcCRyyV9kNbXs_z00480010WaUJ004G0008Xf@P0 +G0010004WB20vIFF000YuQF100CmQ_60400eFV30o00a5t3800WxLqi6mnhksD0dt043tCr1 +n6000UF200VzV2WW0Wumg300ImMU5b409Nyb30g2WgWFvwO6UKy@zTa00GTng0HjiNKWwQ0w +Sxg_z@VLq@JLz@JP@lKt@75_@Gb@@Jw@xq_@DnR7000@Hup4AxR00EJN3slU0JcT00m@@RaS +S5xw@600@@MFF9tJF_QkY@@H2OS3mjysanE3LwRmGfN100S6O00mV@U4fG5nxRG@_6Kwl1hn +h500lcRzcStz70hW0ae@3RQhuj@6000051G0GO_2LdQ2nvQGM594kH2f0GHK0R4l_3q200In +mZK1WPryIpZeYG9g8A0Ckz_1mvDW3emmu@9aAmChXNn@7Ca205H1KnqoF0210ugyJI58aJpD +00a0m@@CyHk1f0GHK0Xi@V2WZB0c4AaK1Q1011G70Ea205H1GI_@900uulLsGI50c@@@@us@ +Zt@7m910LHVOo_RGJ00eQPdIsFA00dz@@Z12H200000W820oO_@t_n3W10000CWE0O0W10OA +0K45m900000FW1aAG5j3yGq0g8G201HW480004492100W0HW840a03C50AY2u4000Ww9G2I5 +e24100000GG4004D0CWa804a890000GG220000I49804918J1WYe0E10000cXaeK1gGGWm90 +0001n10f2CJvv@F__@Xt@V0f7MW8FXLomQ@6C@u6nu9ntzd000iUIVUUrtWTzF9SpS0Sa0it +FU1CU20006d100rEc3200We7D0200GmS64@ACp8AHD3I00mG_qkAI1WY@@n300OyLd94lLT3 +JAn0l6ymB3S5D0QJ0oOXb0K00Gei6azWVXsQ0GG0W@@b00W4o@@@@@Vu9BR0800000XH@@h8 +000280087Gd0004WRWD0Wz3m@@4cG_6000G2qx@@@L7000SYB6CM_3NcRGCy9KtiV00OKY0V +Za2aRvtA0u20ielVZj720004Y300PDoGTZFa2m3H1WoeNpy@@60dD0M6x1000GD0OGA0F450 +A@@V20a848Y00TzJ200lW@@D000W8400000W421Y8G8II844H0X8100G41G410f0O0a00We0 +GPRu@lXFm0In00m3mRz76Gw6s100Eyt9vG00m14E100007E0000a32u00WmPEf0GHK0F4Gw6 +KE72I5mcy1mudx@x9@@PuK9J@A0081zh5Uloh2eP0W62PBf0RmC00Cb@@@@l1104W@@P0Y00 +GRg9qaj1lhc0Gn7Wat03002GqyFqEl1f08HC0C000W0002OIz6GR000000OMz60000ij_4wh +FdMvb0800GryF08000040npjC00C020000I00Ws7J00040G020000000I@IpCpgUJ0iS1Ge_ +C08008NV3Is7l9WD0008oel90000ql00GZ_AA000040008Y0WXVP00naRq@Ds1c1@@@0G60W +@@LimP3G4104xy3O200wSNH040YPKRGe2C00OHlwX61100I04H4Y00mAsC0ox0uqi61000G1 +00eWv7i400KtlYtNN100Pb@@R40c0m@@I0a91u@V51G0WC9k4000OS900qyWY00200009y@@ +3002L_@@@CSi10Y0GW@C485LXup3M08000WoO5Q000B2a@V200clpu_@SsA2000Ya10WMp@@ +NCRo_@1ma80rwxNBkISzl4Q100_@VovUO00m2Jo__5LT2DM@GqLC0qE1u@@@JT@@Jx@lq@@@ +@@@Wn@@Nz@xb@@Tz@@@@@@x795000LRlK@s6y4_90100o2JY2dV00G0000mj1oP8uRI6IdXl +qDODT9U2NbEFhOQy4010008000mf3m0vCyqCRZdV2000wi5guIzJ02004UG2HqZ100WWvhP0 +010mXP60000P4S3gK0Z@@J00mWJZifz@VEWs00Y_7l9jF1000Fb10W5u1BxX7U@BXi7E100G +No_@@Mk7@@V2008EL000Tp_@U2vCyF3WEV0Mxz@@@PG400G0EUawF600w1__tC0008lvRm7u +IiyV800H0UySlmUEHi00GAll100WAs@M00qEswnd00000jz0SRiP00K00400Utg14000cVe5 +b100bX@@wj900400000C0W000008NY030y0Wvr@FU_IFzFX9ku9HQBlY2lHpo100qUOvuzad +7jXp0Wi4W3uewgm70000kNu6l6w10006D000JlJLVw9y1G2Xg@m7yCK3l4Tnp000Rxaz@@BT +r1Gisd3lzhYYHd@s000WoV00GnVHbKWJ002A@@F@_tcvqsDAsyahZcv@Va00Ghy@VKjlrIa2 +rz@Vf8G00@_Bd@@h000ms@@p3W10e@D3IIUfM6Sw@@@7QcJ000aw4006UcddbLPHwS00S4iG +zF@@F6up0Wbjnx@@@Zn_@Nm@l5z@NX@@Ky@@@@@hy@@1_@F1y@FG@@2u@@2wJoyF700CL9x@ +F0000G000@@@3000QK300Dx@@@@@7l@@7g@VXy@Fe@@@@@@Zm@tey@BI@VYs@V8_@5g@@Wy@ +7e@@@@@@ax@7P@@F_@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Pv@@nz@Ny@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@ND800W@@P00004a10W@@R1W00m@@@300000W0Ga2@00W0u@ +VZhCudIAU00WXq@@Y2W2000000008W68Ue6YA000080008f0y0W0Gq0290001QhOiyGU00WX +u@@@@@@@@@@@@@@@@FC0WG0gtfYYUEv@@70sX000000048Ig0a00088VWM6VvaPOy0000d30 +0WobIOHcGY2ua@@@@@@bIXmWe0Gv@VF004_Y0008LWb000d34003800010b5Y726400Gevob +04y01O682Y4IF0IXM45519G92wmJ08AWJ00000m0EFL0d000W000010490m@J000W0004161 +m000200GWKzW00uF102e200GF0We0E1000e000aK1S20a5p@@60000_ohD000a9M518A0I00 +W420oY10G2Gg0RSDW1000oo7ua@@@@@@@@@@@@@@@@@@JViE00nMFwLn@@j000Ge8mk0R400 +_0Qw@VE100ao20WN1D1m@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Lw@@_t@dV_@t +l@Vzz@F@@@@@@@@@@@@@@3r@VG@@7M_@Vj@VNz@lr@@@@@@@@@@@@@@@@@nx@NS@@3@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@F0WGu +@@bW00000000000195a9008W@@D0080m@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@NS@@3@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@d0000EY000@@Z10G0W@@340G00002s@@ +p1020m@@c1Ie0u@VC0004y@l72000_@7C0008000O9400y@FO0080sOW700Eu@@39004W@@V +08F0m@@_5AX70000000mGK008xXzAeeY@@V00Wty@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@yF46300G0MXwX@@R1eW2GuRu5idAW7002VZA00047bnmIPIy@lA00OeFJ3i@@D0800I2O +6a1630040k1B1008001400080a5c40R00_@FA02800440W000KJc13bP00100020W0500100 +00GW04eG00004G008W080010W00000L002000CmPuIumY4000mx200e21II1WY07a000010W +000100bwPmt3CCjd1060W2tp0G100004000G0qTe1brPGxWCaON2000GINJYp_g850Akz330 +02000G0gMC10010000W0280D_c1008000W0zyW1020G008W4NW1e08G02G01400O523Y3C10 +00io600E9yA4G00G00000W0000800080080000200400YBa142G0JMu1000000no@@7rtc6C +MP20104180G800000X0000C0902000W401200000Ga0000080G2049NcGZ56SLu3YcQ0_@dA +1000BFQ0W000020001000208200020G0X0e00008400019W40800G0OWW04H00YG20041000 +O0q0O20402oU81U000pXU5G000m090000H010a009H10081AP09000400400Y0084000I200 +0XX0W0000920ELvXvGD8jG300OB_NO5@@p304000800002G000e0aG00m3I10f20i4A0GY5G +0XGHe0PW0G0m0198816G4O20G020G15QWH01W1W00G22140G0000e000G0u0660MZ0Co8C3g +U2WOW0008WdUOW004G400X0CGc088W20I80G0320804GG4W4WH6D3202140442000H0WwFC0 +0001000G40W0jWQ0000G1300dZs51000004W0000GWIAjHQ2000W04012000a2A1m4h60098 +00W0400e4000G020f00Y008Y000H00002000htrMEpPdj000441G0000024G00xmQ0041000 +01K00000G0W0502000000G10080WW0500W00G2800W0030W00e000500G0000IP1e1qJ_hL5 +W004Ndo0G400020402000Y80St930W080G080A440001008800000000B1YW0Crh18000G00 +000100000Af80WvHYwAN3020000W200IW01081b81GA0G08W0G1000008E29Gi00cu8Y04G0 +G02W2G00200005100000IW01000021Wa000080008b002000000ikqc4FfCX1010WwaPW8K0 +0000Gl000V6d000K4K00000m600000090020040200002S0W0000882020GG0W80W3WqUD0K +l00000009207aW40_8WObDG00000U4000Wg0004P604XU0WoS0e0d180820W000W00_000yH +K00082O6005ag0000WPcBGL@N4pCl8cP600yF0y@Vm5_Y0000100003910WXRZ220000020O +000e2m000W10002000OC00mC020L0C0gI1W10e2W003050N0A000MH0KWY0e0S1G1u2u2m4m +5X9W920024080000B6dMd000cW@@N20_@@mo90_000_8605S600e005BO0000A02W8aF05uC +0080000GU0G9r6000140p0m@@F0680u@@@@@@@@@3@K_4sK2900vUzQdM2RIy@@9WKD0k2Bg +quDOy9a000G7O@6PqJLf@p00e3ACy@@I@@ku@VB@@@@@@@@@@@@@@@@@@@@@@VH10eZFSTKB +Sv400000dD09dBt@@j0000ZE00G5PXy@@@@@RC0002P0005vXn90JaKWYDxBny_GEfv@HY_@ +Zg@t8x@Bw_VYm@Vey@5I@@Ws@78_vBxRG80Gq4G8R@Z1OB0Wa26hFwAIAG55300zm@Vet51K +K1OP@07IyXk4V0000h@18W@@dSzD600eeTx0anjB1G@5W25@FCz@@Y@@ky@@@@@@@@@@@@@@ +@@@@@@@@@FBy7wYZX_mbeKSC000mqDt3vZpJMuXKQN2zXN1001Wa2yu5z4o7Fd0x@7u02muw +9Kl_3Vk@m_r9ypk1FjZ10G0WukT20GQpq0OakV2LX7oX5KrzF3WtE0EIGYomDuDS3s3FXS0U +8mlDYmt9000m0320_@7ZfDmua@7Y28aw_@@@@@pm@@@@@@@@@@@@@@@@@@@@@@@@Wuez@VO0 +0aX52dJ3OvHeRs0CZ1OggF100Wx400u@@bcGpWZ_S20mMxeuLK189@pxHWOjS283b1cm9W90 +EA18Dm4s3KYgoEvd_700W04e@9fyNnG@6aUV20007WE00yee4J_dGr0jKX@L00k@tZtZj@9P +6khUYC1Wk60HJeoZya0080ONI3QoqWYB@fSJ3a940Kj935NQ0W00W5BJezo4cja100085Rg2 +000aP1I88p4I1WYe0I88b7S500ikIKhzx40Wul@@@1880m1fgyEw3f0Gna39SgQ200w024eY +tIbOeq708G0aF13XK8nvf6Kug1jj_GA0K45W4XIa000aIG000BmcGBi6020WOQL6YXD100Y0 +9k8n0ba00I0e307I1WYe0auSK3000GhS00u@@Jo9bXpIDufaJ0001r1W3f0GHK0Iy@V200C0 +_@@@DiK7KA0m_6LKBBU1ILXD00W@@BwV8j00yNs5DL@@x4m@7W@@N24HG8a00W@@@Fc2a400 +00m00e30640W143W1zcRGA0F45G5L2m0Wh6mi0E9LWG_@t004810X8G480004Y41100W09G4 +40IWf0GHK0d8G000W74Og021000W840m@@600892019Y400004aW000009H220HI850AY2u4 +90000m08J5G8000E44000GE4W3001d00m@@@7N@@lz@@dw@t9@@Rw@@@@@@@@OyrU0_@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@Vjs@Jxz@pY@liv@7h_@mk@@hy@xQ@@jw@Fh@a50004Vk1vd72 +021W@@D0000ia00W@@J300YHX_6ael1lJdm@@F8G00u@V600yb_@FR0P00Q2Wa85U0ug0mh@ +i180000004W004W000pFOm@@I4im3000ePC00KE@@8000_I8X1ACG00GGA0I4zl72bU0cxd@ +VHO000040W0WpHOe3030100y@V800wXpU0iZHI0G0G0000040010000G000b203Xox1OC4Wn +vlwG4365vXK0aux_G000Wx000e5@hW80000140000000G000G400008009a20300I00002ao +V800Y0Yx@A00G100000280qoY100C0000W00Y085064200af0995e5G00004010000W02000 +001000E090400060u00000800WH0CW00006051000010YKm3A200@@JrY360802000W80080 +080088040W000040001H00G0K0a00FFaGI1U008_z@@k41H100G002450004080G400G0020 +Ha2W18A40I1mWyC21u61m@@Q10LUm31yF0YMLF4Tco8QLfo3PAZ@1WAFyWe@7WK0C0qggY70 +00@300vZuXQ10Wieqo0o020a1K002e00a10083G6G6WCWE0P05WK0O00083G10W@@t00GVo@ +@@@@@@@@@VFSk_@V20090I2B10G000Y000000880000044G800412000O_A8IbOw89sc7000 +40W000014GgKLqN6304000000G205001000800001G0001004080000aG3m@@RCf36d2Om60 +DS809rMPm@@F8040eZj46TA110000404020000G000WTSbJRiFr69_nmsS64fG5pCPmHJ6az +06HJb02000310I8G000G0010G00005010X420000PT0_@@D8200m0W0W4W0Sjt9000WA5Zay +fmu@VO00OW0004n4004K0G0Z000JKa040WWlzO000100G000G00BLO00coX4vKv@VX0W80is +X17POGvQC000W0040000030040000C61a1mPD0hx9NgL90040eD13IAaXphC0G80GVb60000 +qu00GYSdy@lG000G1004X11cHW0CAW00WTGIudI3G800aGY1008008000020u_H300uAd8dA +1ain@@dWO1000H0Y800081m4PVQ00002W0G0rFQ00G000GW000m0000280G200000O000800 +00OA0ASfe@@L10005W000200K082000000ApG40000fa2000000GA00H40000a2490008IgK +0C0000fL40WIvCeFXMEEDa@@91O00GWSC000W2808Am00A41Ye1ob00W2000vF0100G400qX +ZAW000U7Pc@@V0W80W00050u00C00GW8008822001W0C2O00YI0mmaW40A0O0G0M14GeW8W6 +10000N46028000W38HkGMeHb@@L1002414000W0G48000LY0WIW81001001220000G41W449 +0000W4000cS30acvC8f0O_KPcVPD00GI300WD00B0040002000H004G041w30GW10AeF0418 +0e0W8G4W02MA0601K0000EIYSg42x3208G_@76d7000GW7C3WJPA0rFGE94jg08w3FGq@1W@ +LL5LL50UuXeLLLHxF000iL_GYSdy@lG000WL00080C000O0000480080I4O2m4m589WEWVWb +ez0FHW3UY0@W41_1_1y3s3u7u7mJSFWd8u0000PEe0a8t9br_040000300@@t20sH400GAwe +30D@00ArP400088LLP6@1m@00WPCZWFu11@JL2cfC4KLgKbgKvX7eoCpGm7U0Wg200Wji@@@ +@@@Y000mJ300u@VRgm1c@@z6uQ2m9l5DdIE0001wacXD0I8CS300080000Xm000G04WYP89I +vDk@s001019WdG7uO0000gdE360pWcpD0004W020100102800000G80020I80m@@9000kC0x +4knc10002@gc0008W4vCG080mWsFW00000o0GKv600W004001800WOMDeQRC0040A000OME6 +YKmWYpDeHL3000KW002fgz40MK000GWukR96vpW1lV0300mVpHjwh14G01000WSyh10X00AP +d1000K8200_UrWcat00002040WCtDOqT60020000mwvT3020G08W40841mtqy0W050W00128 +010W8Y0000W820042000W@PNwaaY@30004002000W0v@@74100yGr91tZ1G000001aW0808Y +80oO041o9220100ZBD0@@3J3m98300WX00mAm9qAbG08000W00Y0008yH3Ait00004p7C300 +8209C4G4H004000004iHaAMns6440008H200W008008oU3a00000u4w@@J00G4C7f160000G +0200a4X8000002Wj7V0a00mQ@p0G0W0200000G0o800G1GWX80G8cP40J2L3080B02000@B0 +69a400100HG0_hs08000m820m800WKW10500mcsC000K_iVU0G4100XaGH102Y2H0008420W +f4b08000WAyHIYeE1G000000G0082G4X11pC70000500GC@@d00A5W@@j10Y8KFx6GA00eaV +3a000000agQS300ezVwO812O0000100W0p1O00000I500f2O0008WK0C8WE3Axt60W10000e +cZXX@hDubK30GJ0KXd7vBoGvx68400uuR3_Vt00W00DmRGWv6y@FC0050_@t00GG00O00000 +00O03uLU38000WH400000MeuRSGl1riR050Y0X000W0G000C00020m00010O0000WEG1H212 +G70041018W26HG0G08OfzB42W8WGLP00WjQCvU44R2000G0005WG00G0000W0004400NMR00 +8HG00G4000W0b01001G1920mQ@p0010H00000GXQsG01O3000014000000KR300WD00000cS +06KF4WK00208K0I8000WG100G0Y0eW01C0R0GlR884iX204YWG0m10G8wl107msT39at@C0W +80Dv40Ir3kZ_2CZgGuBG1uCU0mk@@760O600en6000guB50qCF0eC10WY_B20700000300WO +000mT000A0C0t1O0GWS6000100mDQW0d0S0000000mD00WVWE1qb0000S700uEmFmTmU0u0@ +000x1GK06ywnC0000006d0m9d0WPUWJcS2pym1sO30DJL0IL0004W0m@@j000cq400WCUj00 +_GL0yG06HVuK8j9Mv4MRs000QPdyknyoLaZQB5xM4WP7W1xXSTx4Uns0000SI000kD6ZZknO +kxVYtsWZXDu@w40810yqg100G0_4tWTkDG00000WjL0002f77oaLFixj1pQRmGu641h1tTZH +ZuC00W0urB6040H00W000C000m000400000840GG08082000028G0200K00000q10y1T8020 +0QvE11G000000kysWLnJ8IT30000ko690408010GiRB3W0088000W004uKS308206BU200H0 +000WIC00eLS32jUZEtP0002GVN6CKk100W0o0t020000842Y_RZonh00020H00000G00K0WI +vr00900020040000m0GG0100W000005oh3wH1xF001G8UT9kFFXfivH600000000600@1dGq +z90870uIHUcEmW@@JOYC3w6@aCsDefU3ktt0000800J0000G000oCQ7300A0000cWU00mmz6 +aIF3NudmSvRyvl1FCQ0000G0011a800H000c7fDpsR0W0000004HzdGz@6SnQ2bBJI8L9CF@ +300WW4100Ccl1CW00scN505005@p080083040oX04IA8XNcD0qm1G_xs4tl1nwR008Y80000 +W00100805rNBW000000100W04008302W800JCGI1CG11HKAW100O00W800000qc04GrBRKQD +60000100CcyU2G4H001000XGG008ZOEeg00GAOu@4w_o00800WI4040H00W8me0R3480000G +aUdk4Ip@X7nbO4R3U8B100400O0001200004X8G00e8H4K8JXPAs202040850000e0WKI1G0 +00008rMdCGAfWu@V30_NGrjk1hk9HYu6izV2W200Y@F1085K8000400IjwY1a2W0000000fG +CfVO0H004sM200W000244zV2001GkMt0000CK100Mu130020zb@mK19040000001eGW00W00 +00AG002Y00000280mXxj05020E000800048Q86010e14a008W0000C00GAK0030000en04W1 +0000G_Z0WW000W8FbcGrsFaQF302804000G0W0X00110K004WGG0060003m10G01Y3OGHfpK +S430124GWW4CPl1002W00020Y00eRV30OF0K@jA0008ATqWjQCG0G400000W404080002W0a +5d1TUhY00008n200WWG0m00G8wl104G2Kes64m0R0000GG800004AnD30000YHOB00004K0G +WboP0010GRhF000W40042I00WDTDW0mM006WDeG@18004X202W020W0000gjH10m607ntY@4 +1WW@Pm60UD10KLPi100eg7Y@F100Xm@@Z10@pW@@F100eg3000JKr30St80ua0yllA000nP0 +0WxWi0m1_100c300060nmb0C0uW4tI0Ke3000Y000_1G000MJa100004H00sqd1000m80000 +0J0Z000m1C100o2000E00Wi300O703mFGM04GsS9yzeDK500WH10gn60agPyA00e_xKI0000 +0h0005K00X_d3LV10L100w6100G1peA0lZ80_oHMU4p@C00OVIDVlK@b8isA00p0ipl1hAfo +CkICbG8L_o3000OA200fE@G@U_5@h4000St@FdeZP8xlGUsqW4mDeSy4MVE1080K0010grEX +JtV0KE9W00G10000zmb0008000a00W8000G0D@F3BcNnBP9aJe4rXd000WWOlJOkh4003000 +00POr400000W2000000W08eAnD0100000580020000G5508Dmi4xiQGWw6C5T2ndRGgw9yZE +3jhBHN5Laa536000000200140400000G0G1G0A0004000002108G0GUx6aKj100CLBPrWHtP +03000180000088100_@F10009VgN1Q00W_e9vO030004apV2000GIdMYZeO0000nYT60mw5m +000GKVI00IW8yV6EsMYl93PuU3AdpZgoI8oU300G00001SvQ3Qps00004000mb600SOP8zsR +GnMIy3E9pMMnuz6Sgh1HsR0000Y@fDW0000W00mvhD0O02000000CkLzgG20W0Wlo@vuwDW0 +800304uZy72ztWN@D0Km0mj@O080004G0n3gTjOl1Psd0008WQ@JuB_4000W4aI500801080 +CDk101G0RRtW1PM200810000W00W020G001010O0W0004W000W200GW00A8F100102400008 +kS4E6PbR08002028000800104ccg4VfkHLy6000meCUC0G0000c0eST3G000000e00040100 +4110I00G000M00G0GDSU30_w0y@l400WG000A1G0W04m0mw1600808I59MOtWv@t0008LtiI +4yG2806Y00004@k14I00U0m09a00000X04G0a0U20008i200y@l4W200G864a3k10GA1Qrt0 +8G4Wf2aGu_90021O@@DMMzXSvC04000000Y87C00GXHOu6Ctl1m800000000CW0400G2u602 +e000mcxxeRK_l1HWd00W0Y_mVu7AF000W2000G044GA0FSak1A82uG001WY00O4030308000 +E444e040c01G4e0H0W0I0G000W03000m23Wqxh0AWG8Xe88000080WWG040Y10040WW20WW0 +0440P@p0G00000A02200_N2ZtGh80U30W0G9081gWU600050GW0000110W0001W02000000G +200WNX00GQnL08GW0G0G88000410020W000W0040000H000000G500hdp0110WwSn0020Y20 +0WBBV00W000208W0R1084ooUB1a500000KG@0484IG9Hy4K00309K000GWv@@I000WL1042s +G102G000O0000PZ0W202AWKIWS9yqO20e4000080010eYvPkft000WAB@R00@lB0W70X9N1G +Q7Wz_z8HW4Y0F7000OlI@00G0000C000u200u7WBG4060K08000g00002000_100C3u2W045 +0E0XOtC00002g00Wuch0100k3O2K3a50C0300WE046k100y30000G700eyV60o00000a9u0X +00W74_l1m004sdc100d_VOlHdT90000CJCvs@F1mdE0pz@JusmSkO200G00000A100eyR600 +00220Xe8n7u400yxD37V@Gmu90040O@x7k0@XRmLH010mzUj00uODhlVoLtcOmJ0840myoF0 +880fqw70no0aAu61ZdGSQCaFO57hJ2W00000W000WG000WCvj10008008000208oy4EbrWOp +P0000gO00W4tD0050mhu64Vk10200EILYa@9vOO3khFXrkPeg73_@t002400800MXnWEpD00 +008001O0400W008Ylt00480002000SNZ000OJS3wBF104e0ridW0WW00G000002EOdXar2vk +_4g8dXqtJuxL681000004uv_4000GW000400XmysC0oaGODT30088Ktl1000GYJEX46Ou@@J +cHwX@@PW001000G0W00G000000mG0008eXT3ggF1W0040500MPF10009000W000G5Tf1G000 +0010S8l1b@b0e0000G0GG004UVNY3x@PfjM008IFH_3200W800020009P_4kAdd28dfOV3ot +Z1JJ90Ne810000900020G0000PAI00uf0sw_N2000OQ600_@d100300000G010O000P0U6k@ +ScrLj1000uUrF00W6iTJCaC04qZV2@RLnkgK1080W4G00800WIzP0G13mV_6C4V200G00G4I +W1K62W20GNv6000000C1GuhZ5cb10080Efd1000CG600_@d10K400O4002AGG0071W01Gku6 +8000uGLp8020G0008sj7008eKb832GA10100020a2Y0aGFz9GAe0O8tq00K802e8AFn70OC0 +y_l1G000Y4F10WWGNw@mfvF4zhMG205WCe11002AWz4000GAD22OaT380000082000C00GG8 +1008JeR040W122YHY002AfygO@beC33_Ic100LDj@d0Y00G00L0000K1A40iZY10W0W0008K +hY1FXRmKoT1008p8400WG1WwPJe@V30yv0e00000800180000004YiR0W1805gj114mMEuF4 +vSQlcPGpzC0700ukV941WJQ20paAx2GkuCiDzO000GD00Wtyc1f@d00WCv8_Dm000Y1W0078 +300OF0o5F1O0C1m0W3o1FXIi7hRwA0FJ0afd40C20rD20wmCs500StUxCyszIdvh2000qC7a +ev8XIbUZYcDuNO6swMYxsV00mdJTnUSzE3BDfrCxU08h1uIFgsWV3100400W000H0ici77X_ +G8xFKDE3Vi@pQgX40k10002gPt00G080824008000809_y400eT2004OlT323tWoSPOsT9Y_ +NbLrh87S3Uu81000W1ypmGz6SOV2Nsd0Of0WLuC8mU3Ikt0G0400040USoWrE9f6V3w_tWXb +Vu@VF0GG0qdl14G00wsB10008tsPGWy6000W64080200WnDDua@Gg1tZXu310020W00Wmis0 +04000m8WAsDuz@400qP@Bk19xd0G04000440008sWt0G002B_JIKSdaVU8vwM1WE70W000hs +dGmz6y1C3fUIL_TU0400O_T3w@t000mCQ200UL@XQmlglDI000Gqlh1V_p000wM0000rxR00 +00ezICuZdk0W00G000eBvAU@q000010400sQd10h60L7qI_w2zam3F_p008W08000G000100 +GavV2000uf8000002gdV301010000000ZmswNDXf1xQoGKvIG00We6C3A@F100VGW040sTb1 +u000200WQqEXz@IBIoD0lk04xj1WoC0G00008W88EH@ocj222W0000G80000000i4S3Upehg +V3va7900uH6CV2G4000K010YG401e0HMcW5X_640008400qUF30HT0AktWfvJ0G80001GWYH +xAx1Om0800000I800Gsy60M00m0e1IM6lzyl400Stp@F100AoL_Z1004Xq4rAWSC00W00002 +0200mZqC0A900000000YB00C1G002W00089000m00mpy64e1LG100MQ730mFW0000000e6@F +3000eD300y@V200W1C000KFIZ000000K9dVcATX@3040WKij10Y00G00G0020pyEsnEs000W +3i00msjfLKiD00cDEQtWZtDempPI@4ZgpPu5D3sFt000200802001G8000w6S3IDtWnoC0G0 +3IcQ90018G00GW0000mUZ200880W00ijj10080I27Zxh29Gz4MXXXogCOvU3YWt0018G00W0 +000880200W06nCJC00010100mtv9W01G00221000Q51000GG2M1t0000G4080kpE1G00000W +0sV@100020001UdFXXLD0080Gs_64Nk11hRG__6yLk1BQR02000000e00Y08W020G680200I +aT90010G0300G08G000001800040000Km000WHG0000wfO0004002qGl1Pbp0020awfPOg_4 +oesWrwD8hZ4QUD14000nv@Gjt641R2Vpd0000eAMC8mU604G0rPV20100C00008000mL0000 +268W00LdR0021mmep1101GbuOa@k1O0000008W2088JV3El@1000WhBP06W0WqmP0000cq00 +WC@D0W40000200009402SE9yaH_J0W0200040000YG40062i200G2jvpGU@6iN_30G004002 +8000102100GGay@J0034000019000x@R0380WIyWf@@40G4H8800ORKFExdXWxD0G00Gn@60 +080000404G8000Y1G000YUd1mIH0buR02G2010002020W00WC26O20042KdXDuJ00W08000o +2JV0000by80WLJJW0001320mizDOnyMw@8Xzph080400001G0W0HvRm6z6004H00O000G4WA +sC00000022G1082u0KcC89000Gquv@400uGG00G030WW120984G0G006G04408Y08SUL00W0 +0000XG000X0002G4H3jNHDd6004000G006m000A002420Ard1001000G00002Y0Y10002041 +00C200j_d0m6BWY@D0042004W2Z010A9G0180000G0OPV3A@tZ8_DeeT3G4H0rCh4foZ1200 +0400GLgP00WaG00500100sqs00G80Hbo0000Mm300Bc_mcj90010O3JF6zm0000G00H00002 +G0W08@y72KdXc_b00G00Y20Xm@D0049000000GC013B10W6sX7t0800muwU000W00G000W00 +50000014_@dXh9COiV3oyL20080L@nmYY6000004H0Ge@6yiF3WsV0s_t00G0H0000IDt080 +0001W0M5b40W20K000cxt000104WW0I0zaqRPOUU6MrnWCwP0000DP00W@@D00X00000GGA4 +00008kp4610000W80QjDXmsJeI43QcFXZeP88P3m0024_l1W40000e0q0W11j_GUOFKyC3tr +OmDgX00W0100000180041H200GQCsZmtOOj@A00Pzbwl1GMV0s@F1mq70lid0Kv70WxE0lwO +0000Gwh20x@V20iE500m3ORi98j7JbhZ100000C10KyE3000050004Dh1nmb004C0004jm00 +0wgF10LB00C0C2fb1000uW10008000m0G0W1W102030006JJR000G42000VaI2W900WC020O +0P020o0K02v@VF2Im0WxE0HNRmR26yxu3kZ00000KryV200YhNLm00WS400L_10e000Kv706 +0GKO76xl10ET0AfVijlbOOzAI1l2000aQ500wAsZoqbOjB3oJt01000zad00G0mepL9YLL00 +02s5hJ@@N1GW0Wg_99HRC0aX0q0CC9fd00G000W007ad000GWdcFffPFI5t00400zYR0000S +V300vWRmhD60080yMU3A8mW9tLPaOLcsEXRmPuXT6YN@100vNFbx1200W8ph0100mJ_6aeb1 +W2004101Cdy900O8czVZFzb0u62G__60000CdV36wdXzxDO8_GouMbhunei262at00W00LoR +0000I6000fopGtK6azG8080026CXLCC00q00200esDdyaW9RIu@b8_F9Z@F2v@YK_V8c@3ov +@@@pve@P0040CHA3Pp_0OR6WqxP8PB60008Kj@6L_pG9@U0W000480my@6qGS2X4Rma@U000 +80000100041300xVQ080WWJHPu2w7_b_Xwlte_U94000G000OMy4w0mWK0O8UO6s8@100100 +0Sb100020002020Oc0900W0eyQ3g5WX@7GgIxDM9cXVYP0S60GrsdKk@32001AvkYSwJ0800 +W008000K00010G00004008xE30m000000OKQ30000W0080940Q3l9i2j1jWd08800000utfQ +mf_6CXe1008eYskY_dD81w4s5t00G000W001G000Y00gEV3G811I22088S3_ps00G0088020 +0H10G000W08Lt@60284000288210028040W0s7mW1CCW8G0000W850121cR00WeQ0004KW00 +W80025000A00nKy6e00GG00W1000120G09rR000W01KG0n@P002A004K0RWR0028004080PW +002000aG0G000a042WT0D0210W020awwD0110W080a3HDevS3040000W0X00021080080000 +8A_mt0000601000GX404200018000000PE00044400W000W000030010010C0006000400G0 +000WGD_6Cej14X0000100420W0400200WpACW040080802002heR006000440ZpR00200000 +208W00G00080W008000G10Ge00004000140100100082004aG0C0e00sQtWjiDOjP6000mQC +00uzN30a20S5X1DURm5m6a5F3GW04cPZ14000ZlR008W0G0H08420G0WKiBl1VzRGqpXW004 +8ZU3a000ilj1800Y018GG2Y0u5p4010000eIjER9MilYVyPuGm4000000H0etR30002zyT2O +021_sdamODuwU600414nl1TypW910WkyQvxoA000n0000100GC0010G400pzAHtrL004GOwt +70W01010820180000Y5zJ0000Zt00W0HjvDJ3Au@10002000Y00W100W0GG0Wmh9U0410080 +WGU@FG00m8fy7EorW1DJ0082Gt@Ry7X1Lxd00W000410R@R0000820000804m00000G2WWW0 +0G0G804009wdmtyIG00e0944004000K01RsR00101844400440100W590OK@40Ww0aYz3000 +2g7mW6xV0030Gj@6K_l1K100CA0084000e000000G002G0I2GG00AW042W00W2120WZiz000 +W202800GH17cOmj@600900534gAeeaj@P00007@00W0tJ0004mD294yU5rZ_m4u600W0W841 +006400C80264W841W008000I1GzDXCoV2BSR0000001G2000I10KG2020uw@400y9FCv90G0 +80G2000040a82000G821100010840G020001218400008aGA000010m0W08gV@4Ucl5G004D +1PGm@6KdV2W_B0Mq@480008200002Xe00000OW10000G0060GKH11002ZICA503UJr0eW80f +NKnbfO00018pV30G0005000084GP0C0000YJ00Gr@aCSk10040C08WA80WKW3100001Y10W0 +Z88OI01G647a5020108enyP000WIejR000011080800WfsV00208O00WTqP000Bsw@j8000P +ZT3gTt000Y00Q0002G0000002GW2G000000zA00G06A0G000um232wbacaC0GW0B0004W520 +ncd00208W00001U06@@44T0100040W048400002Gl3080aX2zEWWGG6A0G02010100Xe@200 +08GP60GMV0aGJ2000YG40Yasl4000z10000G4H0o000GW1WnzP0004GQtC0000VngV0000w0 +00G_1000400x2u9E1mh1000h000t1g000m0020000G40Yw730600nRR008000002000W1000 +h000INO0GA0C00GrVeT6A9t3WC000T080_1O0W3u200W1000S000uE00mT0NWx0C0m0w000Y +2WWCOOoxGO60000108mS6IDFXHxDu@V30yB0q_l10WA@2p_ayqhe6V3ym@0KmT5NzRGkzI4q +D900003IHY4gRf8SIMNpWidbeK@4E57Ze@D00mI48GGW@iF1840000001400LfdmK_6aMl12 +010QGnZWkhObRFAPt0WH104010YD@A1000tYRmLA6W200OsSFkPl2000Ko420IH7ZQvVO9V3 +QVoWntPehS30024y@l1200WMlt0001402G0AMt01100@mdG6I6800X24000W01000WARvb00 +080iG00XSRG4u9008s4000040012W0H0000kbYXPqb0m00mIzaW028000G018001G008080H +010W0200Z50W14G008O008008004W221W05GmYP60000n00WW00W0000XA2A00404XW03OKU +604u1Czk1G0W0gW@1000120020004SDV2dbR0080000G0W000K010i_l100WOggmWCzDG802 +00G008004Y0400181800G0200a200000020H0000011W0G0G00XG3CWpqDGGGC4080024000 +0e150000003uHU6000mvO020080040WWsxDeET600020040uga4EmdXDwVeAB3_lnWDsD008 +0008000480TwR0KA000m02G00400040010000X04GWW1cCuRV3Itt0100CKYG0400WW0W008 +01o@@600GuDCV3oUmWfvPe2C6_@tWe9C8Hy40W28qw@3v_R0400XQ@V000Y1OW1WmrD00W00 +0G000W04tsb0044WNVI00WG00D8eT@JucU30@f0K_V20001kbtWz@bO229E@7Za4DedF3408 +0ycl1n5Q00000012W004000X1G000080100XG2010Y0W2Kk_AXryJ0W00mRY60006YK20004 +0WOxD080G00090a000djpmGcCSAv61VYne_600428KG3800800G000020000m@GDump40000 +0IWH00000430004W0200A_@t000Z_L@Rml@CSh@3p@dGW@Li9H2@@7YG01aX_JO6V3UkJ208 +0DG000G0084843WZB0ocC10W0A0Y100120Kwl7hvbG1@6aa23HbQmiM9W000SwV302W01B00 +00aG1080000W04001015400X40WWm00001W0400020004000e010eW42GT40W8I02300X40a +5c1C320Yep0W0000G3Wm1XW0004Q6L66@mW2OPeiE30000EbA34001kNr00840PGQGf@6000 +1000A8YeG0098X040Y0HWa02G0WWWK0000O0400804H00W2e0C0G000W0810348B44GaG000 +001u00040408G000000gdpIr0000104W80W00002AiLM90018000020G0GzgCyxQ2@4OGsh9 +0G01epr40500000020018H0020000W400k3b100800GA4sVD1G000FzR0100ojDDO@V30wJ0 +4SB30G08wxuXi0IOZN300G45AR5@@p0200YwUVej132wbX_6C00000G40WfVP00GK1e00XSU +P0000jp10WsUPehr70100K_h1DJO0800gsWD0400mWmX0408u@V300AW00H0WW020051WAUD +8W23G2000104Og438000skh18844c8q00001b1R00WAfmTVuKM66KW1000W0m08WW000000a +00000W0WutIupM94000000Xw@@40G40XW18209100G1aRLD000GW00G004028H400081qWL2 +00XO8221CA4300000CfG4SC38080A3mWmWhG80mW00WW@@nOas4_CoWUaD8U53090004G0eO +P3000m20020GW0Y00000X20000G0G0000810000200eaNMD00GW420G00K00nIQWD00WcZP0 +H20GSlIe000ufL3o7WXOvCOmhDoTB1000400@@0G4H0000W02u70820E000eoT000G00m307 +00SKZl600000@04000WA_XA00WW2_@F100Fo@@p00GbV0E00@@B1Kv7W@@z008hF0_8Y@@J0 +00N00040O001PJP0W0000N000C0C0K1O0W2m000WHMi68000d1G0C2K1W9YC0002000C000w +0m000e303000006000G100Gv20BOR000P080G0W000W100CXD30O00scsW6QDePE3ocBX8IJ +eoZ7Igs00W100000000O49j100WK5GL042a40GXx0000WA000Sy300000Kv7g00004GV0000 +a100G6000KS200hmP000820u70000_100Kz@F60K500000u100u@VLsps000027WpG70Ey@l +7000Gr400atgA@@BK6F6Kne1xVRGthICIz300iGBBJYApn8XSI_@lN2008TjR0080000m000 +60ofEX2Zz0000n3uC00W2e8_7sM@X1CzOOU3MNsWRVCefy4_AF1000W001200100W041W000 +0040401W3HRGOx680014W00mcu900W000mUq7z90W0K0000402S4W000ndpGzz9G0W0u1PCW +00Wack105W0_@t0001Wpod00G0A2000aW02GX00W088000W106WYpmD8_N308X120O2040W0 +002402m0880008G2jHV2Wx400020W0E0OqU3kut00500V_RGAS64iZ1zjdmNs9K@F31tRm9@ +6K8b10190W000qzk140Y00400Dsl105X00W800002W800IC_6000418010O4280800W82W_f +tWV@J00005510040G04000402100000801mvf6Sbl1G010wdF10808X5Pm7cI0W00uGd46Ic +XPwP0080W0G11040000010W0A09000C0W00W20083400W06oB10014u001800022408LU300 +Wgr2R200W10400004700GGmc@CSlD3vsNnD_6i9Y1H1o0000IG040HCPGvsCq8Q2t@810G00 +802001G400202001e7U30kA00002Oxy4WI000400A@@Y0a00000000O2mUw6CJb14100shA1 +0100vU@mVL6WG000001200020804W810000J1O008v@7AqUZUEbOnEC0009G000G08C2100m +pdJek13MfAX6vmOHS3W4244xl1000NQYt01002XpdGKDgi@_600G00004090000000Y41W4l +Pu@G3kZFXvvOOXT302080000004020I400000Wa60oct00010BfRGNC8XY21003M3G440W4m +CWW00W8G000000C00mrv600200C000010XYRP00W000002a0010O010G0aW4A4WC584000Kj +20000G0006004000400240GWkoyufzJM6q001m4G10085088000uYC30G0000OG0118GCa6q +m@3080P801020e818GG2Y18210K0000000SH32000282000W080G02G000081WG108a2Xc0F +100G200828240Sre17udmRs6CGB3BZR01000I10e00008W0Gy@l103J0Yut001905jRmbZOS +Ts3Tjpm48X02000G00GGJ60A40u2U3MppWiwP8x13000W0030000W04400004K0008mB0208 +00OAU300HGKE_6rsNnGSOqxU2W0000004A384444820880W8400428080GW400000enm@F00 +8m1041000W8G201401G010C01G000GHulRFKEN29_N1HG4Wn9bOnOI0G220WG000W00060G0 +80Wx@RmMuI000M21800500100K0802000W0G0000KM20W80Wx@J0H00qiLjKIU2n6BnHl60J +Q000i108B00m022DbcGYRIi_l10W_0oYp040022001Gq10000G0000ff11WxSD0020GuRO4l +f11qPGI_F4DW4x@R000u36000Cu760uKJ1mF08hV6ixk0qLD640m000WP0WheYVg200a100y +o30400000mFoy31kKqDS6000281E308000O200e3W002030C04XlPGYRC4zV200e200m5G5G +6WA0CGK090C708yD300010108OHJ364kYH1au5WBk@t00SU000W9yy00gcQ0qa000000Gxk3 +0fpO0000mJsDe6F90OZ8a_F3W82050004DZ1VkRm5n6q1U5xidphtg8000eyU3QwtWGqJ000 +0x4tIKR_6pLMHZvLShd1zzAnNjOiQR2TczGPU9aAG29bVIPwU4UNKWYT0EeJbUxDu5C6E5QZ +LkU8p_4Iol204008800IEtWpiIegU3000mX8000000000GY3wEPe9O840G4eD300W0010022 +00OWV36XqWCCC000G021W0G008W108000080G0u@V300mO200GG00W000W000500100wREXP +YguGVC04G0qJF3G0004G808000100GW08000G00FmRW0B04040109W20008G00A114000000 +8G0GeX00gzs0aG018W01K5000e020080WW2002000W3N8800000W209W04200amjPOdv42yF +10480vARGlzFqsi40001G004008W00XGW010082000800000a0080G00201L40000W0WZ0WW +000006000Yo7@6G022W2160G0C2G0008W108002W00G0000iS1008400G0W0000130800G00 +miv6040GuBB3gsd1a000V_@mr@680W0fvV6wkZX1@P010e000G01080XfRGz@6000200GW02 +0W1800004G0000805I0eA93IMt000Ms0210000GG08eOG93AytZzBVum@D00E00000020Cmb +z6KYU2reR0000100120Y0050020100G0808000H01W02800BlD10W21x@R0mbJ00WW00054Y +XFXmuC8CuA00G0zwfA4010YmtWjyJ823340040022a000mL@6800GG4001041100e0JPOmiw +6W080O@V3000Jm7000000010GYgrbOAO9oZ1cAnVOxV36_tWgvD000020W400W404001Yqt0 +2089t7@000F3080800G80048i4o3xoXHwnX4rF3G1100600aCF3bpd0040800410100ozEX_ +WJ0400qepC0W_10A20GkEgCmZAm21000000X245004oW69GG00040G810000804840C0a0O0 +0281106808I00K2W4GW040GW000Yf3S3GG0004000000bl1W0A208u10I020AG004P0_DsGF +XdO9PiU30mW0KXh1rMRGjz6G00mW02Y00201Y002020I006090Y40Y8G08G10080K80WeG20 +000K80900qu@600ueW012410002411xURGHzR0G0WG004n0jj0Af0e2_400021010009851e +00000042Y4410000104200004I8G000080f000GkeU2jpd08NJWsRF10008001WD8Xf5V300 +04XG0000O00c00WmtC004XX000C0000GG63100413C000000401qijD0041me_90000sD805 +0GGWZWLPC3L000001C00C0000000GG0eK000xto00OG2@_R0H0O2a00001n0K00000O00180 +22Y1Wl@D8qV6004Vlvl12202UcC40020VyRmDld0000Y010mN79iwl100080800igf18HW0Q +4E10mAG2G00Iwt02000NYPG8S6y0j180WW6_cXe3CedP90L004@fA1yR0w50100080f0000G +e00180004004WC7000005gT01W0440W040200002G@1080mW2r546k1nvd00001000yIW80g +xSZ4uEfpU9000HSqj1JtBX62008hF00WV0GbV0000G5000000wRV100G50000We200wJV00G +T_60W_x7W0000WnG_38000000m@0w0Kv@7AOgsV300w03RRWW00WRwD0u700G6030S04000C +000W1000t100g1m0S7W10E030006000m100WA000P0K100W0W0ELr000000cK000W10002WA +04mXCUSGd1hKbG8tXe@@0000ydl08YhpJulV60OA0azM2a10@QHt0KL0W2000EAtW6yO0Sk3 +00100000uh_xHSx6apW15JJrmNR00mj9A93Y1VcuUs00800400WlnP0080GQH9qGk1004000 +00AW000G00GErIy5l1z@R0uz00002XPgLnevgyES5NY7olm6KmE92300ky7Zrrp100GGAy6S +gE3HAym2mCq6Q5HfO0000000Hm0000D200D3rCXTpmhqI00010000Iz_9SPd1Rbo0W00Yw@D +eqV3Yzd10084ZzR00WW00000WS00080H0001e4T3Q0@XnhJeXJ32ydX3oD00W2mYu9SUU800 +8YA7d114W000020W0000002401W0a0000402010044051d1vgP0000Eo63020106Bm0241W0 +201010080188CS3Ist00010200201000802v7T3cg@XrMJegz7MGFXDID0080HzuCGY00000 +0W80400080W0204200isk1002eM1m0000K400000SO3008m400G8@608G04010200G01400r +ya0G0000109000W004GasG2jldm4t9qSR2TjpGujC0000iQS6kFtWL@D00W0GTw90001Ayz7 +0OwK120000G0240000CW0brpmx@CSRV2XiRm3_944E3LF2JIH9qgX4@@p0000QU100dkd000 +440208G08GcbrZf_JeMnG0000A000CsRLczl20C1hBoRm2O6SSz6FYNHq_9qb9FjSNHAxC00 +U0eyV3G020Csk1G0G0YNlbOYV8jTL_T@40008S700QNt00110pv1p1J94CJB9kdGQx9ibV2D +NPmyxF00GY4W040C080020G800000H000Y4e@KLILnWmxt00G040W0efvn0G00GVZOyLF3WP +10A@t08G0808GY008000GWOP@AIkt01000Vtd000WWsGIO1xA000G1A018DGCott02100zco +Gi7LuR00uzV304a000G4w@VO00H0CdACr@d0W002000C@_@GEqI000PfiQ68060ySnCx1x10 +8mXIOn0010000400401f_d0006WZ@b04520200W_wIWW20m@@j0220OaVX_oFXo7D8v@7000 +GY78000000420WlR9vld4AoLY7xb08000000M00007U@mw@600G287S36HtWlzD0H2Gml@I0 +00HEtT6000W8002eE03_@daUoDegjS00W94eE90nN0M@tWhhDW_000z@7mpmR1W2A00000@z +30rTBnRm6am@600S3kX_1WC000408I4d1000We00008000G0G001W00A0200WAXXZnx@9S6_ +30P00I953P000JRgorsO00mNVaH380000Wg0OkUIA5tfMnJ0001G_pO0Cu0eGdP6Btce8z8I +S60008C@V2000Gv301yP_9XzR000AWmvD8aV3UxEXYr99BTCwps300Dv9aho6_6K1A31cVIq +vaKZ@3@DRm@@60qW0ODzMcbd10A00d1@mgcg4KV2000800K0020000G8010400040u020W10 +0z8j100W00000h50004G0W00W100000W0LQAo0000G0G10sldXDpz8VU30G00rtE9Lrd0040 +0400080G8s9oW@@DW800098000C0180000G01080000WMn2@604WWX0000200040G0020001 +0HCcT2bxd0028WZyJ00H0G56C000e0400msb6KSF9H@RGnC60A0040H000002000W000G006 +H8W01ebV3G21000000OZ1000020C0W40A00004O4020G2000008WGm0j@R000GX__JeZ_4gc +oWLpP0000200090H003ggI8_9qdj1W001G0000W01W0W0000WbUUC000Y00002R300W00000 +01_Sj1ZkOGTv9qjl47vBHy@64Rn3Vh6oNrF0G0G000G020000080W400ULtWkxC0008J0_98 +00000820000aqtJe3830280q_F38200QZoWxyJO_QF6hKYNzDe_x4000400C0W00018W0Wpy +JOfU6CFJ0U1E300204180a@l74000UtmWp@V0402GymUKXF3ruR000010m10lyR0Y00W7yJ0 +0W8mWUCON00Ox@4gWqWDk31080000W00G0HzNmmcbsqUk4PLy0W000009LTLo0400410021v +dW80014142rrdW80400GG402000020G0098MGCs6da8yJuqV30010GW00Y440GsV900W1gx_ +40SM0qyl1000418080080W80YGy@904G8AHn4080Y02000104300000WS00Ge00082ivl1W0 +00Y@FXkKbOpT9WJ000W081008000W00m000G40W4G8G2002I80002080440pER0W000W0400 +00WfAe0yxV2W12Y4Y0084008Kb4400000GGPUV682110022000WHln60010OKq4cbNYwkVOb +I38404yPF30040000IH0000084GPv6qSF30000008YSxl1TiRmjc6ClU2buRGA0C00002H00 +000G80100noaGT_6aNj1dvw1202WJhC81V6400000GG000008G0W1_DO@M3UoF1W@F4t@RG9 +S60142ew@4I4AX70Eu@V3010G200006G0mde6qFU273OmilU00q08cU3E3Y1a0000000m043 +W08O00GGmAF60008000Q080K20W2000eD100000600e00000WWQwDe9Z400000060400000O +GWorD00W200100CG0W400008BW20002400mZ@6aVX1BAwH9wF050000040a00W@@DG0G0G_z +9KBh1NwR0WN7W_@J000I0000K00P01fRmv@6C@l10G00000Gill120001400000G0G22mhGI +yWk4208GIxd10808A0W0YTBXC_D00aD0020Ae0P0004GIXFXy0C0000lZXD00004G100cwt0 +45000004Q0mWB2JG00000GWiaZPW0mM20E09e0P19apGH0Cym@9C300udV0GWC0W0000000G +k3000000TWx0CxF300gQ0000000p00005e00000Ae00000O6W20eW200O6G10lj4D00000YW +700W700000y@F30000GL02GvOC0i8YeyUCW000izQ204000m18a3k1n_RW000K3010C03023 +t000S100K1W100030AeCE30C000_21000H008p088Y0m001820003000e000H400Y8W84H08 +0W0G000m0008A00G4200HAG4YK060u0g000x1000700G4100a1WW820208eSE3USFXY8teqV +6kUp0_@F0xvdW300WRtP0000iW00G8Y000mC0QmF1W006P@@00Gb@_@D004HKd2600u1m@@1 +00000W160@@R0003W70EuLjJoZE10800PNx1uY7WxlDuJT6410020G08XT30020yLF9bQ@G8 +rgCp13du_GK_60000Jn00mS_6ydl1plRGA0CW004exR9EvoWFxu9SSL00qjsglDZd7I9NjKU +_3nY@0uO700080008000W24aU2820GI1m002000O00m000Sm_3fiBHFvRy9l4L_@0000YT@D +8ZT3gpAXQvD0000lb10W5tV8oT3_JMYQmJ00W00004WSwJ0001HvzySdl18000Iq@XMxJ00G +AGIxCG0022800qX_Iibl12000QlpWFwD0000XG00YSDCe7BIsQQZcPJ8I16YjF1mW40jn@01 +W0WEmCe8@7w@n00040ReP00G00000X008800001G00PRPI000Wa8l40040oU8XK@VeN83000 +axE00eF_40G00yEU2RPl1800W0_De8V3gi4cw_X10W@MZ4a0108e3_7I_tWCmb8qZJsyl50c +B0zBpGkT9Kc@6dc@0G00Xp7dfezJG200000Wr301mx@Cqdl1JtbmxqC0400Ow@42E2Z4NivK +UF00igbqk4njlHL2H5U_600G00G8000000uY3400000WW21@R00W1WLFI0030000G00C0005 +01QtFXYuDW2000G8000400020001220000010Cm9v6CfGHVEo0000Ua1187wd006000400Hb +PGJfC000003100G00040W0prWnP6HXK00W0000001000avZQQGGZRyzl7pRrIjmjKul14000 +0fx0Kqz3xtRm0oFyXi1f0GHltFycC6vslHmOX02M08Il4_@FXCxDW000Ghx9SrD3teRmzuC0 +000AXvPorFXS@3nX84G5ICy@l1WG004108y@f1d5OGmy9000YelV3Eht000WGpFQmKHCacy9 +hWknOX6izl100_RduNYggcvJhAgc69G7080000001GA1000000f401000008040I1GYy@D0W +10G306aWF3f08n4sB10006019000082I08x4OG706a2W40IG0kAqWZyJ0000K306a2m35355 +0W20I42YGWGa0008218Y0008XGW824Ya4f0GHK0dKHZPD3OMwzg0w04OR43Ufm0W800DTcGA +0F4a0U000e00W10040i0d40O0G0003850AY2uawCY2000902a0WG48240002HYW000GW4822 +09mK0e8AWJ4800acHK00IY0GUY810000vv90000GIad0Ga4I1WYe0EH200GR6s7V0_LnX42G +0000000GM06AEXJtYQrkV000o2m700000Bf1047eF0xmC9z10008BeUv00001@30GM0_00GX +DS2Av08RmbkFYA000GU700UjSZ7sF9FAj000000u@jhnbQtuAGz60HAm300WWFqaeFEd000m +GL000008Gs@CyqP5@xRGse6KM_3GO00gpadQ@bOP06000000WR9T@40800awl10008014G00 +000140Glx940_34800G0040G010W80mT@608W0G000uPlpSrz37uRm3_C0EC00000020WW_J +JuD03I_sWb@J8NM3six10010000WG0220W000000u6kRK58F0000z500Sa_3L_d00G0W5@Je +uX700020W00ehS3gatWl@DOjmYEbEXi@D00WPzP@CqTh1dGpmjVUqxG22000G004KhuLAYK0 +2g6ZowD8DOI000WK_l1T5EJ4NaG800emw7Qa5ZE4te4tk00Sc6EE3DVpGxCsCfGHxG@08n3W +WdVG0080800000400100000WiQC9Xyd0000qFNZ20003N10W1mJ0004H526Shj1f_72000Zu +@D00020GG001000LxNnpvs000KetV300a@4wV28400U1m001W2B1mmQ_UWG00002a1000000 +5GJDV5uV1W53y8lUIQksWRcfAdS38F00q_F3C80000204LU2ZOdmI_R0004uXY4GW10SERK0 +0IRok@XaJWPVO3ATFX7fN2041mx@60ie0eKU6800500000245mf@de4000080010040G0000 +M00G0WTuRHK1002QF1000O0700_@N200e@_3GLcU@ae0EPXYM8000KnV200KvNbd13W00002 +0008000G400W80800W@y31000Y100O483080100020CBSBtyV2em5Wn@Pm@V1Orxy0W00iVX +J_zTZ2_bGw00GbI8LC_L00eI3D7ZTuh8JZ4oatW_rDOHU6_hxXFxc9tV90vi0qyl4xgFsrzg +000Ws@00m4yg0040ewV3kGEX9yJOmUOU6FaUFC000000WpjkyV8cT3E4@XLkJ0040GywCaTC +CnMBHut9iUz60HF0o4ua_mD0004000a0000004O800G000W0I00180Y1000G00082G030aTu +69jNHwx9CuE6000mOA0WK0I8xcR0001WlsJ8h@4000400W0WK00maz6e0008x1a_Ds000000 +06vIuNYkgz0100a0000004m0008000m020We_V3G0002W00OwQg0lF0qCeGVKg50000000r2 +600ozF704400W0W0WO0SMIN00YtFeI80000001WY2NB0C60fpp3810YqRGQjoDSF00aPO5Xf +I2001G080m090W0002LwXA1_3300tcx_vX0W04O000q800000eIXNBWrA0D4c300GXy@D8bz +k000G6In6ZDJ200GmPd1300WNS@U0G10O0NFcdUCGW00@@d3000100e8vx36000Gm1005xM1 +800aw@310a1m7l6CePN00UrZxd7500Ly30guN1000KvFkUj0MX0CtF60Y00gXE400G000m08 +200yqd1PuSL3tO000HikQI0000Im30000ym@@Q10uHu1Edk4dA0y80NalHsvRCOk100W0Y2F +Xoml2000gd00WlqRvLx7kM@appv10GXylVvyjk1HXdGfvFym_3lilHCzC00080040oquF0oz +000WWmjxLSLc1HQ7Ify6KWl7lpNntzC4Jl1NUd0016WmmPGY000220W@@P020010WGYCxDeV +V60001ieV55ePWG02040W0nhFJm@6qyl1020000020000vfz400800080600WmhxF00W008X +020000200Gzyunvx9000e100WGraCaz09VtBHH16qz@3WIE0YUpW7@JOY_7gKt30040jvOmF +S94Xl1XrVIzz6iR@3J8oGEy68800uR06ch6ZwNJel23sCC18W00tHR0040m7qD80@4gv690O +3VJS_mLdX00100804mbG90002K40000W1WCF5gcOC0ic0qu@CNHRGPq9KhV2Y000E4Nbknhe +XN90000bQ_30000_RmWoVz02000001WvVDe2O6G400amk1RdJogxLCyg400Sdpp@1000WHmM +10G4Wc@D0G50008g00100W00Y0202X00aW8080WW0040200W8YG040znU2no72G80W_sPOrV +3MObXy@D0e12mx@900024012GzgU80000000e800000800820020000W00G00GD@68200G00 +10000200WG@@VIK0X0000K500m5y94IF9brR0bK2000000G90s7F100W2K20000G0iol1003 +029bae0810mU@w@C00208mMFM1t00001vWR020400G00XKRGOuCW100TGyG000ei_w91mNne +sO000G1G00KWv680H80XWG0280WykDueV3G0GG0U00eQAOw@s30004q100USzaewD0000nGu +6GW00HW00205000200DjPW00001GW0WD00028ey@V800a0000055W1v3x1006oBTb8N@Ag1u +1q700000KGT004BU2000gR6F10W16@@J200egK_91uI0mT@j000o0000W06O00MG10CG000L +_1m03mC2AW2A00L10WU000f2000O200O6WmR6a00mDuN39o2rWePs0004KFyR00W800WPWW0 +m0c100630006000e20082e2mCG408WP000HwbtWfp520pSJ_@9000Qy@V6O2000W@@10c1Go +wO83000Y8CW10O030O1A0m3sZp0000YG0000G4HKVl7Rp@GszXaAU20M90kSxdK_VOce7W00 +0qZl1Bcl10G0WTRC81024002SUU2PuR00WIC00202040IWVZ0kIe103wuo0000Wt@RmWwC0X +80O8U3_@ddS@J8hw40_704FU80800_DtWHtDe303oFt000G0jQd000GWotJuQx4wUA180007 +iZ1040WejIui76QYt0000G6608QqwX@HFvyR9000G00108iz7oPt008G0FnR000040001000 +2000gyDJ2hZdmrx6K_k1Fad000uG00W8000WM6F11010fpR000184000028W6Zt008000080 +0a0008000001800400W00000He00W0200W800qvr6W00800001G8008080bvR04000000XnG +O001004W000WG0000G8G00erR34000WW00W000X0000008000W0400400200002W000G1000 +0vD201008W0000000060000004e00004080804000001801000800040010W0WW002mq06W0 +20uoC3_5p00400ViRG@z6010W82@40080080000e844000080G00W08200G500W0WG000000 +500@@R020OagcC0800008W01400G001020400W800005P104200181000200igl1A0010204 +00001020008X400G0000H0W0400G008WG0081agrC8aV380G00880W0W00W00008000I2040 +000402Oe_4ggFXqwV000no@@600M0Oc@4AwdXj@J00WfX000evtP02H0Gn@60400v7A3UXF1 +0440z@R0028m67C0000a100YKxDOy@70080zH932000QfaaPyJeXV60iy0qrR8LwRGLzL4TV +2FTbGf_XiDT500WW0G0W00100002Gk@F000EJA00m4_ISgl1pwd00W4WX@P8W@40GW0q_V2n +uYHe294hh7luRG5WCSbk1040000eCsVV2h_d0W00XVAC8k@70G00K2d1PYcGD1FabS80G04o +XLYH@DOSf4gut00W80Xkd08722004G0400_@xX3zDOZUIkX7Z3_DuYV3QSnWAYDO463I@@10 +8K90W8100600W01e6F30X00W040W0W000004b380xM_0W040050000800200s6S200001008 +4mJ2n@R00e00002G7jQGy19Sbv32008kunWX2Ce@V9009000I000G0GgkCaM6300S5120W0K +800GW0mlL900080000400WW8xD0000480000X00FrdGSi9q@M2XK8Hfz6GA18O2GI82K0H00 +00600GzRL0Ga520Y0000XK2100A00084020081Oxz409000000Y000HgvO000014000b00mU +ub0001mId9is@6ZVR00W0X4ZDe_D3Uqa1000yw7310000Gg0m0000QvSL0A801002mTuL00G +00020G9t6aGx3000G0A000m00040004G1WyPtONm4w9tWAyJeKz400yV300410PWUsF60000 +001Gm@@900G010G0Ilv60O00u6O900S0008O9EO6kzE10K000004ct0Zvdb00W2mYx600800 +0AWIfwC0y@1eOT3I3o0000002W00000Fxl1208G13G000042010GeqLSnV2a8002lg2aL00r +6PGZlO4Va100M00G0Wztg19W@00002JJV0006mhS91W400208MQ1@100G00A40c_N20Gs480 +00W200Dkl1t9OGPx9SQMB00WFy0W0qeR5002S0000w00Da10000000x00000000eg0S5j108 +3HCm00q6j7@gP00c1W@@V00W8000uWj4D0O00msRCi3c1byc020005W00003000m0aKT222W +0g_D10yC00WS300OU1300060OmKZ6GS00u2S30g0G002m000W000WuOvg00WC000p0o00063 +W1Mc5Z6zIONu40m6Ry@@68hF0000_dGX11DR0N10Wa4yu@V6U@q05410PnzGOuCCfy3ZhP00 +04WW3DOXO3Qw_atlD000FuVrF4bS25cYnheX800W008W0C0a1800W81000W00G8028CS3Ucc +XT@b080WmAvI80000yU0Gtu6CMT2hbd0G0WX9mVuVP92ZZXzYJucu7QKZXeX99nx7000mZF0 +2uaSCUsEXljDOpU9wKtWbxV0010080W04G18AW000I4000W000OGW0010004000W0_6FXwkJ +umx46TdX2aO00WHSPvI4mb100GW2TN24000Rix100G00400000H008Y00020000nqF6y3Z1X +KOmIx604100G40002W0A00000W100G40000401B000G00080G24A80100840160000B190WW +G8800o9tWPoD008G42G002100RFOGAi6aNk1001G0000GW82uWT3kmn010A0pmRmBT6KSU20 +0X0Mhp0GK00000040W20028W04G000005W0080000003A02X01GG8000G00G1240000WHG50 +0G500Ihs680200000Yv0e000W00W00104000GA0WG0024X080W0W00008100Y8G0040X0002 +0004W8Y11W0W00K0105000G0000G00081GSK00000G0WI8W010W00G0G00GG010000010W02 +000300004W0MJo000W0GI004G00Szd12002Uxr0gCG00880W00W0040100W1Y8AY4qD0W20W +00X0808000KC0001000G00W800000G80G00W041040a121041446040G00@lR0I000204000 +24G340W11W82U3000IH200W080203AGG004zgd00008004GpFO0Y0008001nnR040000WO00 +0000W0208400G2006G00010800010202W0104001008G00eA0228140100W00I00000SC8C0 +W8O0W0opt0800900004G04KmT2L1R0W000Y02G6004ISc1400m201W00000011f2t4_@d104 +H0nmRmXC6W0000a040940WqwDehV3W0W0yll100W4AytWtrIG000W00m0000G0700shcXhvD +8CU300040e008e_70010KMl1tHP00W0WSzJ00040004e@EC00000K0800G0W00m0oHC1H0W0 +200W0060820000G0GtD60410002G00100020C0800Udo000020W008030WG00007yzRJCG0W +04004001a4G000004H02000401010000040200000420W84CHX1000050080GG08rS3W0010 +0004006mR_6SrO23mR0000G8001b@p0G0000010rMPGlp60G0182436Kt0000700G000a422 +000q32G8yC80000G08W10010005VoR02a0WyzJ0000ou@90W00GG0000G0WF5C00001W00X@ +@D0100880000240v@R04G0Y23C002G4044WI4D8TV3ktsWMyJ00W0Hyz6W180000W2014G40 +00000W9800000220G00002800284W00W040G000300808G0W@6D002200WGWo_J0080G8m90 +0WW8pV3W202008022060W0000K0G000058048061000K001204fH0GKY0C500Yh0020030Y8 +500040408W9W00G808umT3Axt0e2C001088800809W0YL0ZWK0000H1pTO0W08G0200Y8e08 +004GO490100e82480Y104000H10082000m0G00Ga004811PQ000004WG1HLR0C00GO0052CG +080040AE000200O00WF@D00H0W01C0GWG0BHQ0H21008e0G00040W0KXj10I00X80282IWGG +00eHe82a00000041m081W09L01100OGGG000WxG0ISo0000A010008W00n8001H0YOGG80WO +000q0X111CSX1G00002801002480480Y00048005G40e0WG4W000102020000882DG20WK08 +1b0G0W850850H8Y0a200W0H0qBg1l@RW00G80e00081eGGW0G2000K0G40000I1L100081WK +000H800080800000WKd_R0000Gz95000H0000I1Z800a084f00002G0a208X06100f0040W8 +0aI800G4000f0G2C1200W002PA0C0G0H000840W4080W0a20041900408210W01010100O00 +4GK006_9l180000Y80000O20m0Gd@6qOJ2TRd0G0840070004W0900iul1G800004A340AL1 +G0500H8W1G80W4G040P00i010XO80G00W4Ye0e0Y029010m00KW000400G108Y940K00WW40 +00O005G2G3P00K0WaG420620G01G006W0G40110G2O4508601400101WWK00130080m4G000 +i2f1W00W0100008W0000GZE60P0A0300844Y0182000405400006GGK00mNw60it002e00w0 +2280640W044m002W402m0Y0O04801120900G407WWGW0100C0W14000O8o0G0008100606GW +000H6G03000aW00Sm4ul1001P822W02000400611I08Ia22W08W00GCTZ1FuR0b000280A40 +G00000GW40030040W5WF0CuSV38020820000018000q0ID0r12A0820G0W44000008G08I40 +200X00908C258I210400qDX128Y00W00GW00X06000GG0I08008104824G008GW012101089 +04I180W010Y_00Geiv20Y0002m8082g520W0070G10800G002008020000r8000050m20001 +iIrDG0080OB00000AeU020288y@l10G0GK20709K000GB4w300XIcB08204A0X0W8uN0202I +SXU10GiH3aW8eF00020SXw00WeWm10Y00020G082q700619NGV008KIS10H00O10aG2C08E0 +WepC3HdP6_FpCyF0guX7Ys@00DLv704000000KL500000AL10y00001T300000400qm1W70e +vM3g@t00W2A@@R0ex60500W000007Hp8ILLHq7UWPEy0pCZAcPcezF0HJrgYsV04j3FeAPcn +CcHb7yGqFuXeLr3HdfCYMLgymXEuV0Y2m0HhA0f0OW@LLbK0Cm@00DL150YV004@0@8w0x1q +1i3e0e3G1GK000W200GD064h0C0G0g000m00008000u200m503WA060C0C000H10005000_1 +00K1m0W1W10E0300mU000m100GXRG18L038_1w0q1y3e0C7G1Gqe1Om1s1A0q1K086e0Gy30 +We3G7H7WEWU0x050x1A047K08_10Gq1yZu7C7G7GdG2Cu@V30007uE0000G1500tT020000k +xkBq0A_i1t0Pm8@9C@j1000e050G0000000Kip0GKdeup2uh@0mV@0mL100WUVy@6000k3S0 +000SmT0u@@040_101000qT3g000Otj0_@FWBbR0000G@h70000zXC0_xV01OI@4000mvk_@t +ToeF0AuV0070JkhISzRSQl13_R0Wt6Wr@b0214G_zI0100iIRLkzt000042014Ubc10W00G0 +10m000qRc1R_A1000XBgD86i4000G8Q00G010mWG6ybV2574202001W00fURmZ@R4eb1ThNH +Gt6qBE900OO6hoW9uUW200GnxUSoA3BcBnPw902080100m2SC00080050mQvCa6@34000080 +8W00GuUT3400000z08uA6cbdXnmVW000oduI48l4hqdGgG6KVk1W00GkEFX1@D0008080014 +00020G28020iPl108800W02Kyl1GW00018I0A100000kA00WQaIO_U3000G0080nG0000GW8 +aG00040004H00W0800K00100808W880086Nt00800G010A0o0GW00t@R080W8I000W0W00G0 +K80400001W82000L4HW00000020e2200G0W8e00m014g8080540008W04H5W0040G00400Y8 +004G820gG1000OY1WRyD000w4000218040W02HGK082201400020402000WG800W0YW08601 +0E0Y2c008208WG0003C000801H00G69G84o0WG0Wwqm04A00002O2Zt00W887AdmiO600014 +FO0Ggi9Sqk140a140802000400401100000800W00092G00100C800202I00G020100000Iq +18UU300I80204uiV308002810HW0000OL1088000011H00SPj14W0100210400mWW0002G41 +4O00009008080010002Gcv60040enE30Y40080000Y8Guz90908WW00208190028W081G0GW +0108X801224G80000018G000018X00G8000818G0W4W200000WR60008000W011004H00440 +W80aIk1G1000G0Z00002210YX2H40WmW0W0K800e0104210810040CGWKhvR010000W20080 +Gww_XI@DOAy4As7ZyDUeQ@4g@t00W8000YPX8020004umV30G000H010400W000WmVC02000 +034000800030W00Wayl104000H00000002200HW03W0000001Z@F1G00004006wt040G0hgd +mK990800G002Go@600201004mX9600G0uZE3G01000400501my@6uyC0W8040W020G004001 +040400040G0108082WYdC0m040000100110O80wzE11000hrR0G20WNFVu_JCUGEXXuPutv4 +AmpWl2CO4V3000000Y020400000OW3W0HuR04a00W020G000009010G640000K003W0W0040 +002W800000G082W0MaHzD8hF3040008004080Hh_6KEV202082edXpzJua_4000M8000uXV3 +00G0zBd1@kRmYg98I0000004G00000ibvzR083020GH02020000G008000080084040089@R +0000GG010W004G024C_l10800_pt0000200100W00Cbl14800080002W08dD3G000002K5G0 +0mMW9Sej18W62Iut00GG01FR00WW004008G10W010G0WG0008010O8KHI0410006CWG92000 +280001OY0WG0H80G20HX4244AAW310I0228G4W400Y8a00C0X0i200GH84120OW0GAvt00WW +G0K010K1W02100100000W2400C000K0083bMV25Ha0G41e4yPG00000004Y20000GG020082 +00G00G1W1800000W0G0GW0280O2XG0200450000m_a001YGW0OO61140WH0e00C50A1001K8 +4040W21012W8060GI0080I0a0G10I8240601000XGW00WYY000W0G040YW0109O000G44202 +0G000W14WK4084p0008L4Y0041WKI1G0Y060850G4H0000f0O0fa2W4tCG8C1100GA0090G0 +4f8000G9G0WK4414000485YW4200WKI1I400610000xAI1O4W0000WK82p0000I956Y0004W +Ka8Y05G29GAJG2Y000fa22HGG00Gg009a0000a2W0W800HAI1G400008a808000010W04000 +08bKe000000W002A00000G03C0K00014000OG00G0G1501e00aK0I0O000G0W8200K004252 +06I0G0100G00W2400cK00A01I1XGK0W28WW031G0800006SG00O910eW28540i000W020030 +1W5800CO000002Wae00002010m08041402H82050093QM00404GW0O000e814XW0000G0OOa +1cR000020G00W1Hz0C160441G04G00e05A01x0G1G006a0n3W0W1W842G8GCY60076X08WI7 +Wm41W0A0G0050002I100B0Qe04O0Q0D130000WW4W022m0WY100WKL0H2G0W0Y5GKGP00000 +HXGG8004OE6188110G0FAHW004WYG2WE00200I0e0I00K4a1e100mH02W2Y10u0GYW000000 +020GSuk14000O010BWG400001W4m0080002WaGW0800020020002K00411021X060400481W +1001000H0004K00W000900W0205e000YWDCmA0W8e4864m8W8100004KA1I20I200e00G010 +Y00W0K2W8080201G0a2I00000GW8GW0GA000400001210I40200W051gIt00G2WY000wid10 +020000wZXp0H0GeXjP006XDkGV000KmYTBXK0U0W0420YWCX0G80o5wT0Z00mK0W0C204120 +2H@DGc80b2000seftDC200J102n800a8084zt0HY0KAqVJA06WH006H084wl0H01OBH1a00G +a8084zk0GWWOAKVel10W0GW000G0wF00106KU8wSsC86k40Gqg6sc1KvX@0m@08ZPcHq@3We +py1HhgAH1mGWS60000000G5Ly300u7Lu70zXCW@100W3Op30gy30zHceoeF7uEL1000Kqp0u +7m1G5_18cqpTirL00mDgu700y00GdV00800G5@WA000wk100000Kv700qD000005vLG30020 +0083z10000009kbW3s3K7u7evib004@0w8_1q1q3I1u1YEWE0z0T0A0w0K047G9Gk3IaS7m5 +vE8BWSWV09nz0IYa300Wb20b8vE8HoTWVaxWz0A603a8v0b2m3o2e4PEG9c2m30AHo100WQ0 +00G0K1k3W007W10003000u0yjUB000gu7000070u_V38OcPGm3Fm@ggY@1u0FyWWggA1T800 +0ynU8603oPm0FyWW_701fA02ApC4qV0yl@0eALfILgImPCZWggA1pK62cfCgAJPym3oOcP8O +LL1mC@FiU3uF00Kzl4l3P000000280DxNnrtC47i1201060@10002000uy300CHE3R@dmNuF +ifV20400Ey@XKoVG400W4000G001vjRGnt6G108OOI30W0CG0008GS36Rp004000W110G280 +040200402G0WfZD8xy400aqCDU204W0EAB110G03aR0008WJsIOak46ynWpqPuvk7Y@dXshC +u1DCw_n04000GG00_JZ12000Tzd0uC2W_lbueU60004SPE31rNnmxC00C0uUO3W0840000G0 +800G00WeSC00A00000X6wC00800G08WVuJ024G00400K80028416od100W00008r400Cnj10 +G40sJ8X41CO@1600804eV2e000YmrWxvDeZz7QOr0000100G0001300080240WGH50202W40 +2000054Ji10W000a000G00050G00W102800fCR018IWZYCelE3W04000Gl3080010000gI00 +080wzsWXZD0010408O00G02A8Gc0802P44004CY020H1G0W000400W00000A008404W00020 +00804oot00403WG11000GG00BGWG8100e050040b80W00021010W5Ie0080GWH02GG88003W +0020220e10000480880A0040WY88g3I3800K0006X00WWA000myJ82e094I0G00WG4854100 +820GY00W02CG008840W0GG0024080m0G00002020000200C0000480G10W21W00a00G22200 +02a0Wa@D018000K081W0000a0G23o04a8G0A4010XG80S80G4W0W0G90W001202X0G411Y00 +WW1001080XBW0002W4000K00010GK20YW0P8000W006101CH00eWY100G8J88030H12W981G +4C8G404W800244010C010W000m0G1018a21Ia050841102G008082O0000W00W08G8100124 +0G48W00G44200ite140000W0KKkF30W004080A0210040C00W41G020004ces0e0003CR00W +W00e01PWRGOq64b8300meHG00O0000020nzF6000K0005W00000W89000140010022010804 +200G4O0W001010200Y00100008010W02TbR00G8Wm@J000GW0G1002400C00000WW0080400 +GYU909014002Iri600G041W08GG9000W808000WW8G000a0800080WsvD0I042c000mq2008 +000008000400440000100GG0200G0G800000X80mrR60008000W810WfRrD0000eW00YXmI0 +G00408WW3kJ0G00OYr9002010010I8G4a002bzQ00000W4G021216pt00401j@RW86400000 +0Z04012004280I20W4000800000WB130000018pn4cGs00Y00000KW000020n44G040088W0 +10820001000200YG1020008000Al_PG@k6SfY11NcmFz64bk10200080000800080W000Xzy +IOBU3GK0000400401mIz6W0002Y08GGuC00Ova00X0300W8@D0A00021WX4wJ0081W00000W +0WhgR020X00000G08WA1m0YW000W0W00000808OoO3wHn006005zPmcz9G040100080205GG +00VtOmd39yWl1024180W082Ga0G00G2_600200A0WnI_60qR414000WCG028Y40W008Y504U +W10100000eaeh100XW000X82G0000012G023G00@GOmbu68040W0000000G20200010002G0 +W00W808000W8100W0W1000I180XXGW4200104410X0W020W0Y80I202210080041a802WWn1 +10W0L9X6Y8418W200290410GW2I8WW402W28000OK80G8WG0D0W08YI40005WH020a80WY00 +40W0G8002W0064W2W0084900710aW014H90D0C0H8900fGW8Xa10G000W880414100428280 +0O400W41004410e2W002ZdyD0G12001KG840102Z241108m081GW03W0GO000W001W0I00Om +080240YOY0B008GG0GOW2AIX10AW0YW402W044e02e0000Wg3HC2G0W0W2O0004W6O0G0mGW +8864002GW10G061I3G20G28C8X8G00a0WC8K40H10K082g800n20KG0GWG848G8G0WI0W004 +0G00804Y00148K00A482000W485a0000IWK2G0000048514f800002040000005e0000010W +2000800001840000GW201000400fa00C1008WM90000G4G144@@R0GX6A4010800Y054C200 +8WMI1000070840YG000002fCI1G00e5b0000000K20WWW0004j04C000GKI10000084W00a0 +0000WG06800002900000A00010081eHV36KqWk1D0800GzY94fl1W4020004140000080000 +6000K00480b0G00010a00GF@600900000hf000Y20400008Q0000018@U3m00W11482Ka0W0 +00XA@D0W0G0eAnGO0W0naQ020O1000I0W0142K0100814C0000Waz7D01804W200822m0C80 +0G800005002008W00086aG070W000110H0000WW20Y9OD0004K7a6W018WZe82G1080124px +o00WA24Y048000000G0K000000840W1000122880G03O0K000T0GHw6qrl102002Jt00008d +xRGCS6Cdk1804A4081A8208Pn40K0W200004e0mWI600040A080001oSmD004amVo6000W0G +00WI00001000820wur001e89YR0ex401108Bjd0500aZdD02080821WpvD0008WO08280000 +0W80100001Y10G40008WXFD0022nWm90G08G0mM0001De0W08000C002XiB0m08X2glW0XG2 +20G804240000W500C0s01I50080110EEs00020080W02zJW0002A00404001000W501C0IW0 +000dym2Gku6W0GKG0004wd003W6Ae@02800gaYl1000w5W0108KeN0000aG1000000O0000P +109000AmM0000WG2C00084ok00000A000oq70000g08liA0kxzH60001500oS700800000m1 +tT00W_0dx0GW20WCw3Wnk2G000o000@@70WxE00tT000000OZ2Zp00WA000Pz1000SOT200F +0Imt0_@FWy@V01m@02000400uF00mV@3W@f0OGgrL00WB00WV0C0T0P1m1q100a5000S000u +700G7mF0N060e0k000P10006000i200K3W1W2030K06000C00003000x000S1q1m0e205WA0 +08A030gH0aBk1m0y3W105G700mQ000W100YE000T0g0O0H1W2C300e2000O000W200WLWP08 +Wr0G0Y000630008000G000e3W8G7GK0C0T00WOoDutV3WTNeYV00dx0000000300Ly30gud0 +0yhW400TtWi_d1L_10Zl2e@10W_mD8yR3yFWw3P000000WnT700000WxEmHbV8JV0G5@0WCz +10Wq4U0W00GA06a073vAyW@1mTW30@FYdm_s9C7i1FX@mKuIi7E6001000O@tC_9NbV20001 +1001jsQ00O0WrlD0304W00001aW0080080200W02W080GivCq1W3G0004001CQR200cNl8F1 +10G00004004000420200mBwIW00GuKSF0G0848S55hR0440WWyIu6_4oNtWfuJ0200GAi6az +B3WeF0g6t000G0fnQ000002401tjN1080WJnJOsTC_EtWyPDm00W00000W0G1lmP04G00000 +280020038K8l4pVpGmy900440000as10W4mPu5OCoB7ZLvV0100010YW8hD0000008G2I800 +NzP00G00WY0200004G00MZc1LYP0001008W0fzP06G02000W00W804000G00C9P300mWG010 +02000040G0WW000G08048G001OxD30001r@W140000J0Z0W0000H000X00348000840O00q6 +b1v5RmTz60008600402W021IG128009110000G0I00082W0GC00VqRG836W140OkB3000000 +I0G01000W0008000001YQs0W00Gm000W0000GV1004000K20400G0G0W00G21000100G0280 +0001A0800GG8W0W88vwT302G04SS278dm4y6KPl1009G0G9WG0220G08Z14G04023G0G00G0 +000101080a0W9WwfD041000GP00000W001cqt02010Zjd00102820100G018WW80040000fH +1008400K0000801800144H0G1s6010000G0WG0011210023010W004004400nm@60000H0G0 +mJo6qe03e0G0EasWmhC00W8814004G100002gQq08000G100YWmW18D00010000H0800000W +DG0Ha4G2H2c000kF280000001m000G04000001W80I08000101000X004000800WG0200002 +15gto00210K0H0Y4qWKhJOge4Uct08W10084WhBp012000880000020200G401G0O8080800 +063qy10W00I0404080S4d100000W48Swl1WkE0G008i2k1PVRm@@C0G00000WGH36Ko93XRZ +nx7F0G83000G2240G10004050010G00404A0001O1Wn_JOiQ300003001K0G0008200400G8 +02W00100014080000eAF50G028000004Dk12000W080jrl1VaOmFs6808086p7U_GYr@D008 +04W080G00640200001I0020WW00000G0040HyRmMS6Cl_3hPcmYy6CAl10011000000O06W0 +W080008002W00100W0W8H000000108000403vR0000ua@D8H1FIqt000W8pSQ041012W00G9 +0000C180Wm08a0008110080tYRGxl6a3V20W80Eut00I00HaR0800XgvJ0iS2mUM6W00000G +0W0002000GO00W_6bXRyCeMK96Jf200XW080401Y2A88m06580G008uG0IKI904aM1WA8GH4 +081031280840GH0wkt0004Y0008G40bI84G09410W000W00900000410001401000000IT9I +G0WK0G00008011100202G840290GH0W00000082W000080008208000IIrWgKJuCV9008000 +01021G809f00405AH000SKQG8E8GG2280mG200H02W20WO81G244G910GLy9G0000080W800 +0G85008G1G414Ic0A01aKW08G2H0102W0000SA30082000aY6Y028188G210C010Y000800G +Lh90a026400YY00WXwDe103_B23Y000zSQ01000000800W0100W00fW120W2000A0G000001 +YMb1000242000W0I1200040050G428000aA2WW800GAe8Q2530FxQj3X1qA24X000GAj00Y0 +0W4aY0G410080f012H002aYM0W80W40G1WP000000Kc1W8000G1LBkC00a00008IAT6y9D3t +bO00020W0WX0G00G4000G00e2s70W0O000008WC000844106A0G405HW0C8A00002000C000 +H000e0700e0D900000mCmG0G4800m20WW004045O005c0HK616004400G10yzF303000000m +G00Oy@4O000CwV2pCPmjhF080040e0WG000000a9WmmM@600WG0000022080e2OGY0n004WX +0000G2A000X0400000Ie000eX8Y00GGm2W4q020Y2W020G5422H1140Y100Gb000Y00XW500 +1410300A0G01404e8G02G0G801WG02GPT46Q@t0082G36L14D0Wu@DulO3WG00i_l118O008 +00010000W00a00100W0020Lli60W00WY000eM90000G00I0Ucn00W00081009AW0I2000G02 +012WBYD000090200000ax7RmsZ6qdH2PBp000e400009GQmKm9WU9808W12002WVpDG100mW +o90020100001e_00108G0s2W800A5040Y008W0G0mM2W82mK000Wu2w30Y00eK000820m020 +1GV9066U20G8410W4b2W10C5O10Y00mG000820012000B004845200qDC3W50040OWicb10W +HuS700mFP0004KGIS600uk30mTN7094TD3000mZFp0y30Ly30oq7g000ar70WxE0eYV00000 +0qu2Vx10YA@TQ@m0SOikD600m02Vp0w0G01TR00100WV000k0T0O0O0W1m000WHER90000t1 +00GA0600G1I24NW49@0SHS1o2e3m5G966k10R7Wa8n58HYBWR4NWr0w0k1KYXXp0YBOlK0I0 +G9IC2IaO4m4n889WG0J09na0IY43mIy600W98iN3W0000O200St10owZ0Kvd3S@E7000E000 +WJ10Gc_0WA_H0PwJ60S71500P000m1mfy9000y30000ar70KzWWnWR0LLvV0an@0Gm7yWWP2 +00WXSF88LLHGggo3EyW7yWApO61@702ggg4CJP8uXEeALfILLHbPcXWpC31LT62Uu14KLLCp +X7uV0KnCp8e@10Gg200HWN1008W2ibOyR3wVhY3DOu4T900WzK1dGrR@W420XnoD002WGPu6 +80W0edc46tEXzobuoR6cjsWC@D0u11mnTXKPc4x@dGprIqYE3ncRG9UXiRk1TXdmSs6ahU20 +00mpcAXUzs8aE92OR3G8K08001G100qvk10W14000GKhc10000AU9XRuPOykD0000000Xlzl +VgX@100m400m0ZTs000W0G80100WK00000Y1Iugz60W00yqU3QjdXnoD000088W0mLvD8ZT3 +8800GG000ua18500WstDW000G3f6aWV27wR00G4240mW@EQmiO60G0004000030WsuJ88B3_ +ot0448002024G1X802008a0200002G200G0IG20GG4080G08Gap6G0000140GUK6ihd40020 +W0W0a4b1c100wo@100K0nSO01080W00G0W00AX7ZMPCu@@7WX01O600020K04WW0840WO4G0 +81010Z8Ym086800A206GW08W0RKnWo@D0012mz@90280Coz4G0000400400000Wtpl@J000G +0000Gm0000G008010008G00K01000010G40K20wksWttDuOX40000W3008uC60002000100I +0W00W040W00010gvtWX_JeRJ3wwtWofJO5C3Yyd1000G0W04oUm00c40O000oU8XHraOZU3w +zAX5vCu@V3_9pWTCJu@V3000G801a0G02m6@600WC10024000G100APYRGmbj00C00000Fd1 +0Wt5nu0dMkxF13C0002008002qKc140008I0000100C80mAds0WmgF5M92QbXYryOCiAgus0 +0W000200W10W000001G044020000W00WGs3ba_nD0200G0o606t0OQ6d0000001W8uk40000 +2W00W02000200W000NFqo3_6000WXb00GxEO4cgDO0O0C4800802gKU3C850O40W000008A9 +0W000K110UOzaBtDm00000WgWwMzuOB6oUu4CW10e82548X080L0GK00aG002rWGWA9GY004 +CaST2BzvnBy9W000a0000up1WNQVeeH30080yJ0CxxR00a2G1000I0000GW00W4aY0H0mA@6 +002I00G10000W60C8rMFG40045W100mG000mKPV2n0aGOGRqbB90X0G0GW00A0829000Y014 +0100800002a0Co03NSq20W@fcUteN6Cczr3m000008WG0OGEah10K00IP8XDTC8BaGcptW3L +J0W40mgaCafR2J_dm47m4TS220100W0G91G1utJ3s@tWtYR1201mSu6OB00OFv7sRncpnJ0r +IG0G01WzID002HcR0e00X283nRGx_6a3k19D42000400m0G240004Y73G52000EwDaBdtuqC +3Wi_0G6008AV3I47ZGetOBS3000004m0etDCeI10KAjD0@000O0w0q1m007e300G7000uHUR +02m000W0073R0006WMgy00401008fmmDGp00GJqC43W19_Rml5aqhk4600uS700001WpTk3E +04O0000000Wk10000W3k3q00GDUFygD900W_om9g1mbesK3_1tZNKJO2O323d1WGE07XJojq +ISDD600W0800000Ha0014nBtFCTE3LLRmoT98040e1z40008iWE30008z000SyT53kWHjBXi +ik1RnoGKwRaKG24001Er6300LsBFG5008G8001m010AUDXaAPugx4QWzXfpD8RM3cAc1mBB0 +tnNHwyFKRA33NdGgvO8G4100040H1000080000410010G00ym_4kgzXfsJ0022mMv9aAl1rb +R00008s3045tcG0u9aYl1TZP0004WmtVueIFG00000I0000G0W8W0440001008200000GY00 +94000040W0HxeI1u6008V4100mB@ICtl1Xm9HYFX000202140C000000WG004H000ETi10WZ +00O404_V2@kZH8mCKcU2WZc0080K4fm37udGYmIi3N2Hnl10X000002u100W000000m000WG +Zu6i_R2PFWnCYL000WL300GLzOC2h1PF8n6PX048YuqhYMpt000o9Xc55040W3zD0WG0mAd5 +9KX1Otpe0000204euBpGYXBas_D0000Zk00W2IT2520m7Y9KVU50001_pg5001n9fw400041 +088290W6ZqWvMh0010mRVdKDl10l20cSr90G0X2W00111G000Y8TU32FS62000TnR000W000 +0uU100Q0CA02000GA2G40000f0OjV6MksWK0U8juG00qx5LOK02A2000004W087S9G800Kvs +C1XWqj@900510A000X00000A0G000Gm20qOU2JdR08200000000D0Q0M5Z100r2xKN@602G0 +ea@462EXnuDe_GO00Gx5xHKA104W4A0G0000070010f0040Gvddmg_6a2W4HQx1Wf7Wjme2P +z1000GWDpCO0QRkFB1000Cc000Uz8A000uE0100mU0u00000O00007Wv@J000SGA0IyUS5Vz +d00WGfehTAFT300000L00eGRa01z0C3tLh79KPw9aXJKPPJohfCSVP8004SJAmiqTtO7@G0z +50izGNzJdGnuRy2i7000OiA00yrJK0400o1zXQuDuwIR00q46BSK000202000400100GGMK9 +00002G02GM_s0Iy0uo3g6Ft00W000O006rt00004dXQGFNm000WEPJFcZt682103XpGv@6if +SE00I_7HfhAzPOuiS0ax04CINVm_Gj_6KHUB00WGPD00KFALzj@m0@6K5dD00GGIIbgduD8H +XAoSV6G90055SLjyF0100u1ORYKWAG000TFaW000YsiJe9C3I_O60003vmx4000A04100000 +0L2002041KG10b00WK0C00W0b40Gfnm9vz@70Wx0COVK030000H0W804TAx4I1mWBND0H00G +9f6itlAS200Qst920W00W2H80WYW0K80G0A020H4G0008G8WG8G00Y0000480G4000G01t_h +20WUtNhe2042000082400pIQ02J00G008h6pGutj0g81OePd00i00H00K8000410G0100W50 +014WXa203R5QmbHg000WGr00GpLrzEmTb@R0WIaO4a8n8W9YHGI0X0c0IY91a496eK0IGI01 +0c0Any_R100lP6tE100cXWgg21pC3py70gggCKLL2wX74KcF88LLHG7Um3KLbgK50@dFFC08 +10sUO_jnnOCpP_@t000nZHAy@QxFaWSEU000QNZgSiR9oVF00ajVVSK00000a0GG0G0G000q +5w64Zh10200sgoca2YQ@V3C0880204ucV3IRFXohj1000SkdH1G0080_4w_tWPu_100FTGA@ +@3p@zuy@EG@dZq@tGzVDM@F3s@nez@BS@@4cG@@R0Wf2WXz_F1tSc@d100D5H5Q@Ez6ikz3R +xRmSzC49lAk100MrViT2iv@V3004nFe@RlXF38D6WvCp70400008W60CuHXV0GyY4xH_W000 +Ay810004BL_GcYm0M00O5Ng00100008e10327XXxHc10GdvIFNzsw3tfp3Ww3WehZ20G2000 +G00080W0018000GA0IOtz46dT6000qw600gEAAX0008240a10Y20G01000IA064mF3n_t200 +k@azZ20W20006040200G10G00000400u00Kqxy0oQ0OPVd0G00GG0000000150280002Y00W +002000W0000ud@s000WKG00Gp_EXe000W0u00Y000208082Y400W007824008040WrUj100E +Ko_E100UGqPcXeLL5FaP6_70Lym3HxV0Ycg00DLL1000m@X_R30G2WEAYY8300H6G6YCWC0T +0P0A0o0K041e08Y10000830D0dJ7t@lH_@Pi@@5z@Nn@@3w@Vqu@@i_@Dp@@o_@@@@@@@@@@ +@@@@@@@@@@@@f100WsB00GltFa5AF@@@@@@@@@@@@@h800mNs300Dx@VTe@Fdw@nn_@Rk@t6 +y@h9@VQqn20003q00m@@FSFkDXP@@Nu@tb_@Rn@VM_@@@@@@@@@@@@@@@@@@@@@@@@@@@1a_ +@@@@@@@@@@@@@@@@@@@@@@@@@@7r@@@@@@@@@@@@@@_@@@@@@@@@@@@@@@@@@@@@@@@A_@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Vf@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@yWB40_@F40W00@@l7000CX100@@72100W@@@@@Vv000GClmC0000@@7 +3000m@@N400WW@@r20WN@@@51W00u@@40400iinC0100_@73WKF0@@x4000e@@T20003w00W +k4cvz1s0WLhz@@@@@d90u1W@@T20GGv@@d00048aYJ_@NK080X00000G024xnIBkS200G1G0 +00@@Jo0H60140u@Va00Ghy@lJ0004030020W1y@@b0qh0y@@90060_@d40a00001G102Qy@F +I000eC100y@lJ8w62000800X0On7a00y4@@@90W80Y3Ih@@b38300G6G600WC@@N4000GV00 +0v3eIFK6y@@@@@hOYRj000Wbw00G_NXy@@ypY13GL3W85S200Wo7MgCxr9E400_@dA400180 +020010W0280000G306W0080100mFR94rs900k3_@FA1100BiPG2040W02885Xa700y@FLG0W +0W0000W00eYH3WG080000G00WW000W3vIeZgJ00ivV0OK04W00M4HSInIWS00_@t90G08O48 +0G4HG0000040GmzUCq1W1f0G1080010G0ZdW13W2W9kY2020000G00004LxL40008@000@@x +404020a00P0o00W00000GD0OGA0KK593fCA100041200@@x41gH14WC00G000G010020000G +GTX600W08W43I1W240010W00BECXj3P0000dO00W@@T2W00gG4WPC34001Ge2TyXM7V8506A +OqWhJh000X_@@E1004w@V68W00iiQ2PhQGA0K0004Y002m6hO00GKu@Vd000Oqe93@mPmMj6 +S6t33sQ00G0A00000W140000020Gu@@A0N00y@lJ0W18sPp0W0800002m000010063W02010 +O0G0800040010010G00030K01mK0I010010G00030G@@d0600WScIGM00m@@EbHg10001W00 +00002210W00080W80200000W0410400011A0G00044851O0300080002000W000yyL500qd_ +@t9000riX02m600q7h1YWe0008001Y2000204082008001W8I1G2041P20WG04A41200CaC9 +0YD0y@lJ0O00TU00IV1UMcPKZQKv1F4v@08QLzGqPAZeLbAFafC_70gym3Y_V0I1W2HhA0WM +LL0000uV00u@V60C_0y@VK0@000O0O0a1m00383G1G6W208050GC00WO0P0n0o0QA0IG6GFW +CW20T050W3A00P006bJY8NRv@VIG4WxG40@06t100_2g@@BgDB3_@@@@@@@@@s3gL8000qq7 +00IfCgrgtuSwP00CIkQEL3bpGyqUiP_6@@d0uH1WTw@FdVrHgj0Cj@LJklah10WrPrQm@Y00 +m0DuFLxHPGCj81oh1O7_y10G0yxBI00mhoQLh79G2Wt0m@@H10G18mUdIpugch@40000021W +E_N2Kx3mSrs30082100mLqmizF600mJtKdA0_@1tzlKCS@Fq_@1r@@F@D6Al1r2Rm0o21gg1 +ezehYcP9F200@@VrqL8108qky1m_@N8G3C095y900WEs100Lc55800elrAQ3Ejg2tWb2M2GV +2mo_E10O087u4YNl8000m8600wXFAW00W0200c04900v6teS5b00W__H20S1m8SH10000K0G +GI1S200G10406432004411_N40WypyZf2020nT@B10S1OPVd00i1q_iJ0008MuSfs@J000O6 +J00Wz_H20GTPEyH10W800WP04000O0003_N4ek7WNFZIW10e@H0W4WNQM7ENLqiIfB2Gr2G8 +r8LQD9jNF3000Iz30095SrEqXqx@900O4gmbg6kL9wQI0La0aVSNfclHtvd0000Ls00GDpuX +400eoPI00SbVsxLpuom@@@0oM0u@V_1001z@VH0WKhBsFA02000100_@Nez@J00e3mo_H10A +0SJHdIAWA012W00G000045uVH002wtMFA01e0W80GoUOfuZY20010000C4GgI000GIT79K00 +0@@x42820000G2W00MD3fi7Y200W00G10404G00008e104idb001000H0000O0008mV@5100 +Wqw00GCSH10mPvagY_@t000CW@@J50@@70000_lA0YpqoSlCWm5W100Gbi7Go300Gp_EP000 +u1W3Q__@bp@Fvz@lvk8100030Q0020WXkVu6GF00yJbi@L8002_@t010G02000IdnWwPC8vL +O0PJ0y@FL0004UJC10001HAymeYISOv6000G9900y@VN0W0080004ze1N4am6xj00WPy@Vd0 +00H00M0100GW400WBAb0W800088WmuX1KM3m@@E10Y020400200e17O0G08O4I6000m10004 +000dU7yu@V6000av200u@@e00WWy@t300080G0GSFH20410_@N500T19xJb000G00008YC0_ +@t00a8000800848I4n041G02H42WMDR1mY1mo_E1WP0mG0G4IGO400W8q100_@t0J1GWG4W0 +0L4Hf28a2m0YC40LejKL1000O2WH10G109000f00WqMPG00G20W80000828W24W0W8W828WV +L00auz@lJ000bW00H0008a200m@@900Y0G400000WG2100fpE3eF4WmmZI2WXu@@F0000300 +0G7o600eW22000GW2WWcLnZ00mP@EP00060GGe02000KG39Yp02028Gm20002W010000088t +UL00WtS8DL00GW0200i8S20800QYp00W20G00040G0010a8tVL0fE0iilJ0WwG00eW010Yu@ +V60B082000100W80448000i0GGWW080ashAS300Qst9BDXjYHgqy0U000fzeV@70Wg@fx802 +00081K5WR@L10G@pz8H1WmF00XE0T000g080@@R000210J020k0c0S1P1e2u2G8a5WG0uS@L +10V2mo_E10e00000eFCuB00mpvmbWT5eFc9Wrk2toT6L_BFohd0ouF0Y7WWcL97UgE8lw6nz +0G02m@@UKB9IPRwnEwU8700e7_F10SvNbELZcRm9OO0200OyyM0uJ04SLK004023t00100xh +R0200000400W8W00G0000W0000400W00010BOJ200061300@@x4WW000200fcR0G00attOG0 +000800WmpJuYtJ00C14lEL14OGXzC00004000O7x608000W02W000WP@F9tpe_7@@_r@VV_@ +pt@@FV@lpu@tS_@Ch@@ox@RAJbS@L1iL0mu0i5QcDA300_@daVucvAQOs_7300CibvT5002W +njJ8sw46vsWehX1C50mIV25_F3084I0I508W000140000005000080000901000084G0G004 +0200LczmWl9GK008rR9000GOC00Of1d8GWGO008W20W0401000m0@@R0804WQpD00G0qgmIy +Uz6001000OqVg7I9hdmuR6ShU20001G008Ckk128200G00SV860070_@l2G9D0FY45020W8u +J04W8G6pF0041uBU3wX@4000uK700wuEA458G4080002100WG0004O2sF0011G4O0GhXIy@F +60WW1grBg35IOg_4ArF1O0903yNn@@U0SO18jte00008100G49H04040008WLspm5c9a8z30 +G00Ii73000aq200Qst9000J8Y2200G00H1K02014G1W00G80p@R0004G00G44820G0G4aDR2 +rX720Wzk65Z2804002I918Y8200e0W60GY80eK@4G0G000G01000IxmCiok120W0w_73GvF0 +@@x40I00GGA00WWaWWH0000IGI20mTpCG90008AfGepF0000v4W7o0z1N200zr7b0G400IG0 +G0000004010002G1Gy@60028000802000000IxTpGMiU00WBFPVd000202G0W2G000W140g0 +00G080020a_V201O000802G08uV@4000W1200eqMF0Gf0iiVKC00W0e0GG0G002201000080 +0Yj@R000GG800042W0GA09aiV29TR0G00000H0V@ZHYqHXi000W0X20Y0002G8082g520WSo +x30Wi000000500O6O60G00StB600_OJst9000pYmCy4XSoHLpm3erp5LPE24vE4u200Q@t0P +a1000g@lMYaw@P0qY3GXhH1q100u7e3mEG7WCWE010T020WsyU220008WA00We085W42btWS +xD8506oXd1A100DxxqIu6000kpTVf0W0000KTtx@d00o0WHwDmpF0mxpC0W20000CpsK6S_l +400IYous__bRf9TIy100qQkzB@hIn@a0el0ucvesXEXCkVeWRFgx63000Cu000Ai7lPPUO8U +C008T7fWMTRxH6tg0U008y3ykn@1080895WXW00WEApy@V300G@aile8rM0MD@@KtvyClGcz +l5GzD0Bx7Lze85_O2_500oKCgBCzu_@700a0000KuKrD00SAczmLBk2pwZR0cw0eSje0400y +pqC0008sf53a000Fp6rP6E5qs3nCX4W01WYQR1020W20000m00@@N1G56W@@j7000C200W4f +L10300000200W8@@N100Ll@@@@@Vr10K4zTiGrtuq@@I082089zV_EVltmHQIOIokp300YP@ +@JLksIKkd4jih2Gh3Wdz7xrQ6EkMYbay8ePgIkwaBtL10mDIScpts_Fb@B100WST100rmz@C +U@l2dY000000KhcilJ0005sn9A0D603s7r@tUaKmX000WRxT900rbhK8AWk5WbzT2049GbYE +100W0_00GZqp30G6uEJd0050iaw@JfgEWH6Wa28Tjt@BFl800zKbWtrUlRKxh4L@Y10Y0Wau +nhG_7Ab73000mPXrrtxLyvhA@@R00WuZeh@@l@Y000YoE00eCy@7J@@mu@VfzA0W000008ix +VC0n10y@lV00001004zay695G8WW0W1x39ev@@@Nbmmt0000YK10Wgh@FCyY0IV0C6_@7agE +e_5WbzjlGSd00G@ailS7gAHqrU0Sr1uxcn_@d7000q4400Q3QiBQz8UTF008ea8z@7Q@VXu@ +Fe_@1o@@V_@@@@@@@@VOs@@5_@zzZ4mC1WRo6xDw7MaEX1v81000Timm4JdJxiH20WbshyW9 +zjPAt@X0_X14D0m8ucr9z3jXp0020W9nJeTQ340G0qGT2000Gi400SLeMXXd0008Wz2b0410 +Gqz601W0ehW7_@d100bKpgVb000000087hd0081W02U0000oqUIime4020005f0aCBUNnd00 +O0mUnJOEU3cL810000000Oq300i5yL9dNn0yI00m0u@@400W8S_l400ePcatWB1@9SzD01W0 +0000G40200000000H@@V28W4p@@JmX02GeWOy@lGW080c@lYquVORV3EtFXF8JuMV3000meQ +00uvHy00a0qSF3020000001O00O@_700KSVyeM3xR0GW0001009FO00W0Wy7P0C00G3064oV +20Y08_@t0015G0860_@t0GP20FFGroa6yZI2LpamBl64Fp300O0oe91W0208081gUW1000Gq +400YjCXaQQv@VCe000SAQ20085I1GYjHP000eK306G000W0002X08000000G80g181000000 +4s2l_gJSDO6N6I1W200010G4000H4010008040OW040W0KWY400W80igR2004iF7LB0G0W3_ +c0000XNUC01W2mKFC0K0085030304810000Y0WW02M0G000Y0G100Gq@h1WZU0I5t01000V0 +ZqEF94Ci1d1P0020WvECexrD000W20a80400000GWOLD02000000Ub10080W0MSP9a100pic +G70600G8RhL6QRr0W0I00000W2004bi18R00000gW_0008WYIKu9K4W1002cA3mW@@N204HK +306y@V20GL00GL0y@V5l0OmE06000O00L100F05p0007va0m000G0D0@@75H4004H044H040 +01G000G000GKA06W0H000800200WK0C000000Cp008o0m00301000300WP000YB00aPWA000 +C0W10000Y200O6000e1TC0G40GhoE1F00e103IJ0Z85g8N16060000W160W1Go_6000LH100 +m@@i56MB0_U0_@N50808fUGoYOjabT8000ea300SLUTt_h200Ra7mTAI1FsaEXyh3fiR60V7 +0ylTN000GYfIYnmVeGS3skk2000G000Gj900yyDIt4nGXzX0200uTl4UwAX5yVubF300Sh_E +UHDg@mACmW020gXnD0XX04fGKl_n0000ei7gu3U3_nXXXuV000WGsv60000cj00mTK8z6fDb +yR0000Xm2De6W7001000ezxH@k6rtWLzP0080GF0FKiI80YL0_@FgHGV8AX4Y2WaJHV00800 +000e4NKfHgPkrNY6QsOxVC00qiz@FL00W10000G0060004Gx@98W100008m_3FO0000040GN +06qe9340W1ksp08000WIF0Mpag0CPe303ERD1100020002zqWe0U8DM30m00KoA39f6o@@42 +0uxSRKaopBXnyIuFF6I1uXt6D8AWAsKbXxzC04L2G3S8bu43XPj400008100@eGrGQB100Gv +@VmYH9a@@31W92mmN8jmC300m0_@7ZQ0mu@@YGUu1XKW2255f5K2mB292H0p02u11aQwi800 +0X12FY650400W03001d3010eSLF0002aoQK@@R000l000K1408@10GmhIW00040m10300200 +G400W0000v@10I40G000W00aG88Y02H200000W820_@@18Y0000008H8G822Hw@VL0kz0a5a +Djoym@@6006Dv@@@BST910020C000008020000060800G10O0f0GHK0aKi1L00W0H0841a01 +00WG4H80004814X0G4OW4a205H1G2G24WGiDu@@b000GY80oZ89000088U20000IY880Y818 +92019Y40000adW000009HUc2032IG0Y2uXK0OG200GN9T5en@@Xy@myp000WGY00mjq6SE9U +@@Z1z10008BeUv0000e910GM0_00G7NGcK038uV0IA0iXO@1000AZ10WhJXPUlYYDsWl2b8R +L900KsMmw3hukqlGh_TA3vSp0200WQQP8kx7IhD1000u1jRmrr9KyT2fNdJ1hC0200uHx4wo +DXy9J0410G@_6G10000W0000040100ht@0W00000eXR@Yn4s6iVuCWW20G0000011080400A +0WV@I0G0000044G400e0200GG002204W00000G040040000000K0000008Wq7w600W0Q@@40 +UL00400W40GGMwOy@@CK2W00000040WeR@40023ykl102G06Pt0K008406GYDt00m00000GU +@t02G10z@R00X0W_@D00007c00YzmJ02G0GZnF4yHEBfR090OWy_V02W00021brrD00800W0 +000W00byRW000ei7CeFP60200000_OPl7_k69008000010e010G40uHQC00GGSSF3HRRmq@I +0QC0euwkoWN20G0000W0000010400420mIx6W00000101002YVvVG000000uYKAD8kV3Y18X +@_J8XsSkdtWL5DOYyAoem0W000Z@dGY_6a0l400AA100000A0fysh0000200287y4UstW7VJ +010400G4WszJex@4gud1G0000CL0g38XmnP0100Gal@0420000040O6eqeV0040000W0100G +00104550aRk18000001019W0eyx4G004000001G04000UG300h4aGC06W000AdV304004tSE +1@R028W000018280MDd10008000e04000G10GG04W009Y_jJ00W000a2eq@PW000000i0000 +0090WMH@Xj@mOaVL0G010000W0Q1m3yC0II100085f000H4104200O60000X4100O204G800 +0a000f0G200300WKI200G40I940G82400000Yu4000g400G4I10400HY8W000W80002000W0 +WNnDG200mz_s04c0O3_7000X800000W02000C00590GJ000K0W40q40020G81004200040Ga +c00A0012Q2W2004m0W0032Y0000RKG004400e00408A0A00G02000C0008000H1004120000 +YsttcCND001H0210Wv@J00m00000G5G0100100g30004108844IG004Gm18W20W000p28W10 +0020H0402020iW4018A00W100WkX2Y0400280a0G000800200C0W000c18100RbO00O0W@@j +10H0mh_IG0000040a001080GW0Yq80G01I8G408000W0884e020000KW041W0DW86W00GW00 +a00001G10000Kp200600G2q02800001YeG00004000120882WXk@11X0000G0KV208W44_@F +1W200082w500Z0DNeN000AqS10H0Ge0O4041r100G8X3q7002bCk0G400K0420HW_00G8Wx2 +000QlGM000Gau20H0001m8041Y200W0W38A40080E0W80OGTO_@F1000L00000m0@30mT@@@ +40GcP000Kn3F4f@18QgEJqoCZebP6p8pCgILgyW7Y_@K0OG6@3GA068QL100Wgl7YEJP4jgK +vXCZ1W1HhgAW_m3yF00OcP0OXVR00u700060N000P00W_yJWu7000EG7W2mU050n1A0Yx004 +t1w8k3s3K3u7e0G6G1W8Wc2W1ypy3e3e7G7G1WEW20n100W1De0Ga10Wu7G6H6mUWE0P05Wi +0CW8300H6G600WC0500EPdA00W30eupg@FXA4y0s00G4SG_z@300gHchdgFytOryA_pdXU_J +uKV3W0000aV0uOVsosR6000mA100_@FA200WnBaJ_z9qDK200sSYKWA102W001G1410Swl1W +002UUZX2_De6S3000418000010KYu600WGO4Q90gj0q8U220106tN804010W188G04020000 +m00G00108002G0WKG042088G00000802G40400000H01W20W18200QW020008Y08011000a0 +401G0W0eW00010@CP0000IP220PHbGoy9qDV2RFF30G004040W8W003000m0W0040000G0C0 +818080002aiel1nxR0I4040014000C000100840WW0400063000feR0008WUiC00G1MYs9Sy +O5rI0300W00002G09200800810gCS30100004080E3000824G00800000200W00010M02GW0 +40020W0GOy601409193s@F1Wz8WTuPms3FaxEIf0pmtu60080e@V30900aVP209W00001CX9 +3xad0000O5200HPw40100W000G400AACXKEbuo13kPd100CW00000WH0qrE3hjR0028@WOkA +fz7IIpWvsDOt_4A@BXy@D8hG300G0Cy_306P0gnmc00310000KG0W9xnurU3_keYTLI00200 +0001000Wa104knOcc@z0W120400m@@DGW00mxZ9i@e100W2000W000W8WV3W000000010g20 +02080m80LTmG2_600GCzg7gwut004H00021ssF11W04JzR0002010G00O8000002Y0000040 +01800010f0QG7b68000u10340000Q210Y00GM064CBIW0W0000G1H0000085eG800000W2W8 +000000eGKa8200aIA0410W00fGG4a9000WKa404100I954Y0000WK00Ip0000850X4H00WKW +2W0ocr0P052Wa80000IT0NE7FM100e0G100004000M0000000W100W200K02A00002800C00 +00W00m400G10822h2I1m0000K01WG000G10Gou323o3m000ug00WG000G1AG0u0kSw_@10WY +000040W8022W07W6G20010GC00GH008WYW050101YE210000GG0g84m041Y1K8A0200004X0 +U00580T0028W2GnGKOu0000HHeOG0DIR08JWG90108GC0wPQ904W000800020E8g1G040100 +02W0WieI300000K0G00G60I2000004402W0020GW00000G00I141008zqQ040G00020G0001 +00Gub001041mKg9y@lG010000IW000G400C0040Mb08H0C5O10Y00mG000C2001202H@5048 +0b2ztWH00KA084610G41WGe@60H4Wfa2W10G8410W4101WL10240J1000ZwWj4410Yf00100 +00IKKyo100me0Lm6w730J008cWa0m1C1e4s3G9IEWIaO4a8n8W9oTGI0v0@0IYP1a49789I_ +1Iay3u7v7OFWEWV0bOK06a2W18cWz0q1C55W1000Wr5G9YO2I4v7m400OlkPG2008000uF0y +00oegg8u3FGmCdXW7U01LL5pSu1Uu1LCpC2wV04agF8eCpGG7Um3KLb@1m1@301dnC2Ueg4C +JP8uXEeg3TmCp45W14KL000u2u11pK60Ue3U000yF0ZhrLcDv0GX1OnSggW_XieDeVU6wZs0 +8W00NuOm@@94qK2bJPGlb6OD00OfR2@@V300ZUN2J51W0W9ab00W0mcx9SBj1boQGmsCidG2 +Tpc00000WD50Nz6rhy600X1OYNCols0e0W00000H200K0U2000W4000K6k10410k3F1h200p +YRmTPCCArF04G00G003000GW0H8000G0010001010C0W0020204020W04010800WKW400000 +GX00080WeAVD04W00800040G0402001101044080000W6W9uZAFT300K2100020010012000 +006080018000148mV300080WW40000084Y40088f_d0OG0800200G00000100G0W01080000 +mw00hDdGxwCCsCFG00G000400800020e000WmtD0000Iz@6W040001220000GWm8@@dm@P6y +1Y10010002W0GG2OxG3000mbfOKXVBHpy60004911FUe7300isVmBq3tIaVl1h4aG@b60000 +W001W800Wo7C0080mkqCG4000n00m5tFSll12O00kRsW_HJ3248oZv6yJz90008HE004p2O4 +000000HCoT200001002aTE63@B10WzaVKZ200Wu2_F000G0049Q856W0W0008YmaY60140e3 +Y76zl2Wi203sx40GWWgyJOhG30060W400O9U3040WW04420004C201G000Xwd0000G00WY3J +A10W00000KI7W0MmBXlPZ20G1G1z6GW4006000eo400000a2A0k@t00090000f00H0a2G2fn +R00W2my0I000000W7ZmjD00I1m@@BzYf1Hzpmft600Y0eNV30060000820G00009kOzPedF6 +Y_F106C0dWRGp_Hr@V20G10kSr0WY040002WP00qjl1814000008W00400W8020apyP00W2m +w@9000W3M1eHFAET_J5nrR01Y000000020G00000040X00000008GW00000100800W00egbA +00SoCMFIr7N100100C0I01M00G8i140000W0W10G0mM20E0DK0I9000aG1020WG0uWK0C0Re +020000012099R00010040G01000TzWe0000Ie0010000C0078h5000Et10000L_v7000W160 +0g0GpygO700eRxeE2s00W0080000GI000W1000J000k0C1C1o2W3W000OF000u00mgu60O2s +307mKA0900006100GU060040000300Wmd1oJ00P1GEu810ow3000GvwCKrV2000KnF00CtF3 +08Y8Yyt30H107Nhrbq64Tg130dmlqI0001eOyD00007XBIRAoGun6K4E3NcPGHl9Kiy3rnLH +lu900OAiPkA6XVfU2Oe6OC6Y3Z2qD0KY1GO6Hjhk1G000srt000W0VWPms_60400eJy4MOtW +YkDubTC000WoS00erzJMIj52000m20A000W000L012G008K101W00WKa1Ae0SLk1008WGA00 +1WW0eHS30400CVc10Y04wbF100A2000000WdNR13Tnun@@dG40014G0W00C0G080W8W1080G +00140104228eWRpDW0K4W2WY008W0O00000240a20114000YW02800FJP0240WwsJ01000Gg +6WFH39OVO00m004000GJ02P000480G0081000800I0W0280800600G02205010W000800042 +100G10C0000080218000W811040001000W100oU81v2003txHI6p00W0W0400G000002G20m +1G0038027048W04GEaF1C010G440883Z087eR00G01010GfLO0080WvoJ000700G0000mIVL +iHHuvG0000000800110WG0G000W80004008k_4o1mW1zD08G0000GG04000001000eSil13c +dm@@60Y_1uNVd00H4a@d1IW00W0G44tk12W02_@t04I10222Y_@t06G00088000010048001 +0mZw60080eyV3gjE100mag200AcDAW00Gj_R0004G02I80080080902008mC3000W0212110 +010W1aIIOOx@4W80002WW8J@400CV7D3LtoR0080m9VJW0000G048G04000X0oyFXD0C0010 +mI_900W0Ono4MgF10yA0Vcx4040mimIW00000004e0000W0cWW0020H01GYG0G0103880GG4 +G8a00280001080080000I03@d0W0180084v_d0000UQ200fhx4O6004HGW41W18201H6X4ID +28004M0e201WG89001I0006W0415041880060084CYGG0004H8I401W00Z00W410GG200WW0 +0000C240002010080000uSq2lJ000e00Y42000WKHW8I080I954A500aWK40n0G4000b8CZ4 +00WKaYZI10W0GA1DXJ000Ha2IGI200GAemGX0G00a200240200I19281200bKGmC0000000G +R6WLcZI1008e004WLGG001G0200001W280K0G400000O0880008W000000G128020000K094 +04400040002000e010P010O2A44I01L6X1000e0000HB008OVdC80W0024X01I0200014cW0 +0060WS2941WW6I50m00K0n0m020W043G8Y701QGu01484440000H840K00075J1922WyGS04 +1E04008G410008012000WrbShZ2120000a8041G001e00041000108G48H20G0b0W00H402I +2004HG409092000Aa000402080212210W0G088W880bkQ00G0WExD0a000Gt4WbzT20mM24H +0Gf0W0HWp0wbWH00O8008633tWSmDm5C2GEu60GW08MS3a2z50H00KB080610G0100eN0014 +YX0000oO00GJuH100eYV00dx0tT_XA@00L_10LEaQl100300kx_1Pz10uk30gS7G8Y0W_@7m +100m3000000WCz1mC00Ou20mJ82000W@_Ay@400CtNVSKIWO2a8v7W9oF82y7GS1_Xy3oA7S +9GGM0v0c0ACS3a8v68HpF0NaVWi0Y0S1KYI2e4HC000AI1ORTd0mC2ApC4KcPCZCpuV0Sm@0 +Gm@1WW7201pK62Ue3_NLgKLLKPcP8u3FGGLd9HS3Y2m0FyWW_701Tu32ILL4qV0y0LLvV0eo +CcHm7y0Wg200WbQ00m6tKL9E904082NYa9pDeN@Yo1@XPpDejV6I18XSUPewSI0pf0ChVQph +RJmUK10010008mGy6CMy3TSR0220W3dI00000G80W@@z00mdrzUIKj@F0005001W0120W280 +0a0080000000DE3t0880000000Wg000008zQ30AG0Exl101100004qIS2Dup0mx6WWmb8lGU +000K8200040009e000010020800040806000418G820G10JRPGO66W028erG380040200uvU +3G500W00000G8mVy60000b_00mYvIii7F0090e0040004083400220010000001n000010W0 +580000000WChxR01000800CW0W000080WG200000900WZzJ0m80mw_600Opy@V30240yu@63 +x1300181422000G00W00800020m00000e020010a008043k1bsPWW10WYoV0083m3rF0UV1u +@@e0G0J0100yBV3MhF10410lf@0K0100W80VSdGoz643U5I600Qst91WW0FRRGg_60208Ot_ +700W8KKU200082ut00W00FEY10YPvRcY2080000H00000JAOmjwFqhU2Fh@mw@9qxl4W1B06 +5cgHrJuFS9UPFXktF1000ViY94PFI2GH00015X0a000Y0020G0X0003wRGcs90041000W100 +e44000fJQGNxU00ua@Xhe0G930L02W00804O0WGAU00H0002400400YW00000010082001GV +_60G000E00G1s6y_@30B202st9005641000082W081euR30G00q7E39YRW20GW9_D0041H5u +FqCU2p@dGuL9yiFI0060GOG0G0G0QrV32xmW_mD0042GXy9CRj1jSRm_@60080e806U@F100 +Jkdh75220nJmDuOP3002AKOl1RRR0005WdWP000W200W18440xMRGZiL0EA1OPVd0040X200 +8QT3E@tWk@D0G00m5x6q_T2nbR000WeasP0100GCuF000WtR00Gp_E1oI0G8aW0040008010 +G0GK20508K010000a01000000O00I4t0WGa48000omr000W00f40S0Ie4503v@d00WphVzZQ +vQ34000CQj1GMV0Ayl2k30Pw300IvsWZ@z0480mSzH1u200e3m500G70S00000TY0d10a409 +Yd000PW4aC000S0000WmmP000aKD3CO600eNVd6fo000D00eUYZxN200WV0000u000WA00er +@J00a@t27OPWRGA0Ii_V2PXZHBs90ov18itbMsk2W0021Xp0108WUhCOgN3oXUZt@D0000bw +10WvkVeeYesthYT2sOYs4EFt0002R3epmqU5LKE300100WW0ymU2HYRG_Q6iAi13jRGwRU0S +r0O0A9kMN82A48XyQ08W0001007pam6y6qLl1W800kVm00400000acAt04002TtdG_z6000W +1_8WW000W2fFvjA9g_N200e0W0080000kac17rR02W00GW100000G15GW0000G0000WW0800 +1BgR08WWWBrD00080A000GG000W0A6MF100TA00W0_mtWC_g8YzP0I0090H5100504W0egqJ +0I00200080808lya0GYW104000G00W00e0W00H802000000CG8G80000400WG0uhV3W0000M +bG02A4G@zRakF3HAGIOxFazW1001000041001001W4W20WL@VOtz700G1inF3000ei500ybn +I0000402080G001080C20Ws@D0G200008WZmC000GW4G00048W000C000ICpt3X@N1002xyq +nOR@VcDt008YG08I000204yV24800WC200404W020msPIK4Q56KK0cSDgmHn000GGFE60400 +eGX4gWF10G08B@@00G1WHyDOO1CcuqcXKP0G08W020000W0tvbW008W4HCOXq78000yTk1X@ +N10WDyurZY0800W0000G02G0068000H0Y2ORF300220004000C0X4I0IK402020WG10SNU22 +000ASyX8sJ0i52Gc@LyaL2px330G0G0400280400D00180G41004X0080Y0@4OWP001J1G42 +80a0X20e0008RM3wNt004G5B@@00O0W3bC0N00GZGHH1G0080015000W8b0HvA1ea2Wa@D0W +G0000GA5100000e0500CZB3a1002Ar0000000ONZ9lY@_DeKE66sN5W000000100G0000a28 +800041e4NJWc10Gg_600L0000G001204128VAA1000G000Hr0a0Ou0W@@hG6G1GWBFanlAvp +pW0W00S00WF@R000G2020001GHdFo0G880N@d00A0G0082l@_mAj60000dJ00m@@IW088O0H +3_Uq6400000WA0000009100000X14WdhD00GG0000aVJJ0b00m7@600048@63cazXwuC00mB +L1MRyl@C000Y8010yrR20Wi1Wm08H500evV3GG8000000z2eW1O34WK20409K0W00840E000 +0B00O0i1205sn0X8wYgdD0Ca2m@@I00OB00W06K0GWSS@100Giw1eK50GLJQP008600000Eh +ed1mkm2GH18@OL8600qilJ000GD00020C4n080W2W000i6000O00001000104WV040e0S100 +o2000C0000000u700W9OF0G0JPnPm3r9O000m0o000W00002000o5@@l200C100y3W000qOf +4fyx100Wnr_Dmh00WHULF00006vL0X900Kvl100W6qTUT3Q0YHz0YQk@90WOg700000YQ_k@ +n0W43GerK56k100W0W000K2U5bY@GQu6K8d4FuPGEJ9a8aGZZ9X00GWIuO0040GDlCW00800 +00010GWd@JG08GGnh9S8c1000000ClKlB6jc@pLwB1m@0O7Ug8G0046k1K0000004C0l1DIP +m5y68010O7P3EIsWOnDW01GW08002000pWPmQy6000WSx56_ucX2npH48G808804005NKOGh +v90040010I01G0YeHJ0400000W04101PdR0088W5qPutP3G40000mCg9yAUFY1100G5lq244 +0140016G00G01004080100020X03GH00G01CX420008G940024W0a000O8W0G0H2e81e214G +m@w6G000m00G82Ae020100000G01000000aE3422W00000880400W0avk10002gvp000W0tX +330W0020m00G142jo0080000040102080200CebX08002052010prt02G00aW51DGeWaol1G +000800200GGW0240G20WwNJGzG4mU46G060OVT6IHs004080800MywXk5z0254820010G070 +0W000W8q_l1G01480010000W200W0G000W02280001300W0200800028080G0lLO00G0010G +0dbO00200a00000eU2XdXMuJ8xR32uV6000188100G4000290010000810W1009G0XW0W004 +4008EoTv6qgX1NOR0100WtzCG0880010000W0m00000080082y@V307e0i9K51n@GNydKZl1 +04000WH0000HiCV3W0I280240000qb@6W8020502ms4900800W00028014208W001E0nWhzD +8LH3000ZIP08ePD6oMqWE_JeUjP80800WW0eHD341000G1000800200G6m00280000040008 +00W0mFK9010G0040m6@600W00200mQW6000406040000000St00W00010CpW1xCX100GmszL +P4J340000022G0408W00mNmCuH8300W10009u8c4wdC1G000W010EOtWbPIO8T30_m0aem3V +T6I0@U00H0IW1044HG01ne0OeG080gY0YW41G090GAW5W4Y24X4G020W01102200W2G00000 +00W41G00004040G46000G8280040000004G020W03305000000OM602Q4qWXObu@V6K200y9 +q928018I44Ga8800O020K822WG1W0X2e1A2040a0100044W32GWKWG00GG00W00001GG0000 +20mW040L900e5HW800000W2b0024000008sjt000wU3zR0C0000010W0W0kwtW4GJOkV3A1K +5000K402089000A0G400001a200000IGg00040810a2Yo0800GAI9G40000850H0I0000IL2 +0P0008bKW0I0000I108100000f04H0200aIA0_@t00TWKO0I81G00GA010Y000eW20H00000 +A008a0000aYP00GiS6KbfA000I8A0000Y0G85000004WC000000020PIK100HWK009004128 +00C000KW00m210000G0A31100014042020AG0G8Q20e004P4H6000G020QsIj1c3404I800B +00H60KG5x64Fb10000G48000H0OXRLAf8XsoD0a0GW80W0C0020W00m6G820W8081510O0KG +W8C0W0A858Ge8080G8E2W80048W88CF0G052meG0J00W3a1H4100840G3a204WW8000WtE3G +900IWG00aW040400G80WWG020Y0H41e800001480020020eHTzdqyl12Y004000W10900004 +G2480W08ICHG014000e0040100W009G000008a00G020004001e00WeaC00K20I20AW0809a +O000240008W4000A20A48800G010W00000408WG0G00qIX1njRmf7gCLl100M00W8W140001 +WWW00G8KVZ08044G@D484II102n800a8084zk1GY0OAqx0610Wf001O4002404Y_R0CH0A5w +l1Z00OK0F000WqUqVIM060H004H000O10G01O8Wj0410ne0010G804GiSFqHx6010040GWOU +00000WjkYwFtnFg0GVa1OHF300S70ex60wZCW300eY@yKqp0mTm1GqF30000000GHqJC0000 +ZuL0t5i00mMq60We000KnF00000mFg0000008q66EL00u2W1u70306WE000T000W2000@W4G +_1_Xy3s3G7u7WISF0b8v0AHoTGYax0k8t1P1KA0F450387000@V0b5W1uYO2i7G4W9WIKI0b +8Y1AH4J000@0c0C1O4Bt3TKu140000@A0C_A0000C2004ryvLad1GKp3GqU5000WW7wWHKbA +pCZ3_702_m34yG08eggGm3Fm@ggYPc10pCZWUu11zNL2wm34qX7K5LLv1FanCcHm@1WWP200 +0GB08OM06GLLUm37yF04S6p8uX00GLf2000W@1OW@PYzk210023IRGFuI4hT800Ksh2dA200 +1z@Rmw@6S@l19@RGr@60010008G0000XtBb8H63ojC10200WkE8g0mWFcbesU90000UGREVb +inupXGL00uQze0G00asc1FnR0008040W00GW00002K6d100W0Yor00080x2@G4t6W0000000 +nTp600Wc3W01GLq9KrD3HZN1G00eK_F14G4H6y600200W0008G2000306080Eqc10H000100 +000A0008ehQ3g2t0G0000G0Ws@F1GfB0lnuH1_Iyzj15gwHBv6KGV20G020Y00W02001CHW2 +80WCxD010K018W00K00e0W000840000110G088000G01G00XGG04Sbj10008P300000020K0 +0080YZuDe7E3wqE14040000W_ocXI_91802101003000HAO00Y86100E0O00K122q@l108W0 +089100G00100a140024000100kUp000e000W1g2A100Pf@UdmKN6K4U27zRG8xLW400eYsGo +zdXT2J00e0GDpC012GOb43wWt0G400bTR040001200G0G0_@t0GbE0rKPm9@C45l1ZoR0020 +G00000408QpKbKtD001Gmzx6CVO2Y0002GaXFwJ0H00GEzOiRb1a600wus900e05Bp00G811 +00GjvR001800200000G0120KwV200104W0008G081R3UpCXbxD0000002ieujDuTp4sNNeOz +Cu3@4000G040023018G00W9@D004Amz_6001eOJS60080W000epO90LW0yh2FbflnAz94jl1 +80GG00000100Pj@402W0r@l102004000SZe1008038DXZ@D0000k@00WSxC8WTa0Gm0KLl1R +wP001e0IW0G00W04408004O001W40086A1m4G00848021208008W82000018080O06KbXGHC +0m0000W2iKbJOMJ6kgJbazb00100C2001W0820X0W02001001GO01Da02H1HW00W80808ijl +100000241004100W00480110G0A080000W82W08s_4c@t0W_A0000GYWNY4Mv1005000H005 +100G4f80008280W00044010W854G004HWK2000Y0A1850qaK0408a2281024GAf000G60040 +0GGK0000f0WI001IaYK0008100000uuI000fI000GaAIN68040aDRE0840G0G0G0G80O0000 +014100O02AGC21620e4080Q80A0GW0I800CeW08a0W0W02202H31062880900420G1400K20 +05Y0nC40WX444G000X00000009DG0004000404000066JU2TFm30000004400i80000W00O0 +0800ma06000003218440W080W0G0060280G1u806GW81I3K0G00083800100A1004400OGW0 +YGo08400C0B0GG004000OL402o10003mZM6yFq31yF30W80H000h0P00W00H104I0W0001HI +W0200YG1Y00WrwD00G452C0808e00020002004480080g038020402W8501G001WW0G10000 +0G000a6FW080H0aci4Xuc30A1000020G0008040W88J0042WSXC100W0o5041002WG0G4a50 +1619kGV008Kou20H0WG1G8041w300ZmcB8B0008Ik0W800e0CIA060DN000W1Fo21W01Ce@1 +3Y9dX@zv10Pc100G5FyGa_7WefA0HBpCYMcPyFLLfALTGLgAwgKLq7wXeLbAHhALU8JPyF0o +uX74z@08wCVGqPcXeLL5FSu1_700yF0HxX7YsV000uEx1HdP6WMLLy000yNcDnCL1G701YEW +E0u0T0A0w0K047e08g10GS7eZe6G7GTWEW2Wz050Y3A04@008_1yJy3e3e7mFG185038o00G +y3aXu7iNK090000W4W2GC06000q9Ju4Q5tWQNi1o00000000eF00WnN1WxW30_H500yA0yZA +0aHVO400mFg0m1t1WCw300w60ex60000et@t000m2s5002@l200QC9IJLLSaaulAJKQGK1QT +Kk4XhMHiu6CRx3reR0000MT000Ledmmt8L0hDR_Z100Mli76Rgs7obEXTuVemz7cvE1W920d +tomw12TsV5001011000084ij_401000G01uCS3oqc100805@QG3l90000xX33w_F10WA01vR +GiB64aF9xrZHuPU4TV20080_CtWAPC014008080aG003YR00000002dDXRmmp6y@V2480102 +00yWU2dqRGe@6KiN8n@RmjpFiBj1lvdG8o6i6k10G001024i@l10004100W0G238nQ60LM00 +40GeLT9kXFXEsPuTk42u760W040000000Kiqk4FLd00m0WO_J00G4Gnv6y@l1Q400QlsWr_D +00u0GKy6W580OoV6_NFXkXo9YbnMInfmyb00001000e0zO86k4CSm4yhF3000W0G00igV2bn +9HWS9i8NHJQJ20004F300000GAgd100080004AiFXnpP8h3I2_a70001TxRGqw90W0000mPQ +Px60200eO@429tW4Fa8XV3cpyaTqWX000Ks36Kzl10W00Ycq04000W412618XTWD0040GPb6 +i7l1hpRGWy948N21ynpdpCyb_340W8EKd10010000e9C00G000AXK600G01004W0004000Wo +_I00W0G@e6yzWDdzRG71FaEI20001YTt0200GGC000YK40H0000I90000H000000g6950Y0H +000028Y800008WK00040102002850000X00I42004G000G4000100002mIy6KNY1xsr20040 +0G48hNy0H00041002200008W00084000208e0G0W001e20Wc004G0005010000G_A800W200 +K00400B6030WX00AG00G100e0060420P1O0m000W000o00e0080840CiEkSUJbXK@P00C000 +8800O0I008W0C000e800200030004400000WC5H410000OG00G10000084060W00WG2O008G +GA000400010W024018060H00W1900104020@0opNsF000WeHE3g_t0050a0008008H088IW0 +G0mCf6000rH0401008000XW000K800e000G001202YK814800H00U0t00a000C1080108G10 +GW20mW@60500eIhMW002yuF3nkPG5w60W08o00020OWiOuCG4008061WKvCWB0000PYQ10Ge +8n10410W20G0G4K700014EGM000GWy20HaDd18A00020EWe000W0u00Y000208002YImuXIl +5ILL5f@08w0vCmX7yF00O6p4TLgAw@000GuC0YMcP4j3FuVPcnCcHbPCJq@dDN2ou@CbHLLH +b7UGq@3WeLzXOvCm3@1W@100LL5qHZ3pZRI4xc10P000m0G000a1e08ICS6u0P4n0x1g3a1K +0e3e0GS000y23K04t108Y1yJS783e6G7Gp2m008w00my3eZ83G7G7WCW2GW09Ga1aX8383G1 +Gc3vIOOez8Y80yRKr9hXKg@F00WsBCXjlXlb8@v1000bz10WOjIRjTR000C5rE6J8dJpKH1I +u0OIUF_YQcaxT2000bE10WGvD80mhoUG800TudaxHTpBjvVEWZG0IU0fEKGws@7000pu300e +8bvdSFAGG50TcuHNTKrWLB000Wi900aa66f9U800WwBtyetHsEv43WiD0JviH@alTKV595uH +GcoX020uyV9000yCLY7V4AKV@2rx6600W0EcHE0090@O_mw@6GP00e1lAQ7HkxLH500JmxqI +0E50OyVC0410iADLvzF3a00Wo@h000AzMJZj5q@P9z@LK@Nbr@JXzVKQ@@4t@Dvz@IW@dau@ +7H_VHc@F4w@1f_@Fi@tZx@x0@VEo@V3z@rO@@Cu@7Z_@lm@VB_@@@@@jP@@Qu@dc_@dn@VP_ +@d8@@7w@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@VcyrU0_@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@B5000n@@C00On_@@F12000MX0u@@@@@t6000 +G@@d0004000Wc@@@V0f@@@@@@@ZD0Wp_@@zG000m@@120f1u@@Y8000y@l18000_@VU00vm@ +@xnB2d4fG2@@J5mF1W@@T2200m@@HnT00ec8XcNOc@@L10GusN68b0K2@@@3200a@@V00e3m +PKJ_S530000jA00KZo6dOzm@@@@5132000Q0mW@@D0SY3moCA20048uA6w0m0000OfPKnt9T +z@@6a844X0X8100G42G4100G2X0H4849000u5a506@@@VA6bMY13zQ8Kg0X45m9@@R0G8200 +0002a0HG081_@lAWu00st3312000X8HG000aAW7H1So@@6880000009Y440Ya00@@B10oX00 +W38u40000ES0000GE4m100XJ0000C000000W43m3oX00WZ890000GG22Gg06Ga4o9G030000 +W300u@@4000Y45m3@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@V208Mx@@@@_3B2000wpm9y@@@ +LSFJAZC0oh1u@V8100Gr7_3PF0P9bI00G_QSzC@@F1miC0@@tudkI000Wni00m4yDkzW4000 +A_@@@@_j1G40mhkC0000DVo9X700C@F3002G_@@@qH_Pku4aC00y@@@HAy@@@@@zy@TN@@st +@dT_@Nl@Vrz@Fz@@1p@@l_@@@@@ZlZ70001000i4100A6ehs7520mHPA_TH0008TVX0DR0Cy +WbJQo0D10W@@f2004m@@810Wn@@@@N3Hq@@H200Zp@@@@@@@@@@@@@@@@@@7@@VD@@l3_@ve +@@Dy@NZ@@@@@VM_@VS@@5@@@C@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ev@7 +w_@Vs@Vd@@FS@@1@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@Fd4000_@V3ma70@@@@@@d0W00u@@D008v@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@Nb@@3t@Vm@@@@@@@@@@@@@@@@@@@@@@@@@@@s000O52000040u@Vjw5G +800iA@@36040W@@@1qg1m@@V2000LO00Gr12z@VN00ELH0000800u@V9U1uY@@J3G00000W0 +000000K1_@F100G0@@R000W02000JImmr2_1Cf0u@VC0080y@@U00G0A7n0000eqZ00s8814 +000@@R0420WN5Oud4m_@lYM7I000pp@@68W00u@@40040aGnU9AO0020040000C0000008UW +0000aGY29W0088603W000afX12002ELuX@@JxC33000G3MW0G0000I0201000020W0000000 +21000009800G00@FaGB1iTAI20200006000uZ10000WW0000000204IXn0G0000W00I1mW08 +OBx160010W20002400W100Wl140016040HW041G0020A0W01G0G2000W00190022004020W0 +0000800WsTmivSCG0W0000800024XeOWu0000030G2W00080800G00001000A04W0pZOm@86 +aeHQ4020000080100000104G0W00K024000q_FaY10G000004001a2000900GA4000080G80 +0000b0W02Wm@@cLoY10004020000W008WGGiC60y61100000W20W00000G0028010000KW00 +000088080000G00WavIQ0G0W00001080080C040W00000I00a100Wg400W8000GWW0W02000 +02m800W020ZWe100004G0090004001G020G0C03m@@Z100W004050WG0000I00W000180080 +00WhZ82Y045GG0001040GG002W00000205W0100G800X041040001GmpCc1008o04000O00G +00W004041H100G003000W3aQ100i0X10010WI0G0G4K701004CGT000KGu00Ia5W18A40020 +84WZP00WebP6@BpC_70gyW7Y_V04jg000mmx3HBpCYcggyWCpeALfo3n0O00Y_G74jgKv@Cp +281GhA0@@F6G00430W02G6GDWCWQ0T050o0A041000UB050mT002A0T0t1w0g1q1K001e0G4 +G1Wu700H6WEWC0P0T0o0A0a1K0MGIE008W@@R0mO1m8aC0000a200W2fC8693_@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@BVy@nB@Fyp@@Ez@kN +@Vxs@p_z@hZ@lwv@dk_@el@@vy@RU@@bx@Fv@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@VNH000y@VE000evB00y@FO0004_@d700iF@@@ +@@@CG000u@@M000Wy@l1000ue200y@VT00W0g1GZ@@P0000X500W9DWyO33YK8100xHPFav@ +@90Qp0u@@@@@@@@@@@@@@p5wD4000000Yccn0000qY300_@FD0080H1Wo4DC0uu1u@@@@@Nt +HZIO_8I02000uY0u@Vd000aByW85G1HXYq251ubG4X8mO01UW0IdMM400WmWG7HJ10200GW1 +0WWp18AWJ000GKa46@@d3mB000LW00oV004yL2800010002000400G800W0000n@30Y80G00 +0WWe0E1100GI1HLQb760000000000YIZc0m80C45G500W400Zc00000K@1m@@@@@@@@@@@@@ +@@@@@PMQCek5WPeOx@@M000o1q700000n2Hdy@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@tL@@Rz@Vyw@@E@@jx@@@@@@@@@@@@Vfy@Fg@@@@@@xw@tE@@hx@@@@@@@@@@@@@@ +@@@@@@Fu@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@F00001000 +WLS0_@@@@@52040000Lq@@@FLY4_@d7000qXKy@@@h200G8xXV8200y@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@Vi@@ru@@ez@7w@@7t@Vn@@@@@@@@@@@@@@@@@@@@@@@21002u@@V0004y@l1000 +01000f9008fW9RE81004000e6@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Xx@Fu +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@D001000 +KX@@@A0001@@d3001W@@P0Om3m@@N1040u@@Y000G3500u@V81000_@V20080000Q_@@a9Cy +0OH1W@@@@@@j1001y@F3W5T0_@@@oMcv@V900CB@@lS0001AUnWeNC0020GH0Ly@V2WbE0_@ +@@85s8DXA2g9XS5O00WPLJBx5cZ40200_@N20R80@@N7081W60C8K8965YXxZCeIZA_@VC22 +00D0Om44U000000Wys@@@@@@@9ITOQF900u1uH5Et8n0s300@@39000H80000009424HWGa0 +00G8@@@@tXHl000050W14Z13r0mm@@_14Y00000W09G440IW2a0GG481200000YGm@@60002 +C50900000o20u@Vs4400000W4H220HI0I41GG49106nX1009Hf0O00mHG0000oX0E008S200 +041vG00m14S200007EY18XK0e8AWJm900y@@@@@@@@@@@@@X0t302kieP0ouTG3W000000Y0 +000002041200@@t20WQrxzOOXlAsB0fHrC8s0C_@V30O40ViXHugmy@@64800g@p000019cL +n@@R0000ri00mUSXy@@Cj4OGjhp40h400u43Yb400G0NMQm15LiAB300010W000018G00001 +40WcOVeDH3C000yde4@@l1GD6WmTR10G8m@@a0W12e8Na000GID008SNIYK81GW00RXk1000 +080G000W00010004G00I0mheI00508qtDo_L200V9P0toO58z@@@@@@@@@@@@@@@@@@@@@VR +_@3vdPfNU4_LBWY00_@FA000a0010180020004402GUnC0G01u@V30840aJf104000O00004 +08@@408002200OBD34000000Wc_00mnJsCkM2JG@0001WynKfnS90000cGc11dd000en@@f2 +W0W001500200W0480000rNT20020@@t000AG0000H0000G00000I0008WprPeVz4gFt00EB0 +NPPJax9yKM50GW00108qek4G00031tW5zD0W00u@@6G04G04000400W40882030G08010002 +0000WtuayIu4Y4kBB11000pZro@@6010G00000C00000020410oWt0XW0W00144228000000 +eWW0000040040G00X020414m0Y00GGG100W22G04G0020100W008GxS60H000eIg0G0880W2 +0GGW00X0W0b0G0214002010W2001W00G0004000080mvQ60W020010n@@UKJl10W0L0801yY +M2800200G00008002080000280120000008020W2280W02W154G04K100W04004G000W0008 +014G0vrb0z20008808000401W0G0101080208WsxD04500280mCyDO2V38W00y@F9nic000H +WltD000A000W020e20000W00GKRC30020000G0080000W0408040002W000000000m020004 +41000kR842000002020020W0084040008000G00ICbO2Dnn000WWu@Evk@@RO@@5w@FX@@@@ +@@@@@Vg_@JDJt9NH2Wo0m@@K100W00028000X3pCG0000014XEdh8lU3kUs0800GdFd0000e +0eD0000El040000G00800000cvb1rGRmyP6y@V8Jp_mAoRKpyC@@R0003@@@@ftNC040Gq@b +1W020001000804200m5mI4YS2W00000200G0WOHR6ojs00G94nYb08000W0105RR0000Yfeo +PYP3wxr000002008040000WGG00000W80000W0014ELEXLbD040W00G8WEiJesC60000Yn00 +OqR3E2mWf0CO8O62Ap080000400sAp08000TDRmAqL0000400e0280400m0RDRmnr60001W0 +W0000I0W0000001UlsWLYD00288H00WdlC004000AH0W0W0H1O0040000_9G101000008Y0e +NR30W0000G40028000K0e808G001owMbZeD00W0W020180002G00cHsWVaD0200ma66000Ge +yw4003080000212X000W7iDGG00W200W3bDu@V30x20000000048438WliJ0W000420010G4 +0001MvmW4cJG004mfs9Kpy3PRp010000200G014oU81004GT0OW004YNkD87E3_@t0W40000 +10_Pt0000420300G00kzi1000W1Y60SOG200000128q2j1000G40110240OuW4EPdXFFgu@@ +@dh_@uk@@jy@RR@@rw@Fj@@@@@@@@@@@VfxuM500h29brI6SFqYD3zv1Jikg04k0u@@F100G +oI00u@VIcqZXtgJONl7ovQfxgP00GCOMsC0012ug1LMGEDG7C0zpBnas6iHV2pZRmFzCCteD +r2Q30004w300pKd000W08040h8A1W00WU4VW000q0ygy@@F00SS@@N200W8@@lnD1f5gz@VY +@Vdw@l9@@Pw@@@@@@@@@rX1CGY6W@@lAaMa000mAU00CqRLcZ2i@@bx0RCAO36G220nWdGa2 +KLLGB@@Z1H90Wd1ewsQ38022000G00080440XlhDOBR3_McXpu3100ezMs600408ZD6wctW3 +06ukiSkjsW85A24wFGNSIK9t6ji3Z000040002WW080000002eiS3G004yJ73134IMU9KHl4 +8000E0OWG94w4x@B1@@Hq@F4_@@m@@@@@@@@@@@tU00MR9w2pCpTD@R50PP0IOMYWdLv@ViZ +qrZ8ha00miOcrIaGjA@@R60K6WNYd90B3800000G8u@j7QREA0004C100_@73W0W0000G020 +Yy@V20804_2tWomDG08WmeuC0000SkPg00OHbaDC80010002G00000480080emdP00010202 +W@@Z2Sz1GVxR800004G0Gxr9CGD30001E0OWQlP8eab_@@@2i@V0y@3G@@@t@l@_@t@VF00M +rv4Bq@@@@@@@@@@@@@@@@@@@@@@@@@tUz@hV@Vwv@V__@bt@@u@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@xt@V_@@tT_@Rl@Vsz@Vz@@@@@@@@@@@l1000m9E00y@VE2000_@t60200D0Om@@a00 +mNu@VH1lO0y@VE0G00YK0uB8ov@@700mIcLF60002_@t60002vJ8n@@y0Sg1e7ZhkAuXa_p1 +000hk00Ww9YQW1600G0y@@F00mjoU8g@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@msY20Gtx +@@2b453BUPmbN9y876lIn001401200PpX180000A10zKXX000WWvm020WG1T6q2M2bW13084 +W@@F1000bG00Woyof6ECkphYF_m00W04021W85s00WFPTQUKzL50W00G00000G0e4C900804 +zG5ntvHE4C0200u8G30100_tc1W7204001qEe1p3cm2POG4000001mlWOG000iAEI6Ep0014 +020000800MGd12400088000e20m010W04001848Y00c2m0000uM200002000400W80m@@900 +G000W00000uKAC8DH3sJZ1a0010000000XigM20082wLh540W0000WoOm00W0W000W010000 +1024G00GW00W0G0G0G00100800000GQo@@L06000400000IW_1C8oX400001080000WHsZ64 +un3pyPmZZIKQ83RFQ0004m@@P0021GtV60080u0W100400801e5I301000oU0020C000G000 +q0pVKnDWCade44000E3q00004K020_@@@@@@@@@@@@@@@@@@@@@@@VO00@8@@lqki8z@FO08 +08A6s9000mS600_@t918042000W0004Ib1200000108002000a0008010001PRW008WugI00 +0WGQs601000000OWs60G0W8JR300Gm@Li420100001abz3RgLnjQI8008e_O3gwcX6bD8JPF +W000iIT2v9pW0000Gs60PC@GQn@0W001480m1s6Sxb17jP040008000G010gJ8XvsCeTS3kW +cX3oCOTi4000GOA008luAW0004M63HASo2QF001001W0GRt9iIj1xRPWW000G04GJSP01W20 +W0000500000000GWX000nM1C00Wx30200102WCqJ0400004008080008000W24iU20G00408 +0abE300A0cNpWFzOOZT3010G0G100004n@@9020W0mJ0180100210tin080000HC0vOR00X0 +8401480080040000WG00008002K0000Xv80200208W04020W02003010000G30WG00000W02 +0X200K30000002W01000iSD340000O0YA8Q3G40010W010040002ag4O0000a00000800ndR +000080008AG40080010G0080008010008G014GA1t00001004G020004G02K000W10WBmD00 +0W00006W10W13O0G002G00K0030000G0082000048W04Y000jYP000000448Thp0000K0002 +rdP0010WcnJW000m31600000820Gqr6G00008G04001WoxIG001m3s6008Gk90308000m000 +080mkP6080020010G01000SK8I00800W04G0i@_40mG08001e_13000AbJX1lFO0804aJsCW +K00GD46Ccl18000lMVfWj@@Ny@xL@@Tv@FN@@@@@@@@@@@@LRqT3m4C0R34rGP6q6dATQzmM +nF000W4600mQ3p30408OjAENR3G000JAdmJtI0sC1uM2g00W0C286jEdG1r6Saj7W0G0000W +5BS5F4o3W010004G044W000018W82100400200008TYP0000akYDOAPL00SUSoWA@@J2000G +021004000O400000S_13oEtWlZD0003GwwF4Zz6VbR0uS4Wu3Nw@@408C0CYk1Y000sisWDn +V00G0GtuOyk_3000uOF00SEvpDH@@Is@d4_@7f@VHy@Fa@@@@@@@@@@@@@@@7Loua00G4v@@ +@@@daRo210003H10W@@Z2002GRr6y@VH00el_@tfllD8ox7_@@70m009A4rwQ9S19IO400oU +Wg@@N20GzHDr@Fpz@na@@Bx@tI@@hy@@@@@@@@@XbrB020WpbDO@Q3wNsWuTt83v70000dnD +30804_@VU00W0NAOGrr9K9U216ZHTpI0u008_O6sP_dLbJ0100100000G048100EBF1W0000 +00W4K00yiU20002010000001040qzwFiCT20000HF88qoCI@@R00402015W06000140G2800 +9G10W008000We0220400S0m0D0O000004005WW28oJ814000W000p6dXtnD00Wf70000001G +vOdGJs900WWu@VRW08000X01W00200O4WAK40100020000WG28e00000GW020P4Omh36G8G1 +00000G0G00100040000G04Bl1Xnp0eC2000000204_@N20240@@R30X0K0010jqRmpr6Cel1 +zbR04G4WHxJ02W4Gws90W00OHS9400000005Y05ma06CcsLvO@@Du@NZ_@pm@VC_@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@FV@@n@@@Fw@t3@@xu@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@bP@@Ou@7c_@Vn@VN_@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@l4600 +00wojIsF60G0020000K40000WXC0C0m40000WW4088204210YW009G0W280m04QCcX4IQWXO +0C0040800O22m0020G0000WcuW160G00000W10A82030000QqtloCC0W0040000ivEy30_@V + ; +' // Loading device with a `jstart` instruction. +IRSCAN 10, $03cc + ; +D = 12; +WAIT D CYCLES; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +' //Loading device with 'bypass' instruction. +IRSCAN 10, $03ff + ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +POSTIR 0 ; +PREIR 0 ; +PREDR 0 ; +POSTDR 0 ; +' // Loading device with a `jstart` instruction. +IRSCAN 10, $03cc + ; +D = 12; +WAIT D CYCLES; +' // Loading device with a `cfg_in` instruction. +IRSCAN 10, $03c5 + ; +DRSCAN 224, $0000000000000000200000008001000c0000000466aa9955ffffffff + ; +' //Checking done pin status. +' //Loading device with 'Bypass' instruction. +IRSCAN 10, $03ff +, COMPARE $0021 +, $0020 +, X; +IF (!X) THEN GOTO F; +POSTIR 0 ; +PREIR 0 ; +POSTDR 0 ; +PREDR 0 ; +IRSCAN 10, $03ff + ; +DRSCAN 1, $00 + ; + +SUCCESS: +PRINT "Successful File Execution."; +EXIT 0; + +F: +PRINT "File Execution Failure."; +EXIT 16; + +ENDPROC; + +DATA TMPDATA; +INTEGER TMP_DELAY; +ENDDATA; + +PROCEDURE ADJUST_BIG_DELAY USES TMPDATA, MAINDATA; +TMP_DELAY = D / 100; +TMP_DELAY = TMP_DELAY * 25; +D = D + TMP_DELAY; +ENDPROC; + +PROCEDURE ADJUST_SMALL_DELAY USES TMPDATA, MAINDATA; +TMP_DELAY = D * 25; +TMP_DELAY = TMP_DELAY / 100; +D = D + TMP_DELAY; +ENDPROC; + +PROCEDURE ADJUST_DELAY USES MAINDATA, ADJUST_BIG_DELAY, ADJUST_SMALL_DELAY; +IF D > 2500 THEN CALL ADJUST_BIG_DELAY; +IF D <= 2500 THEN CALL ADJUST_SMALL_DELAY; +ENDPROC; + +CRC 324E; diff --git a/oldfiles/vulom3/ulogic.vhd b/oldfiles/vulom3/ulogic.vhd new file mode 100644 index 0000000..0162ad7 --- /dev/null +++ b/oldfiles/vulom3/ulogic.vhd @@ -0,0 +1,320 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Davide Leoni +-- +-- Create Date: 5/4/07 +-- Design Name: vulom3 +-- Module Name: ulogic - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: VME address encoder and decoder, I/O ECL configuration +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +entity ulogic is port ( + RESET : in std_logic; + CK50 : in std_logic; + CK300 : in std_logic; + CK100 : in std_logic; + LEMOU : out std_logic_vector(2 downto 1); -- + LEMIN : in std_logic_vector(2 downto 1); -- + TIN : out std_logic_vector(16 downto 1); + EN : out std_logic_vector(4 downto 1); + ECO : out std_logic_vector(16 downto 1); + ECL : in std_logic_vector(16 downto 1); + IOO : in std_logic_vector(16 downto 1); + FLED_T : out std_logic_vector(6 downto 1); +------------------------------ VME interface ------------------------------------- + U_AD_REG : in std_logic_vector(21 downto 2); + U_DAT_IN : in std_logic_vector(31 downto 0); + U_DATA_O : out std_logic_vector(31 downto 0); + OECSR : in std_logic; + CKCSR : in std_logic; + HPV : inout std_logic_vector(15 downto 0); + HPW : inout std_logic_vector(15 downto 0) + ); +end ulogic; +architecture RTL of ulogic is +signal ckcsro : std_logic_vector (35 downto 0); -- write clock for registers +signal oecsro : std_logic_vector (35 downto 0); -- read enable for registers +signal hplx : std_logic_vector (7 downto 0); -- data register for logic analyzer +signal INPUT_ENABLE : std_logic_vector(7 downto 1); +signal downscale_register_1, downscale_register_2, downscale_register_3,downscale_register_4, downscale_register_5, downscale_register_ts, downscale_register_vs, downscale_register_clock : std_logic_vector(3 downto 0); --15 +signal delay_register_1, delay_register_2, delay_register_3, delay_register_4, delay_register_5, delay_register_ts, delay_register_vs : std_logic_vector(3 downto 0); +signal width_register_1, width_register_2, width_register_3, width_register_4, width_register_5, width_register_ts, width_register_vs, width_output : std_logic_vector(3 downto 0); +signal scaler_pti1, scaler_pti2, scaler_pti3, scaler_pti4, scaler_pti5, scaler_ts, scaler_vs, scaler_mdc, scaler_tof, scaler_dead, scaler_pti1_accepted, scaler_pti2_accepted, scaler_pti3_accepted, scaler_pti4_accepted, scaler_pti5_accepted, scaler_ts_accepted, scaler_vs_accepted, scaler_mux1, scaler_mux2 : std_logic_vector(31 downto 0); +signal scaler_reset, scaler_mdc_tof_select : std_logic_vector(7 downto 0); +signal or_on_off : std_logic_vector(7 downto 0); +signal ts_gating_disable : std_logic_vector(7 downto 1); +signal pti5_ts_alternative, delay_register_beam, width_inhibit_register_beam, width_external_register_beam : std_logic_vector(7 downto 0); +signal mux_selector_1, mux_selector_2 : std_logic_vector(3 downto 0); +signal branch_en_with_mdc_tof_width : std_logic_vector(4 downto 0); +--signal u_data_o_s : std_logic_vector(31 downto 0); +signal cal_trigger_disable, com_run, dtu_error : std_logic; +component trig_box1 + port (CLK_50MHZ : in std_logic; + CLK_300MHz : in std_logic; + CLK_100MHz : in std_logic; + ECL : in std_logic_vector(16 downto 1); + ECO : out std_logic_vector(16 downto 1); + IOO : in std_logic_vector(16 downto 1); + TIN : out std_logic_vector(16 downto 1); + LEMIN : in std_logic_vector(2 downto 1); + LEMOU : out std_logic_vector(2 downto 1); + INPUT_ENABLE : in std_logic_vector(7 downto 1); + DOWNSCALE_REGISTER_1 : in std_logic_vector(3 downto 0); --15 + DELAY_REGISTER_1 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_1 : in std_logic_vector(3 downto 0); --4 + DOWNSCALE_REGISTER_2 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_2 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_2 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_3 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_3 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_3 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_4 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_4 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_4 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_5 : in std_logic_vector(3 downto 0); + DELAY_REGISTER_5 : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_5 : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_TS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_TS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_TS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_VS : in std_logic_vector(3 downto 0); + DELAY_REGISTER_VS : in std_logic_vector(3 downto 0); + WIDTH_REGISTER_VS : in std_logic_vector(3 downto 0); + DOWNSCALE_REGISTER_CLOCK : in std_logic_vector(3 downto 0); + BRANCH_EN_with_MDC_TOF_WIDTH : in std_logic_vector(4 downto 0); + WIDTH_OUTPUT : in std_logic_vector(3 downto 0); + MUX_SELECTOR_1 : in std_logic_vector(3 downto 0); + MUX_SELECTOR_2 : in std_logic_vector(3 downto 0); + OR_ON_OFF : in std_logic_vector(7 downto 0); + SCALER_PTI1 : out std_logic_vector(31 downto 0); + SCALER_PTI2 : out std_logic_vector(31 downto 0); + SCALER_PTI3 : out std_logic_vector(31 downto 0); + SCALER_PTI4 : out std_logic_vector(31 downto 0); + SCALER_PTI5 : out std_logic_vector(31 downto 0); + SCALER_TS : out std_logic_vector(31 downto 0); + SCALER_VS : out std_logic_vector(31 downto 0); + SCALER_MDC_TOF_SELECT : in std_logic_vector(7 downto 0); + SCALER_MDC : out std_logic_vector(31 downto 0); + SCALER_TOF : out std_logic_vector(31 downto 0); + SCALER_RESET : in std_logic_vector(7 downto 0); + PTI5_TS_ALTERNATIVE : in std_logic_vector(7 downto 0); + DELAY_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_INHIBIT_REGISTER_BEAM : in std_logic_vector(7 downto 0); + WIDTH_EXTERNAL_REGISTER_BEAM : in std_logic_vector(7 downto 0); + SCALER_DEAD : out std_logic_vector(31 downto 0); + TS_GATING_DISABLE : in std_logic_vector(7 downto 1); + SCALER_PTI1_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI2_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI3_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI4_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_PTI5_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_TS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_VS_ACCEPTED : out std_logic_vector(31 downto 0); + SCALER_MUX1 : out std_logic_vector(31 downto 0); + SCALER_MUX2 : out std_logic_vector(31 downto 0); + CAL_TRIGGER_DISABLE : in std_logic; + COM_RUN : in std_logic; + DTU_ERROR : out std_logic; + HPV : inout std_logic_vector(15 downto 0); + HPW : inout std_logic_vector(15 downto 0) + ); +end component; +begin + trgb_1 : trig_box1 port map ( + CLK_50MHz => CK50, + CLK_300MHz => CK300, + CLK_100MHz => CK100, + ECL => ECL, + ECO => ECO, + IOO => IOO, + TIN => TIN, + LEMIN => LEMIN, + LEMOU => LEMOU, + INPUT_ENABLE => INPUT_ENABLE, + DOWNSCALE_REGISTER_1 => downscale_register_1, + DELAY_REGISTER_1 => delay_register_1, + WIDTH_REGISTER_1 => width_register_1, + DOWNSCALE_REGISTER_2 => downscale_register_2, + DELAY_REGISTER_2 => delay_register_2, + WIDTH_REGISTER_2 => width_register_2, + DOWNSCALE_REGISTER_3 => downscale_register_3, + DELAY_REGISTER_3 => delay_register_3, + WIDTH_REGISTER_3 => width_register_3, + DOWNSCALE_REGISTER_4 => downscale_register_4, + DELAY_REGISTER_4 => delay_register_4, + WIDTH_REGISTER_4 => width_register_4, + DOWNSCALE_REGISTER_5 => downscale_register_5, + DELAY_REGISTER_5 => delay_register_5, + WIDTH_REGISTER_5 => width_register_5, + DOWNSCALE_REGISTER_TS => downscale_register_ts, + DELAY_REGISTER_TS => delay_register_ts, + WIDTH_REGISTER_TS => width_register_ts, + DOWNSCALE_REGISTER_VS => downscale_register_vs, + DELAY_REGISTER_VS => delay_register_vs, + WIDTH_REGISTER_VS => width_register_vs, + DOWNSCALE_REGISTER_CLOCK => downscale_register_clock, + BRANCH_EN_with_MDC_TOF_WIDTH => branch_en_with_mdc_tof_width, + WIDTH_OUTPUT => width_output, + MUX_SELECTOR_1 => mux_selector_1, + MUX_SELECTOR_2 => mux_selector_2, + OR_ON_OFF => or_on_off, + SCALER_PTI1 => scaler_pti1, + SCALER_PTI2 => scaler_pti2, + SCALER_PTI3 => scaler_pti3, + SCALER_PTI4 => scaler_pti4, + SCALER_PTI5 => scaler_pti5, + SCALER_TS => scaler_ts, + SCALER_VS => scaler_vs, + SCALER_MDC_TOF_SELECT => scaler_mdc_tof_select, + SCALER_MDC => scaler_mdc, + SCALER_TOF => scaler_tof, + SCALER_RESET => scaler_reset, + PTI5_TS_ALTERNATIVE => pti5_ts_alternative, + DELAY_REGISTER_BEAM => delay_register_beam, + WIDTH_INHIBIT_REGISTER_BEAM => width_inhibit_register_beam, + WIDTH_EXTERNAL_REGISTER_BEAM => width_external_register_beam, + SCALER_DEAD => scaler_dead, + TS_GATING_DISABLE => ts_gating_disable, + SCALER_PTI1_ACCEPTED => scaler_pti1_accepted, + SCALER_PTI2_ACCEPTED => scaler_pti2_accepted, + SCALER_PTI3_ACCEPTED => scaler_pti3_accepted, + SCALER_PTI4_ACCEPTED => scaler_pti4_accepted, + SCALER_PTI5_ACCEPTED => scaler_pti5_accepted, + SCALER_TS_ACCEPTED => scaler_ts_accepted, + SCALER_VS_ACCEPTED => scaler_vs_accepted, + SCALER_MUX1 => scaler_mux1, + SCALER_MUX2 => scaler_mux2, + CAL_TRIGGER_DISABLE => cal_trigger_disable, + COM_RUN => com_run, + DTU_ERROR => dtu_error, + HPV => HPV, + HPW => HPW + ); +---------------------I/O ecl port settings and led configuration --------------------------------- +-- tin(16 downto 9) <= (others => '0'); + EN(4 downto 1) <= "1011"; +-- en(2) <= '1'; -- I/O channel 9 to 16 is an output if 0 +-- tin(8 downto 1) <= (others => '0'); +-- en(1) <= '1'; -- I/O channel 1 to 8 is an output if 0 + FLED_T(5 downto 1) <= not INPUT_ENABLE(5 downto 1); -- input LEDs +------------------------------decoder for data registers ----------------------------------------- + process(CK50) + begin + if rising_edge(CK50) then + if CKCSR = '1' then --read from VME bus + case (U_AD_REG(17 downto 2)) is + when x"0000" => delay_register_1 <= U_DAT_IN(3 downto 0); + when x"0001" => delay_register_2 <= U_DAT_IN(3 downto 0); + when x"0002" => delay_register_3 <= U_DAT_IN(3 downto 0); + when x"0003" => delay_register_4 <= U_DAT_IN(3 downto 0); + when x"0004" => delay_register_5 <= U_DAT_IN(3 downto 0); + when x"0005" => delay_register_ts <= U_DAT_IN(3 downto 0); + when x"0006" => delay_register_vs <= U_DAT_IN(3 downto 0); + when x"0007" => downscale_register_1 <= U_DAT_IN(3 downto 0); + when x"0008" => downscale_register_2 <= U_DAT_IN(3 downto 0); + when x"0009" => downscale_register_3 <= U_DAT_IN(3 downto 0); + when x"000a" => downscale_register_4 <= U_DAT_IN(3 downto 0); + when x"000b" => downscale_register_5 <= U_DAT_IN(3 downto 0); + when x"000c" => downscale_register_ts <= U_DAT_IN(3 downto 0); + when x"000d" => downscale_register_vs <= U_DAT_IN(3 downto 0); + when x"000e" => downscale_register_clock <= U_DAT_IN(3 downto 0); + when x"000f" => width_register_1 <= U_DAT_IN(3 downto 0); + when x"0010" => width_register_2 <= U_DAT_IN(3 downto 0); + when x"0011" => width_register_3 <= U_DAT_IN(3 downto 0); + when x"0012" => width_register_4 <= U_DAT_IN(3 downto 0); + when x"0013" => width_register_5 <= U_DAT_IN(3 downto 0); + when x"0014" => width_register_ts <= U_DAT_IN(3 downto 0); + when x"0015" => width_register_vs <= U_DAT_IN(3 downto 0); + when x"0016" => or_on_off <= U_DAT_IN(7 downto 0); + when x"0017" => mux_selector_1 <= U_DAT_IN(3 downto 0); + when x"0018" => mux_selector_2 <= U_DAT_IN(3 downto 0); + -- scalers must not be written by command + when x"0020" => input_enable <= U_DAT_IN(6 downto 0); + when x"0021" => width_output <= U_DAT_IN(3 downto 0); + when x"0022" => com_run <= U_DAT_IN(0); + when x"0023" => scaler_reset <= U_DAT_IN(7 downto 0); + when x"0024" => branch_en_with_mdc_tof_width <= U_DAT_IN(4 downto 0); + when x"0025" => scaler_mdc_tof_select <= U_DAT_IN(7 downto 0); + -- scalers must not be written by command + when x"0028" => pti5_ts_alternative <= U_DAT_IN(7 downto 0); + when x"0029" => delay_register_beam <= U_DAT_IN(7 downto 0); + when x"002a" => width_inhibit_register_beam <= U_DAT_IN(7 downto 0); + when x"002b" => width_external_register_beam <= U_DAT_IN(7 downto 0); + when x"002c" => ts_gating_disable <= U_DAT_IN(6 downto 0); + -- scalers must not be written by command + when x"0037" => cal_trigger_disable <= U_DAT_IN(0); + when x"0038" => dtu_error <= U_DAT_IN(0); + when others => null; + end case; + elsif OECSR = '1' then --write to VME bus + case (U_AD_REG(17 downto 2)) is + when x"0000" => U_DATA_O <= x"0000000" & delay_register_1; + when x"0001" => U_DATA_O <= x"0000000" & delay_register_2; + when x"0002" => U_DATA_O <= x"0000000" & delay_register_3; + when x"0003" => U_DATA_O <= x"0000000" & delay_register_4; + when x"0004" => U_DATA_O <= x"0000000" & delay_register_5; + when x"0005" => U_DATA_O <= x"0000000" & delay_register_ts; + when x"0006" => U_DATA_O <= x"0000000" & delay_register_vs; + when x"0007" => U_DATA_O <= x"0000000" & downscale_register_1; + when x"0008" => U_DATA_O <= x"0000000" & downscale_register_2; + when x"0009" => U_DATA_O <= x"0000000" & downscale_register_3; + when x"000a" => U_DATA_O <= x"0000000" & downscale_register_4; + when x"000b" => U_DATA_O <= x"0000000" & downscale_register_5; + when x"000c" => U_DATA_O <= x"0000000" & downscale_register_ts; + when x"000d" => U_DATA_O <= x"0000000" & downscale_register_vs; + when x"000e" => U_DATA_O <= x"0000000" & downscale_register_clock; + when x"000f" => U_DATA_O <= x"0000000" & width_register_1; + when x"0010" => U_DATA_O <= x"0000000" & width_register_2; + when x"0011" => U_DATA_O <= x"0000000" & width_register_3; + when x"0012" => U_DATA_O <= x"0000000" & width_register_4; + when x"0013" => U_DATA_O <= x"0000000" & width_register_5; + when x"0014" => U_DATA_O <= x"0000000" & width_register_ts; + when x"0015" => U_DATA_O <= x"0000000" & width_register_vs; + when x"0016" => U_DATA_O <= x"000000" & or_on_off; + when x"0017" => U_DATA_O <= x"0000000" & mux_selector_1; + when x"0018" => U_DATA_O <= x"0000000" & mux_selector_2; + when x"0019" => U_DATA_O <= scaler_pti1; + when x"001a" => U_DATA_O <= scaler_pti2; + when x"001b" => U_DATA_O <= scaler_pti3; + when x"001c" => U_DATA_O <= scaler_pti4; + when x"001d" => U_DATA_O <= scaler_pti5; + when x"001e" => U_DATA_O <= scaler_ts; + when x"001f" => U_DATA_O <= scaler_vs; + when x"0020" => U_DATA_O <= x"000000" & '0' & input_enable; + when x"0021" => U_DATA_O <= x"0000000" & width_output; + when x"0022" => U_DATA_O <= x"0000000" & "000" & com_run; + when x"0023" => U_DATA_O <= x"000000" & scaler_reset; + when x"0024" => U_DATA_O <= x"000000" & "000" & branch_en_with_mdc_tof_width; + when x"0025" => U_DATA_O <= x"000000" & scaler_mdc_tof_select; + when x"0026" => U_DATA_O <= scaler_mdc; + when x"0027" => U_DATA_O <= scaler_tof; + when x"0028" => U_DATA_O <= x"000000" & pti5_ts_alternative; + when x"0029" => U_DATA_O <= x"000000" & delay_register_beam; + when x"002a" => U_DATA_O <= x"000000" & width_inhibit_register_beam; + when x"002b" => U_DATA_O <= x"000000" & width_external_register_beam; + when x"002c" => U_DATA_O <= x"000000" & '0' & ts_gating_disable; --b0 + when x"002d" => U_DATA_O <= scaler_dead; + when x"002e" => U_DATA_O <= scaler_pti1_accepted; + when x"002f" => U_DATA_O <= scaler_pti2_accepted; + when x"0030" => U_DATA_O <= scaler_pti3_accepted; + when x"0031" => U_DATA_O <= scaler_pti4_accepted; + when x"0032" => U_DATA_O <= scaler_pti5_accepted; + when x"0033" => U_DATA_O <= scaler_ts_accepted; + when x"0034" => U_DATA_O <= scaler_vs_accepted; + when x"0035" => U_DATA_O <= scaler_mux1; + when x"0036" => U_DATA_O <= scaler_mux2; + when x"0037" => U_DATA_O <= x"0000000" & "000" & cal_trigger_disable; + when x"0038" => U_DATA_O <= x"0000000" & "000" & dtu_error; + when others => null; + end case; + end if; + end if; + end process; +end rtl; diff --git a/oldfiles/vulom3/vlogic_1.prj b/oldfiles/vulom3/vlogic_1.prj new file mode 100644 index 0000000..c25b735 --- /dev/null +++ b/oldfiles/vulom3/vlogic_1.prj @@ -0,0 +1,15 @@ +vhdl work "set_width_special.vhd" +vhdl work "set_width.vhd" +vhdl work "scaler_s.vhd" +vhdl work "one_clock_long.vhd" +vhdl work "new_downscale_ck.vhd" +vhdl work "eco_delay.vhd" +vhdl work "downscale.vhd" +vhdl work "delay.vhd" +vhdl work "bus_data_com5.vhd" +vhdl work "beam_ramp.vhd" +vhdl work "trig_box1.vhd" +vhdl work "vmelogic.vhd" +vhdl work "ulogic.vhd" +vhdl work "clocking.vhd" +vhdl work "vlogic_1.vhd" diff --git a/oldfiles/vulom3/vlogic_1.sdc b/oldfiles/vulom3/vlogic_1.sdc new file mode 100644 index 0000000..95e2f2a --- /dev/null +++ b/oldfiles/vulom3/vlogic_1.sdc @@ -0,0 +1,57 @@ +# Synplicity, Inc. constraint file +# /home/marek/vulom3/vlogic_1.sdc +# Written on Mon Apr 28 11:36:24 2008 +# by Synplify Pro, Version 9.0.1 Scope Editor + +# +# Collections +# + +# +# Clocks +# + +define_clock {p:vlogic_1|CKFPL} -name {p:vlogic_1|CKFPL} -freq 110 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 5 -route 0 +define_clock {n:beam_ramp|clk_10Hz} -name {n:beam_ramp|clk_10Hz} -period 1000 -clockgroup Autoconstr_clkgroup_3 -rise 0 -fall 0.5 -route 0 +define_clock {n:CLKDV_BUFG_INST|CLKDV_OUT} -name {n:CLKDV_BUFG_INST|CLKDV_OUT} -freq 55 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 10 -route 0 +define_clock {n:CLKFX_BUFG_INST|CLKFX_OUT} -name {n:CLKFX_BUFG_INST|CLKFX_OUT} -freq 330 -clockgroup Autoconstr_clkgroup_1 -rise 0 -fall 1.5 -route 0 + +# +# Clock to Clock +# + +# +# Inputs/Outputs +# + +# +# Registers +# + +# +# Multi-Cycle Paths +# + +# +# False Paths +# + +# +# Max Delay Paths +# + +# +# Attributes +# + +# +# I/O Standards +# + +# +# Compile Points +# + +# +# Other +# diff --git a/oldfiles/vulom3/vlogic_1.ucf b/oldfiles/vulom3/vlogic_1.ucf new file mode 100644 index 0000000..3e37e67 --- /dev/null +++ b/oldfiles/vulom3/vlogic_1.ucf @@ -0,0 +1,249 @@ +NET "AD<0>" LOC = "V16" | IOSTANDARD = "LVTTL"; +NET "AD<1>" LOC = "V15" | IOSTANDARD = "LVTTL"; +NET "AD<2>" LOC = "V6" | IOSTANDARD = "LVTTL"; +NET "AD<3>" LOC = "V5" | IOSTANDARD = "LVTTL"; +NET "AD<4>" LOC = "T14" | IOSTANDARD = "LVTTL"; +NET "AD<5>" LOC = "U13" | IOSTANDARD = "LVTTL"; +NET "AD<6>" LOC = "U8" | IOSTANDARD = "LVTTL"; +NET "AD<7>" LOC = "T7" | IOSTANDARD = "LVTTL"; +NET "AD<8>" LOC = "V13" | IOSTANDARD = "LVTTL"; +NET "AD<9>" LOC = "V12" | IOSTANDARD = "LVTTL"; +NET "AD<10>" LOC = "V9" | IOSTANDARD = "LVTTL"; +NET "AD<11>" LOC = "V8" | IOSTANDARD = "LVTTL"; +NET "AD<12>" LOC = "U12" | IOSTANDARD = "LVTTL"; +NET "AD<13>" LOC = "V11" | IOSTANDARD = "LVTTL"; +NET "AD<14>" LOC = "V10" | IOSTANDARD = "LVTTL"; +NET "AD<15>" LOC = "U9" | IOSTANDARD = "LVTTL"; +NET "AD<16>" LOC = "W13" | IOSTANDARD = "LVTTL"; +NET "AD<17>" LOC = "W12" | IOSTANDARD = "LVTTL"; +NET "AD<18>" LOC = "Y5" | IOSTANDARD = "LVTTL"; +NET "AD<19>" LOC = "W5" | IOSTANDARD = "LVTTL"; +NET "AD<20>" LOC = "Y12" | IOSTANDARD = "LVTTL"; +NET "AD<21>" LOC = "Y11" | IOSTANDARD = "LVTTL"; +NET "AD<22>" LOC = "Y6" | IOSTANDARD = "LVTTL"; +NET "AD<23>" LOC = "W6" | IOSTANDARD = "LVTTL"; +NET "AD<24>" LOC = "W11" | IOSTANDARD = "LVTTL"; +NET "AD<25>" LOC = "W10" | IOSTANDARD = "LVTTL"; +NET "AD<26>" LOC = "Y7" | IOSTANDARD = "LVTTL"; +NET "AD<27>" LOC = "W7" | IOSTANDARD = "LVTTL"; +NET "AD<28>" LOC = "Y10" | IOSTANDARD = "LVTTL"; +NET "AD<29>" LOC = "Y9" | IOSTANDARD = "LVTTL"; +NET "AD<30>" LOC = "W9" | IOSTANDARD = "LVTTL"; +NET "AD<31>" LOC = "W8" | IOSTANDARD = "LVTTL"; +NET "AI<0>" LOC = "L19" | IOSTANDARD = "LVTTL"; +NET "AI<1>" LOC = "M19" | IOSTANDARD = "LVTTL"; +NET "ASI" LOC = "R17" | IOSTANDARD = "LVTTL"; +NET "BERR" LOC = "U16" | IOSTANDARD = "LVTTL"; +NET "BERRO" LOC = "V20" | IOSTANDARD = "LVTTL"; +NET "BLTACK" LOC = "U17" | IOSTANDARD = "LVTTL"; +NET "CAIV" LOC = "R19" | IOSTANDARD = "LVTTL"; +NET "CKFNL" LOC = "B7" | IOSTANDARD = "LVTTL"; +NET "CKFPL" LOC = "A7" | IOSTANDARD = "LVTTL"; +NET "CON<0>" LOC = "F18" | IOSTANDARD = "LVTTL"; +NET "CON<1>" LOC = "E18" | IOSTANDARD = "LVTTL"; +NET "CON<2>" LOC = "C18" | IOSTANDARD = "LVTTL"; +NET "CON<3>" LOC = "C19" | IOSTANDARD = "LVTTL"; +NET "CON<4>" LOC = "F16" | IOSTANDARD = "LVTTL"; +NET "CON<5>" LOC = "F17" | IOSTANDARD = "LVTTL"; +NET "CON<6>" LOC = "D19" | IOSTANDARD = "LVTTL"; +NET "CON<7>" LOC = "E19" | IOSTANDARD = "LVTTL"; +NET "CON<8>" LOC = "G16" | IOSTANDARD = "LVTTL"; +NET "CON<9>" LOC = "G17" | IOSTANDARD = "LVTTL"; +NET "CON<10>" LOC = "E20" | IOSTANDARD = "LVTTL"; +NET "CON<11>" LOC = "F20" | IOSTANDARD = "LVTTL"; +NET "CON<12>" LOC = "H16" | IOSTANDARD = "LVTTL"; +NET "CON<13>" LOC = "H17" | IOSTANDARD = "LVTTL"; +NET "CON<14>" LOC = "F19" | IOSTANDARD = "LVTTL"; +NET "CON<15>" LOC = "G19" | IOSTANDARD = "LVTTL"; +NET "DI<0>" LOC = "N17" | IOSTANDARD = "LVTTL"; +NET "DI<1>" LOC = "N18" | IOSTANDARD = "LVTTL"; +NET "DI<2>" LOC = "N19" | IOSTANDARD = "LVTTL"; +NET "DI<3>" LOC = "P16" | IOSTANDARD = "LVTTL"; +NET "DI<4>" LOC = "P17" | IOSTANDARD = "LVTTL"; +NET "DI<5>" LOC = "P19" | IOSTANDARD = "LVTTL"; +NET "DI<6>" LOC = "P20" | IOSTANDARD = "LVTTL"; +#NET "DOUT_LCD" LOC = "M16" | IOSTANDARD = "LVTTL"; +NET "DS0I" LOC = "T19" | IOSTANDARD = "LVTTL"; +NET "DS1I" LOC = "T20" | IOSTANDARD = "LVTTL"; +NET "ECL<1>" LOC = "B15" | IOSTANDARD = "LVTTL"; +NET "ECL<2>" LOC = "A15" | IOSTANDARD = "LVTTL"; +NET "ECL<3>" LOC = "A16" | IOSTANDARD = "LVTTL"; +NET "ECL<4>" LOC = "B16" | IOSTANDARD = "LVTTL"; +NET "ECL<5>" LOC = "C15" | IOSTANDARD = "LVTTL"; +NET "ECL<6>" LOC = "C16" | IOSTANDARD = "LVTTL"; +NET "ECL<7>" LOC = "B17" | IOSTANDARD = "LVTTL"; +NET "ECL<8>" LOC = "C17" | IOSTANDARD = "LVTTL"; +NET "ECL<9>" LOC = "D16" | IOSTANDARD = "LVTTL"; +NET "ECL<10>" LOC = "E16" | IOSTANDARD = "LVTTL"; +NET "ECL<11>" LOC = "A18" | IOSTANDARD = "LVTTL"; +NET "ECL<12>" LOC = "B18" | IOSTANDARD = "LVTTL"; +NET "ECL<13>" LOC = "D17" | IOSTANDARD = "LVTTL"; +NET "ECL<14>" LOC = "D18" | IOSTANDARD = "LVTTL"; +NET "ECL<15>" LOC = "B19" | IOSTANDARD = "LVTTL"; +NET "ECL<16>" LOC = "C20" | IOSTANDARD = "LVTTL"; +NET "ECO<1>" LOC = "A5" | IOSTANDARD = "LVTTL"; +NET "ECO<2>" LOC = "B5" | IOSTANDARD = "LVTTL"; +NET "ECO<3>" LOC = "C6" | IOSTANDARD = "LVTTL"; +NET "ECO<4>" LOC = "C5" | IOSTANDARD = "LVTTL"; +NET "ECO<5>" LOC = "B4" | IOSTANDARD = "LVTTL"; +NET "ECO<6>" LOC = "C4" | IOSTANDARD = "LVTTL"; +NET "ECO<7>" LOC = "D5" | IOSTANDARD = "LVTTL"; +NET "ECO<8>" LOC = "E5" | IOSTANDARD = "LVTTL"; +NET "ECO<9>" LOC = "A3" | IOSTANDARD = "LVTTL"; +NET "ECO<10>" LOC = "B3" | IOSTANDARD = "LVTTL"; +NET "ECO<11>" LOC = "D4" | IOSTANDARD = "LVTTL"; +NET "ECO<12>" LOC = "D3" | IOSTANDARD = "LVTTL"; +NET "ECO<13>" LOC = "B2" | IOSTANDARD = "LVTTL"; +NET "ECO<14>" LOC = "C1" | IOSTANDARD = "LVTTL"; +NET "ECO<15>" LOC = "F3" | IOSTANDARD = "LVTTL"; +NET "ECO<16>" LOC = "E3" | IOSTANDARD = "LVTTL"; +NET "EN<1>" LOC = "M20" | IOSTANDARD = "LVTTL"; +NET "EN<2>" LOC = "L20" | IOSTANDARD = "LVTTL"; +NET "EN<3>" LOC = "M17" | IOSTANDARD = "LVTTL"; +NET "EN<4>" LOC = "M18" | IOSTANDARD = "LVTTL"; +NET "FLED<1>" LOC = "H20" | IOSTANDARD = "LVTTL"; +NET "FLED<2>" LOC = "J15" | IOSTANDARD = "LVTTL"; +NET "FLED<3>" LOC = "J16" | IOSTANDARD = "LVTTL"; +NET "FLED<4>" LOC = "H18" | IOSTANDARD = "LVTTL"; +NET "FLED<5>" LOC = "H19" | IOSTANDARD = "LVTTL"; +NET "FLED<6>" LOC = "G20" | IOSTANDARD = "LVTTL"; +NET "HPV<0>" LOC = "H1" | IOSTANDARD = "LVTTL" | SLEW = SLOW ; +NET "HPV<1>" LOC = "G1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<2>" LOC = "J6" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<3>" LOC = "J5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<4>" LOC = "H3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<5>" LOC = "H2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<6>" LOC = "K5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<7>" LOC = "K4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<8>" LOC = "K1" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<9>" LOC = "J2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<10>" LOC = "L5" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<11>" LOC = "L4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<12>" LOC = "K3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<13>" LOC = "K2" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<14>" LOC = "M4" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPV<15>" LOC = "M3" | IOSTANDARD = "LVTTL"| SLEW = SLOW ; +NET "HPW<0>" LOC = "C3" | IOSTANDARD = "LVTTL"; +NET "HPW<1>" LOC = "C2" | IOSTANDARD = "LVTTL"; +NET "HPW<2>" LOC = "F5" | IOSTANDARD = "LVTTL"; +NET "HPW<3>" LOC = "F4" | IOSTANDARD = "LVTTL"; +NET "HPW<4>" LOC = "D2" | IOSTANDARD = "LVTTL"; +NET "HPW<5>" LOC = "E2" | IOSTANDARD = "LVTTL"; +NET "HPW<6>" LOC = "G5" | IOSTANDARD = "LVTTL"; +NET "HPW<7>" LOC = "G4" | IOSTANDARD = "LVTTL"; +NET "HPW<8>" LOC = "E1" | IOSTANDARD = "LVTTL"; +NET "HPW<9>" LOC = "F1" | IOSTANDARD = "LVTTL"; +NET "HPW<10>" LOC = "H5" | IOSTANDARD = "LVTTL"; +NET "HPW<11>" LOC = "H4" | IOSTANDARD = "LVTTL"; +NET "HPW<12>" LOC = "F2" | IOSTANDARD = "LVTTL"; +NET "HPW<13>" LOC = "G2" | IOSTANDARD = "LVTTL"; +NET "HPW<14>" LOC = "J4" | IOSTANDARD = "LVTTL"; +NET "HPW<15>" LOC = "J3" | IOSTANDARD = "LVTTL"; +NET "IACKII" LOC = "T15" | IOSTANDARD = "LVTTL"; +NET "IACKOU" LOC = "U15" | IOSTANDARD = "LVTTL"; +NET "IOO<1>" LOC = "B12" | IOSTANDARD = "LVTTL"; +NET "IOO<2>" LOC = "A11" | IOSTANDARD = "LVTTL"; +NET "IOO<3>" LOC = "A10" | IOSTANDARD = "LVTTL"; +NET "IOO<4>" LOC = "B9" | IOSTANDARD = "LVTTL"; +NET "IOO<5>" LOC = "C11" | IOSTANDARD = "LVTTL"; +NET "IOO<6>" LOC = "B11" | IOSTANDARD = "LVTTL"; +NET "IOO<7>" LOC = "B10" | IOSTANDARD = "LVTTL"; +NET "IOO<8>" LOC = "C10" | IOSTANDARD = "LVTTL"; +NET "IOO<9>" LOC = "B13" | IOSTANDARD = "LVTTL"; +NET "IOO<10>" LOC = "A13" | IOSTANDARD = "LVTTL"; +NET "IOO<11>" LOC = "A8" | IOSTANDARD = "LVTTL"; +NET "IOO<12>" LOC = "B8" | IOSTANDARD = "LVTTL"; +NET "IOO<13>" LOC = "B14" | IOSTANDARD = "LVTTL"; +NET "IOO<14>" LOC = "A14" | IOSTANDARD = "LVTTL"; +NET "IOO<15>" LOC = "B6" | IOSTANDARD = "LVTTL"; +NET "IOO<16>" LOC = "A6" | IOSTANDARD = "LVTTL"; +NET "IRBLO" LOC = "V19" | IOSTANDARD = "LVTTL"; +NET "LEMIN<1>" LOC = "R4" | IOSTANDARD = "LVTTL"; +NET "LEMIN<2>" LOC = "R3" | IOSTANDARD = "LVTTL"; +NET "LEMOU<1>" LOC = "T2" | IOSTANDARD = "LVTTL"; +NET "LEMOU<2>" LOC = "T1" | IOSTANDARD = "LVTTL"; +NET "OAIV" LOC = "R20" | IOSTANDARD = "LVTTL"; +NET "PRES" LOC = "U19" | IOSTANDARD = "LVTTL"; +NET "RES<1>" LOC = "T18" | IOSTANDARD = "LVTTL"; +NET "RES<2>" LOC = "U18" | IOSTANDARD = "LVTTL"; +NET "SAD<0>" LOC = "M1" | IOSTANDARD = "LVTTL"; +NET "SAD<1>" LOC = "L1" | IOSTANDARD = "LVTTL"; +NET "SAD<2>" LOC = "M6" | IOSTANDARD = "LVTTL"; +NET "SAD<3>" LOC = "M5" | IOSTANDARD = "LVTTL"; +NET "SAD<4>" LOC = "M2" | IOSTANDARD = "LVTTL"; +NET "SAD<5>" LOC = "L2" | IOSTANDARD = "LVTTL"; +NET "SAD<6>" LOC = "N5" | IOSTANDARD = "LVTTL"; +NET "SAD<7>" LOC = "N4" | IOSTANDARD = "LVTTL"; +NET "SAD<8>" LOC = "N3" | IOSTANDARD = "LVTTL"; +NET "SAD<9>" LOC = "N2" | IOSTANDARD = "LVTTL"; +NET "SAD<10>" LOC = "P5" | IOSTANDARD = "LVTTL"; +NET "SAD<11>" LOC = "P4" | IOSTANDARD = "LVTTL"; +NET "SAD<12>" LOC = "P2" | IOSTANDARD = "LVTTL"; +NET "SAD<13>" LOC = "P1" | IOSTANDARD = "LVTTL"; +NET "SAD<14>" LOC = "R2" | IOSTANDARD = "LVTTL"; +NET "SAD<15>" LOC = "R1" | IOSTANDARD = "LVTTL"; +NET "SAD<16>" LOC = "R6" | IOSTANDARD = "LVTTL"; +NET "SAD<17>" LOC = "R5" | IOSTANDARD = "LVTTL"; +NET "SCS" LOC = "V18" | IOSTANDARD = "LVTTL"; +NET "SDA<0>" LOC = "U3" | IOSTANDARD = "LVTTL"; +NET "SDA<1>" LOC = "U2" | IOSTANDARD = "LVTTL"; +NET "SDA<2>" LOC = "T4" | IOSTANDARD = "LVTTL"; +NET "SDA<3>" LOC = "T3" | IOSTANDARD = "LVTTL"; +NET "SDA<4>" LOC = "T6" | IOSTANDARD = "LVTTL"; +NET "SDA<5>" LOC = "U6" | IOSTANDARD = "LVTTL"; +NET "SDA<6>" LOC = "V2" | IOSTANDARD = "LVTTL"; +NET "SDA<7>" LOC = "V1" | IOSTANDARD = "LVTTL"; +NET "SDA<8>" LOC = "U5" | IOSTANDARD = "LVTTL"; +NET "SDA<9>" LOC = "U4" | IOSTANDARD = "LVTTL"; +NET "SDA<10>" LOC = "W3" | IOSTANDARD = "LVTTL"; +NET "SDA<11>" LOC = "W2" | IOSTANDARD = "LVTTL"; +NET "SDA<12>" LOC = "Y4" | IOSTANDARD = "LVTTL"; +NET "SDA<13>" LOC = "W4" | IOSTANDARD = "LVTTL"; +NET "SDA<14>" LOC = "V4" | IOSTANDARD = "LVTTL"; +NET "SDA<15>" LOC = "V3" | IOSTANDARD = "LVTTL"; +NET "SOE" LOC = "V17" | IOSTANDARD = "LVTTL"; +NET "SWE" LOC = "W17" | IOSTANDARD = "LVTTL"; +NET "TIN<1>" LOC = "F15" | IOSTANDARD = "LVTTL"; +NET "TIN<2>" LOC = "E15" | IOSTANDARD = "LVTTL"; +NET "TIN<3>" LOC = "E6" | IOSTANDARD = "LVTTL"; +NET "TIN<4>" LOC = "F6" | IOSTANDARD = "LVTTL"; +NET "TIN<5>" LOC = "D15" | IOSTANDARD = "LVTTL"; +NET "TIN<6>" LOC = "E14" | IOSTANDARD = "LVTTL"; +NET "TIN<7>" LOC = "E7" | IOSTANDARD = "LVTTL"; +NET "TIN<8>" LOC = "D6" | IOSTANDARD = "LVTTL"; +NET "TIN<9>" LOC = "D13" | IOSTANDARD = "LVTTL"; +NET "TIN<10>" LOC = "C13" | IOSTANDARD = "LVTTL"; +NET "TIN<11>" LOC = "C8" | IOSTANDARD = "LVTTL"; +NET "TIN<12>" LOC = "D8" | IOSTANDARD = "LVTTL"; +NET "TIN<13>" LOC = "D12" | IOSTANDARD = "LVTTL"; +NET "TIN<14>" LOC = "C12" | IOSTANDARD = "LVTTL"; +NET "TIN<15>" LOC = "C9" | IOSTANDARD = "LVTTL"; +NET "TIN<16>" LOC = "D9" | IOSTANDARD = "LVTTL"; +NET "WRDIS" LOC = "N16" | IOSTANDARD = "LVTTL"; +NET "WRI" LOC = "R18" | IOSTANDARD = "LVTTL"; +#NET "CKFNL" TNM_NET = CKFNL; +#TIMESPEC TS_CKFNL = PERIOD "CKFNL" 100 MHz; +NET "CKFPL" TNM_NET = CKFPL; +TIMESPEC TS_CKFPL = PERIOD "CKFPL" 100 MHz; + + +#NET "ulg_1/trgb_1/Inst_beam_ramp/clk_10Hz" TNM_NET=ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz ; +#TIMESPEC TS_ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz = PERIOD "ulg_1_trgb_1_Inst_beam_ramp_clk_10Hz" 1 MHz;# Generated by Xilinx Architecture Wizard +# --- UCF Template Only --- +# Cut and paste these attributes into the project's UCF file, if desired +#INST DCM_ADV_INST CLK_FEEDBACK = 1X; +#INST DCM_ADV_INST CLKDV_DIVIDE = 2.0; +#INST DCM_ADV_INST CLKFX_DIVIDE = 1; +#INST DCM_ADV_INST CLKFX_MULTIPLY = 3; +#INST DCM_ADV_INST CLKIN_DIVIDE_BY_2 = FALSE; +#INST DCM_ADV_INST CLKIN_PERIOD = 10.000; +#INST DCM_ADV_INST CLKOUT_PHASE_SHIFT = NONE; +#INST DCM_ADV_INST DCM_AUTOCALIBRATION = TRUE; +#INST DCM_ADV_INST DCM_PERFORMANCE_MODE = MAX_SPEED; +#INST DCM_ADV_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; +#INST DCM_ADV_INST DFS_FREQUENCY_MODE = HIGH; +#INST DCM_ADV_INST DLL_FREQUENCY_MODE = LOW; +#INST DCM_ADV_INST DUTY_CYCLE_CORRECTION = TRUE; +#INST DCM_ADV_INST FACTORY_JF = F0F0; +#INST DCM_ADV_INST PHASE_SHIFT = 0; +#INST DCM_ADV_INST STARTUP_WAIT = FALSE; diff --git a/oldfiles/vulom3/vlogic_1.vhd b/oldfiles/vulom3/vlogic_1.vhd new file mode 100644 index 0000000..7cb8e81 --- /dev/null +++ b/oldfiles/vulom3/vlogic_1.vhd @@ -0,0 +1,261 @@ +-------------------------------------------------------------------------------- +-- Company: GSI +-- Engineer: Jan Hoffman, Davide Leoni +-- +-- Create Date: 8/8/07 +-- Design Name: vulom3 +-- Module Name: vlogic_1 - Behavioral +-- Project Name: triggerbox +-- Target Device: XC4VLX25-10SF363 +-- Tool versions: +-- Description: Top module, DCM, display, LEDs, VME signals +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +Library UNISIM; +use UNISIM.vcomponents.all; + +entity vlogic_1 is + port ( +--............................. VME Signals ............................................ + AD : inout std_logic_vector(31 downto 0); -- VME Address-Data bus + AMI : in std_logic_vector(5 downto 0); -- VME Address modifier internal + ASI : in std_logic; -- Address strobe + WRI : in std_logic; -- write + BERR : in std_logic; -- bus error for chain block transfer + BERRO : out std_logic; -- bus error for chain block transfer + DS0I : in std_logic; -- data strobe + DS1I : in std_logic; -- data strobe + IACKII : in std_logic; -- interrupt acknowledge chain + IACKOU : out std_logic; -- interrupt acknowledge chain + IRBLO : out std_logic; -- interrupt 4 output to VME or BLACK output +-- MON : in std_logic_vector(7 downto 0); -- VME module number connected to hex. switch VN2 .. VN1 +--............................. Buffer/Register Controll Signals ............................................ + CAIV : out std_logic; -- Address buffer clock signal Int->VME + OAIV : out std_logic; -- Address buffer OE Int->VME +--............................. Front panel Controll Signals ............................................ + ECO : inout std_logic_vector(16 downto 1); --signals to ECL output(1 is the lower connector of ECL OUT) + EN : out std_logic_vector(4 downto 1); -- ECL enable (EN1 for ch. 1-8, EN2 for ch. 9-16) + ECL : in std_logic_vector(16 downto 1); -- signals from ECL input (1 is at the lower connector of ECL IN) + IOO : in std_logic_vector(16 downto 1); -- signals ioo from ECL I/O (1 is at the lower connector) + TIN : inout std_logic_vector(16 downto 1); -- output signals to ECL I/O (1 is at the lower connector) + LEMIN : in std_logic_vector(2 downto 1); -- signals from LEMO upper + LEMOU : out std_logic_vector(2 downto 1); -- signals to LEMO lower +--............................. SRAM Controll Signals ............................................ + SAD : out std_logic_vector(17 downto 0); -- address + SDA : inout std_logic_vector(15 downto 0); -- data + SCS : out std_logic; + SOE : out std_logic; + SWE : out std_logic; +--............................. DISPLAY and LED Controll Signals ............................................ + DI : inout std_logic_vector(6 downto 0); + AI : out std_logic_vector(1 downto 0); -- display address ( use 1 and 2 only, 0 and 3 can't be seen) + WRDIS : out std_logic; -- display write + FLED : out std_logic_vector(6 downto 1); -- Front panel LED +--............................. Euroball Readot Signals ............................................ +-- PASSO : over HPV or HPW +-- RENI : over HPV or HPW + BLTACK : in std_logic; +--............................. System Signals ............................................ + PRES : in std_logic; -- reset positive from reset IC +-- SRESI : in std_logic; -- reset from VME + RES : in std_logic_vector(2 downto 1); -- reset from CPLD + CKFNL : in std_logic; -- Diff 100 MHz ck neg + CKFPL : in std_logic; -- Diff 100 MHz ck pos + CON : inout std_logic_vector(15 downto 0); -- Connection between PROG and vlogic_1 + HPV : inout std_logic_vector(15 downto 0); -- Logic analyzer signals + HPW : inout std_logic_vector(15 downto 0) -- Logic analyzer signals + ); +end vlogic_1; +architecture rtl of vlogic_1 is +component clocking +port( + CLKIN_IN : IN std_logic; + CLKDV_OUT : OUT std_logic; + CLKFX_OUT : OUT std_logic; + CLKIN_IBUFG_OUT : OUT std_logic; + CLK0_OUT : OUT std_logic; + LOCKED_OUT : OUT std_logic + ); +end component; +component ulogic port ( + RESET : in std_logic; + CK50 : in std_logic; + CK300 : in std_logic; + CK100 : in std_logic; + LEMOU : out std_logic_vector(2 downto 1); + LEMIN : in std_logic_vector(2 downto 1); + TIN : out std_logic_vector(16 downto 1); + ECO : out std_logic_vector(16 downto 1); + ECL : in std_logic_vector(16 downto 1); + IOO : in std_logic_vector(16 downto 1); + EN : out std_logic_vector(4 downto 1); + FLED_T: out std_logic_vector(6 downto 1); -- to front panel LEDs +--............................. vme interface .................... + U_AD_REG : in std_logic_vector(21 downto 2); + U_DAT_IN : in std_logic_vector(31 downto 0); + U_DATA_O : out std_logic_vector(31 downto 0); + OECSR, CKCSR : in std_logic; + HPV : inout std_logic_vector(15 downto 0); + HPW : inout std_logic_vector(15 downto 0) + ); +end component; + +component vmelogic port ( + ASIS :in std_logic; -- + DSR :in std_logic; -- + AD :inout std_logic_vector(31 downto 0); + AD_REG :inout std_logic_vector(31 downto 0); + WRI :in std_logic; + AMI :in std_logic_vector(5 downto 0); + CKCSR :out std_logic; -- clock data into csr + OECSR :out std_logic; -- output data from csr to VME + CON :inout std_logic_vector(15 downto 0); + HPLB :out std_logic_vector(15 downto 0); + CK50 :in std_logic + ); +end component; +signal reset : std_logic; +signal count : std_logic_vector (23 downto 0); +signal counth : std_logic_vector (27 downto 0); +signal counf : std_logic_vector (7 downto 0); +------------------------------------------------------------------------------------------------ +signal tri_dat : std_logic_vector (15 downto 0); -- trigger bus level data +signal led_out : std_logic_vector (4 downto 1); -- 4 LEDs, on piggy +signal lemo_dat : std_logic_vector (15 downto 0); -- 4 bit data from LEMO input +signal enable, oecsr, ckcsr, asis, dsr : std_logic; -- enable internal data bus to outside of fpga +signal mres, sta_dis : std_logic; -- internal acknowledge +signal din, dadis : std_logic_vector (31 downto 0); -- internal data bus, CSR +-------------------------------------------------------------------------------------------------- +signal en_trcnt : std_logic; +constant tr_cnt_dat : std_logic_vector(7 downto 0) := x"20"; +signal tr_cnt : std_logic_vector(7 downto 0); +signal u_ad_reg : std_logic_vector(21 downto 2); +signal u_dat_in, u_data_o, ad_reg, pdone :std_logic_vector(31 downto 0); +signal dis_out :std_logic_vector (1 downto 0); +signal fled_t : std_logic_vector(6 downto 1); +-- +signal hp : std_logic_vector (3 downto 0); -- states of flash machine +signal hplb : std_logic_vector (15 downto 0); -- +signal prova, to_LED6, SOFT_RESET : std_logic; +---------------------------- +signal rst, clk2x, clk0, ck50, ck300, ck100, locked : std_logic; -- internal acknowledge +begin + Inst_clocking : clocking port map( + CLKIN_IN => CKFPL, + CLKDV_OUT => ck50, --50MHz clock + CLKFX_OUT => ck300, --300MHz clock + CLKIN_IBUFG_OUT => open, + CLK0_OUT => ck100, --100MHz clock + LOCKED_OUT => to_led6); + ulg_1 : ulogic port map ( + RESET => reset, + CK50 => CK50, + CK300 => CK300, + CK100 => CK100, + LEMIN => LEMIN, + LEMOU => LEMOU, + TIN => TIN, + EN => EN, + ECO => ECO, + ECL => ECL, + IOO => IOO, + FLED_T => fled_t, + U_AD_REG => u_ad_reg, + U_DAT_IN => u_dat_in, + U_DATA_O => u_data_o, + OECSR => oecsr, + CKCSR => ckcsr, + HPV => HPV, + HPW => HPW + ); + vme_1 : vmelogic port map ( + ASIS => asis, + DSR => dsr, + AD => ad, + AD_REG => ad_reg, + WRI => WRI, + AMI => AMI, + CKCSR => ckcsr, + OECSR => oecsr, + CON => CON, + HPLB => hplb, + CK50 => ck50); +--------------------------------------------------------------------------------------------- +--...............................RESET signal............................................ + reset <= PRES or res(1); -- or not SRESI; -- PRES active high from power IC, + -- SRESI active low from VME +---------------------------------PANEL LED--------------------------------------------------- + process (ck50) + begin + if rising_edge(ck50) then + FLED(6) <= not to_led6; --led on if pll is working + FLED(5 downto 1) <= fled_t(5 downto 1); --leds on if inputs enabled + end if; + end process; +--............................... signals to/from CPLD ....................................... + mres <= '1'; +--............................... display ....................................... + process (ck50) + begin + if (ck50'event and ck50 = '1') then + count <= count + 1; + end if; + end process; + process (count(4)) + begin + if rising_edge(count(4)) then + WRDIS <= count(5); + if count(6) = '0' then + AI <= "01"; + DI <= CONV_STD_LOGIC_VECTOR(51, 7); -- 33h "3" ascii + else + AI <= "10"; + DI <= CONV_STD_LOGIC_VECTOR(50, 7); -- 32h "2" ascii + end if; + end if; + end process; +--............................. VME Signals ............................................ + BERRO <= '1'; -- H means inactive + IACKOU <= IACKII; -- interrupt acknowledge chain +-- SRESI -- system reset + process(ck50, asi, ds0i, ds1i) + begin + if (ck50'event and ck50 = '1') then + asis <= not asi; + dsr <= not ds0i and not ds1i; -- synchronized DS input from VME + end if; + end process; +--------------------------- VME address buffer control signals ------------------------------- + CAIV <= '1'; -- clock for address register internal<-VME, disabled + OAIV <= '1'; -- OE for address register internal<-VME, disabled + u_ad_reg <= ad_reg(21 downto 2); + u_dat_in <= ad; +----------------------- DATA MULTIPLEXER for OUTPUT to VME ------------------------------------------- + process(ck50) + begin + if (ck50'event and ck50 = '1') then + if (oecsr = '1') then + din <= u_data_o; -- data to VME over AD bus +-- elsif (dis_out(1)='1') then din <= dadis; -- display data over AD bus not necessary with vulom3 /*/*/*/*/*/ + else + din <= (others => '0'); + end if; + end if; + end process; + enable <= oecsr; --or dis_out(1); -- address and data bus output not necessary with vulom3 /*/*/*/*/*/ + AD <= din when enable = '1' else (others => 'Z'); +----------------------------------- end of VME ----------------------------------------------- +------------------------------------------------------------------------------- +-- * UNUSED @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Unused Signals @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +--------------------------------------------------------------------------------- + IRBLO <= '1'; + SCS <= '1'; + SOE <= '0'; + SWE <= '0'; + SAD <= (others => '0'); +-- con(15 downto 7) <= b"000000000"; +end rtl; diff --git a/oldfiles/vulom3/vlogic_1_syn.prj b/oldfiles/vulom3/vlogic_1_syn.prj new file mode 100644 index 0000000..6f6c43c --- /dev/null +++ b/oldfiles/vulom3/vlogic_1_syn.prj @@ -0,0 +1,76 @@ +#-- Synplicity, Inc. +#-- Version 9.0 +#-- Project file /home/marek/vulom3/vlogic_1_syn.prj +#-- Written on Mon Apr 28 11:33:20 2008 + + +#add_file options +add_file -vhdl -lib work "vlogic_1.vhd" +add_file -vhdl -lib work "clocking.vhd" +add_file -vhdl -lib work "ulogic.vhd" +add_file -vhdl -lib work "vmelogic.vhd" +add_file -vhdl -lib work "trig_box1.vhd" +add_file -vhdl -lib work "one_clock_long.vhd" +add_file -vhdl -lib work "delay.vhd" +add_file -vhdl -lib work "downscale.vhd" +add_file -vhdl -lib work "set_width.vhd" +add_file -vhdl -lib work "set_width_special.vhd" +add_file -vhdl -lib work "scaler.vhd" +add_file -vhdl -lib work "scaler_s.vhd" +add_file -vhdl -lib work "eco_delay.vhd" +add_file -vhdl -lib work "new_downscale_ck.vhd" +add_file -vhdl -lib work "beam_ramp.vhd" +add_file -vhdl -lib work "bus_data_com5.vhd" +add_file -constraint "vlogic_1.sdc" + + +#implementation: "workdir" +impl -add workdir -type fpga + +#device options +set_option -technology VIRTEX4 +set_option -part XC4VLX15 +set_option -package SF363 +set_option -speed_grade -10 + +#compilation/mapping options +set_option -default_enum_encoding default +set_option -resource_sharing 1 +set_option -use_fsm_explorer 1 +set_option -top_module "vlogic_1" + +#map options +set_option -frequency 110.000 +set_option -run_prop_extract 0 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -pipe 1 +set_option -update_models_cp 1 +set_option -verification_mode 0 +set_option -retiming 1 +set_option -no_sequential_opt 0 +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 + + +#sequential_optimizations options +set_option -symbolic_fsm_compiler 1 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "workdir/vlogic_1.edf" + +# +#implementation attributes + +set_option -synthesis_onoff_pragma 0 +impl -active "workdir" diff --git a/oldfiles/vulom3/vmelogic.vhd b/oldfiles/vulom3/vmelogic.vhd new file mode 100644 index 0000000..7e1e9bc --- /dev/null +++ b/oldfiles/vulom3/vmelogic.vhd @@ -0,0 +1,247 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +-- +-- vme_1: vmelogic port map (asis=>asis, dsr=>dsr, ad=>ad, wri=>wri, ami=>ami, mon=>mon, con=>con, xxx=>xxx, + + entity vmelogic is + port (asis :in std_logic; -- + dsr :in std_logic; -- + ad :inout std_logic_vector(31 downto 0); + ad_reg :inout std_logic_vector(31 downto 0); + wri :in std_logic; + ami :in std_logic_vector(5 downto 0); +-- mon :in std_logic_vector(7 downto 0); + ckcsr :out std_logic; -- clock data into csr + oecsr :out std_logic; -- output data from csr to VME + con :inout std_logic_vector(15 downto 0); + hplb :out std_logic_vector(15 downto 0); + ck50 :in std_logic + ); +end vmelogic; +-- +architecture RTL of vmelogic is +------------------------------------------------------------------------------------------- +------------------------------- vme signals ----------------------------------------------- +signal ckad : std_logic; -- clock for internal address register +signal stda : std_logic; -- start data phase state machine +signal wrs : std_logic; -- synchronized VME WRITE +signal ack_csr : std_logic; -- internal acknowledge csr +signal ack_hpi : std_logic; -- internal acknowledge hpi +signal ack_fsh : std_logic; -- internal acknowledge flash +signal ack_vr : std_logic; -- internal acknowledge vram 32 +signal aph_sta, dph_sta : std_logic_vector (3 downto 0); -- states of aph machine +signal enable : std_logic; -- enable internal data bus to outside of fpga +--signal vafsh : std_logic_vector (3 downto 0); -- vme address phase outputs for flash +--signal va64 : std_logic_vector (3 downto 0); -- vme data phase for VRAM64 (dual port ram) +signal vdcsr : std_logic_vector (3 downto 0); -- vme data phase outputs for external vme buffer register +signal amr : std_logic_vector (5 downto 0); -- internal address modifier register for VME address +signal int_res : std_logic_vector (23 downto 22); -- internal address register for VME address +signal sel_rnd : std_logic; -- FLASH, CSR, HPI, DPRAM random access +signal sel_bt32 : std_logic; -- DPRAM BT 32 access +--signal sel_bt64 : std_logic; -- DPRAM BT 64 access +signal selcsr : std_logic; -- CSR selected +signal selflsh : std_logic; -- FLASH selected +signal ad_co : std_logic_vector (1 downto 0); -- vme address phase outputs for: stda = start data phase... +signal csr_o : std_logic_vector (1 downto 0); -- vme data phase outputs for csr +signal pr_ou : std_logic_vector (1 downto 0); -- priority encoder outputs +signal tr_ou : std_logic_vector (15 downto 0); -- priority encoder outputs +signal vram : std_logic; -- vram1 or vram2 32/64 bit selected +signal vulom_sel : std_logic; +signal ckcsro : std_logic_vector (1 downto 0); -- internal CSR +signal oecsro : std_logic_vector (1 downto 0); -- internal CSR +signal din,csrr0,csrr1 : std_logic_vector (31 downto 0); -- internal data bus, CSR +------------------ VME address modifier ------------------------------ +constant am_f :std_logic_vector(5 downto 0) := b"001111";--AM543210=001111 ext. Extended supervisory block transfer +constant am_e :std_logic_vector(5 downto 0) := b"001110";--AM543210=001110 ext. supervisory program access +constant am_d :std_logic_vector(5 downto 0) := b"001101";--AM543210=001101 ext. Extended supervisory data access +constant am_a :std_logic_vector(5 downto 0) := b"001010";--AM543210=001010 ext. Extended non-privileged program access +constant am_b :std_logic_vector(5 downto 0) := b"001011";--AM543210=001011 ext. Extended non-privileged block transfer +constant am_9 :std_logic_vector(5 downto 0) := b"001001";--AM543210=001001 ext. Extended non-privileged data access +constant am_8 :std_logic_vector(5 downto 0) := b"001000";--AM543210=001000 ext. Extended non-privileged 64-bit block transfer +constant am_1b :std_logic_vector(5 downto 0) := b"011011";--AM543210=011011 ext. Eurogram Readout +constant am_29 :std_logic_vector(5 downto 0) := b"101001";--AM543210=101001 ext. Direct Configuration of FPGA +------------------ VME addresses -------------------------------------- +constant csr_ad :std_logic_vector(3 downto 2) := b"00";----vmeaddr=XX00 0000 - XX00 000C +--constant sram_ad :std_logic_vector(3 downto 2) := x"01";----vmeaddr=XX40 0000 - XX40 FFFC +-- ............... vme address phase state machine, states declaration ......................... +type vme_adr_typ is (va00,va01,va02,va03,va04,va05,va0b); -- va06,va07,va08,va09,va0a, +signal vme_adr, vme_anx : vme_adr_typ; +-- ............... vme data phase state machine for CSR ......................... +signal st_csr_drd : std_logic; -- start state machine for CSR read +signal st_csr_dwr : std_logic; -- start state machine for CSR write +type vmdacs_typ is (vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08,vc09,vc0a,vc0b,vc0c,vc0d,vc0e); +signal vmdacs, vmdacs_nx : vmdacs_typ; + +------------------------------------------------------------------------------------------ +begin ---- BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN BEGIN +------------------------------------------------------------------------------------------ +----------------------------------------------------------------------------------------------- +--.......................................................................................... +--...................... VME address phase state machine ....................... + process (vme_adr,asis) -- states are - va00,va01,va02,va03,va04,va05,va06,va07,va08 + begin -- ad_co[]=stda,ckad + case vme_adr is + when va00 => ad_co <= b"00"; aph_sta <= x"0"; + if asis ='1' then vme_anx <= va01; + else vme_anx <= va00; + end if; + when va01 => ad_co <= b"00"; aph_sta <= x"1"; + if asis ='1' then vme_anx <= va02; + else vme_anx <= va00; + end if; + when va02 => vme_anx <= va03; ad_co <= b"00"; aph_sta <= x"2"; + when va03 => vme_anx <= va04; ad_co <= b"00"; aph_sta <= x"3"; + when va04 => vme_anx <= va05; ad_co <= b"01"; aph_sta <= x"4"; + when va05 => vme_anx <= va0b; ad_co <= b"11"; aph_sta <= x"5"; + when va0b => ad_co <= b"10"; aph_sta <= x"6"; + if asis ='1' then vme_anx <= va0b; + else vme_anx <= va00; + end if; + end case; + end process; +-- ............................ clock for address phase state machine ................................ + process(ck50) begin -- 50 MHz clock + if (ck50'EVENT AND ck50 = '1') then + vme_adr <= vme_anx; + end if; + end process ; +-- .............................. synchronize outputs .................................. + process(ck50) begin + if (ck50'EVENT AND ck50 = '1') then + stda <= ad_co(1); -- start data phase (low=address phase - high =data phase) + ckad <= ad_co(0); -- ckad = clock for internal address register + end if; + end process ; +----................... end of VME address phase state machine ................... +-- +---................... save VME address into FPGA internal address register ................... + process(ck50, ckad) + begin + if (ck50'EVENT AND ck50 = '1') then + if ckad = '1' then + ad_reg <= ad; wrs <= wri; amr <= ami; + end if; + end if; + end process; + int_res <= ad_reg(23 downto 22); -- internal resources +--.................. select SAM4 module = compare address register with hex switch ............... + +-- process(ck50)--, ad, mon) +-- begin +-- if (ck50'EVENT AND ck50 = '1') then +-- if (ad_reg(31 downto 24) = mon) then -- VN2 31...28, VN1 27...24 --*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/*/ +-- vulom_sel <= '1'; +-- else vulom_sel <= '0'; +-- end if; +-- end if; +-- end process; +--.................. compare address register and address modifier ............................. + process(ck50, ad_reg, amr) + begin + if (ck50'event and ck50 ='1') then + if ((ad_reg(1 downto 0) = b"00") and (con(7) = '1')) then --(amr = am_9 or amr = am_d) and vulom_sel = '1' then + sel_rnd <= '1'; -- CSR random access + else sel_rnd <= '0'; + end if; + if ((ad_reg(1 downto 0) = b"00") and (con(8) = '1')) then --(amr = am_b) and vulom_sel = '1' then + sel_bt32 <= '1'; -- BT 32 bit access + else sel_bt32 <= '0'; + end if; + end if; + end process; +-- * CSR0 @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ DATA PHASE for CSR @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +--................................ comparator for CSR ....................................... + process(ck50, dsr, stda, wrs, int_res, sel_rnd) + begin + if (ck50'event and ck50 ='1') then + if (dsr='1' and stda='1' and wrs='1' and int_res=csr_ad and sel_rnd='1') then st_csr_drd <= '1'; -- CSR sta-ma + else st_csr_drd <= '0'; + end if; + if (dsr='1' and stda='1' and wrs='0' and int_res=csr_ad and sel_rnd='1') then st_csr_dwr <= '1'; -- CSR sta-ma + else st_csr_dwr <= '0'; + end if; + if (int_res=csr_ad and sel_rnd='1') then selcsr <= '1'; -- CSR selected + else selcsr <= '0'; + end if; + end if; + end process; +-- csr_o[]=ckcsr,oecsr, vdcsr[]=odvi,cdvi,odiv,cdiv + process (vmdacs, dsr, st_csr_dwr, st_csr_drd) -- states are - vc00,vc01,vc02,vc03,vc04,vc05,vc06,vc07,vc08 + begin +-- csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; + case vmdacs is + when vc00 => csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"0"; + if st_csr_drd ='1' then vmdacs_nx <= vc01; + elsif st_csr_dwr ='1' then vmdacs_nx <= vc08; + else + vmdacs_nx <= vc00; + end if; +-- +--............................. read csr ................................ + when vc01 => vmdacs_nx <= vc02; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"1"; + when vc02 => vmdacs_nx <= vc03; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"2"; + when vc03 => vmdacs_nx <= vc04; csr_o <= b"01"; vdcsr <= b"1010"; ack_csr <='1'; dph_sta <= x"3"; + when vc04 => vmdacs_nx <= vc05; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"4"; + when vc05 => vmdacs_nx <= vc06; csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='1'; dph_sta <= x"5"; + when vc06 => csr_o <= b"01"; vdcsr <= b"1001"; ack_csr <='0'; dph_sta <= x"6"; + if dsr ='1' then vmdacs_nx <= vc06; + else vmdacs_nx <= vc07; + end if; + when vc07 => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"7"; +--............................. write csr ................................ + when vc08 => vmdacs_nx <= vc09; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"8"; + when vc09 => vmdacs_nx <= vc0a; csr_o <= b"10"; vdcsr <= b"0011"; ack_csr <='1'; dph_sta <= x"9"; + when vc0a => vmdacs_nx <= vc0b; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"a"; + when vc0b => vmdacs_nx <= vc0c; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"b"; + when vc0c => vmdacs_nx <= vc0d; csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='1'; dph_sta <= x"c"; + when vc0d => csr_o <= b"10"; vdcsr <= b"0111"; ack_csr <='0'; dph_sta <= x"d"; + if dsr ='1' then vmdacs_nx <= vc0d; + else vmdacs_nx <= vc0e; + end if; + when vc0e => vmdacs_nx <= vc00; csr_o <= b"00"; vdcsr <= b"1011"; ack_csr <='1'; dph_sta <= x"e"; + end case; + end process; +-- ............................ clock for vmedacs state machine ................................ + process(ck50) begin + if (ck50'EVENT AND ck50 = '1') then + vmdacs <= vmdacs_nx; + end if; + end process ; +-- .............................. synchronize outputs .................................. + process(ck50) begin + if (ck50'EVENT AND ck50 = '1') then +-- csr_o = ckcsr,oecsr, + ckcsr <= csr_o(1); -- clock data into csr + oecsr <= csr_o(0); -- output data from csr to VME + end if; + end process ; +--------------------------- VME control signals ------------------------------- +-- vdbuf = odvi,cdvi,odiv,cdiv + process(ck50,vdcsr,ack_csr,ack_hpi) + begin + if (ck50'event and ck50 ='1') then + if (selcsr='1') then + con(4) <= vdcsr(3); -- odvi = OE for data register VME->internal + con(3) <= vdcsr(2); -- cdvi = clock for data register VME->internal + con(2) <= vdcsr(1); -- odiv = OE for data register internal->VME + con(1) <= vdcsr(0); -- cdiv = clock for data register internal->VME + con(0) <= ack_csr; -- acknowledge from csr + else + con(4) <= '1'; con(3) <= '1'; con(2) <= '1'; con(1) <= '1'; con(0) <= '1'; -- inactive + end if; + end if; + end process; +---------------------------------------------------------------------------------- +-- hplb <= (others =>'0'); + hplb(0) <= asis; + hplb(1) <= ckad; + hplb(2) <= st_csr_drd; + hplb(3) <= st_csr_dwr; + hplb(6 downto 4) <= aph_sta(2 downto 0); + hplb(7) <= ack_csr; + hplb(11 downto 8) <= vdcsr; + hplb(15 downto 12) <= dph_sta; + +end RTL; \ No newline at end of file -- 2.43.0