From 72fa4b4c4b178bf23d7ddbc4d81d071322ffa823 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Sat, 17 Jan 2015 17:25:47 +0100 Subject: [PATCH] now using a Makefile for building --- nxyter/Makefile | 183 ++ nxyter/compile_munich20.pl | 155 -- nxyter/compile_munich20.sh | 12 - nxyter/compile_munich21.pl | 157 -- nxyter/compile_munich21.sh | 12 - nxyter/compile_munich32.pl | 2 +- nxyter/cores/adc_ddr_generic.ipx | 8 +- nxyter/cores/adc_ddr_generic.lpc | 23 +- nxyter/cores/adc_ddr_generic.vhd | 455 ++--- nxyter/cores/dynamic_shift_register33x64.ipx | 10 + nxyter/cores/dynamic_shift_register33x64.lpc | 44 + nxyter/cores/dynamic_shift_register33x64.vhd | 291 ++++ nxyter/cores/fifo_adc_status_4to4_dc.ipx | 9 + nxyter/cores/fifo_adc_status_4to4_dc.lpc | 50 + nxyter/cores/fifo_adc_status_4to4_dc.vhd | 482 ++++++ nxyter/cores/pll_adc_clk.ipx | 8 - nxyter/cores/pll_adc_clk.lpc | 66 - nxyter/cores/pll_adc_clk.vhd | 99 -- nxyter/nodelist.txt | 5 + nxyter/source/adc_ad9228.vhd | 524 ++++-- nxyter/source/nx_data_receiver.vhd | 80 +- nxyter/source/nxyter_components.vhd | 1483 ++++++++--------- nxyter/source/nxyter_fee_board.vhd | 24 +- nxyter/trb3_periph.p2t | 1 - nxyter/trb3_periph.p2t_single | 20 - nxyter/trb3_periph.p3t | 5 - nxyter/trb3_periph.pt | 10 - nxyter/trb3_periph.vhd | 1 - ...eriph_multi.p2t => trb3_periph_nxyter.p2t} | 0 ...trb3_periph.prj => trb3_periph_nxyter.prj} | 7 +- nxyter/trb3_periph_nxyter.vhd | 1 + ...lpf => trb3_periph_nxyter_constraints.lpf} | 43 +- ...iph_nx1.vhd => trb3_periph_nxyter_nx1.vhd} | 38 +- ...iph_nx2.vhd => trb3_periph_nxyter_nx2.vhd} | 4 +- nxyter/version-major-minor.txt | 1 + 35 files changed, 2343 insertions(+), 1970 deletions(-) create mode 100644 nxyter/Makefile delete mode 100755 nxyter/compile_munich20.pl delete mode 100755 nxyter/compile_munich20.sh delete mode 100755 nxyter/compile_munich21.pl delete mode 100755 nxyter/compile_munich21.sh create mode 100644 nxyter/cores/dynamic_shift_register33x64.ipx create mode 100644 nxyter/cores/dynamic_shift_register33x64.lpc create mode 100644 nxyter/cores/dynamic_shift_register33x64.vhd create mode 100644 nxyter/cores/fifo_adc_status_4to4_dc.ipx create mode 100644 nxyter/cores/fifo_adc_status_4to4_dc.lpc create mode 100644 nxyter/cores/fifo_adc_status_4to4_dc.vhd delete mode 100644 nxyter/cores/pll_adc_clk.ipx delete mode 100644 nxyter/cores/pll_adc_clk.lpc delete mode 100644 nxyter/cores/pll_adc_clk.vhd delete mode 120000 nxyter/trb3_periph.p2t delete mode 100644 nxyter/trb3_periph.p2t_single delete mode 100644 nxyter/trb3_periph.p3t delete mode 100644 nxyter/trb3_periph.pt delete mode 120000 nxyter/trb3_periph.vhd rename nxyter/{trb3_periph_multi.p2t => trb3_periph_nxyter.p2t} (100%) rename nxyter/{trb3_periph.prj => trb3_periph_nxyter.prj} (98%) create mode 120000 nxyter/trb3_periph_nxyter.vhd rename nxyter/{trb3_periph_constraints.lpf => trb3_periph_nxyter_constraints.lpf} (88%) rename nxyter/{trb3_periph_nx1.vhd => trb3_periph_nxyter_nx1.vhd} (96%) rename nxyter/{trb3_periph_nx2.vhd => trb3_periph_nxyter_nx2.vhd} (99%) create mode 100644 nxyter/version-major-minor.txt diff --git a/nxyter/Makefile b/nxyter/Makefile new file mode 100644 index 0000000..7b0f18d --- /dev/null +++ b/nxyter/Makefile @@ -0,0 +1,183 @@ +TARGET=trb3_periph_nxyter +FAMILYNAME=LatticeECP3 +DEVICENAME=LFE3-150EA +PACKAGE=FPBGA672 +SPEEDGRADE=8 + +TIMESTAMP=$(shell date '+%s') +VERSION=$(shell cat version-major-minor.txt) + +# ------------------------------------------------------------------------------------ + +.PHONY: all +all: workdir/$(TARGET).bit + +.PHONY: clean +clean: + rm -rf workdir/* + +.PHONY: checkenv +checkenv: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- Check Lattice Environment ---------------" + @echo "----------------------------------------------------------------------" + @if [ -n "${LM_LICENSE_FILE}" ] ; then \ + echo "Lattice Environment is: ${LM_LICENSE_FILE}"; \ + else \ + echo "------> Lattice Environment is not set"; \ + exit 1; \ + fi + +# ------------------------------------------------------------------------------------ + +# Bitgen +workdir/$(TARGET).bit: workdir/$(TARGET).ncd + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Bitgen ------------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $(TARGET).ncd \ + $(TARGET).bit $(TARGET).prf + $(MAKE) report + $(MAKE) error + +# Place and Route (multipar) +workdir/$(TARGET).ncd: workdir/$(TARGET)_map.ncd + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Place and Route (multipar)-----------------------------" + @echo "----------------------------------------------------------------------" + rm -rf workdir/$(TARGET).ncd workdir/$(TARGET).dir + cd workdir && \ + par -f ../$(TARGET).p2t $(TARGET)_map.ncd $(TARGET).dir $(TARGET).prf + cp workdir/$(TARGET).dir/*.ncd workdir/$(TARGET).ncd + +# Mapper +workdir/$(TARGET)_map.ncd: workdir/$(TARGET).ngd $(TARGET).lpf + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Mapper ------------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + map -retime -split_node -a $(FAMILYNAME) -p $(DEVICENAME) \ + -t $(PACKAGE) -s $(SPEEDGRADE) $(TARGET).ngd -pr $(TARGET).prf \ + -o $(TARGET)_map.ncd -mp $(TARGET).mrp $(TARGET).lpf + +# EDIF 2 NGD +workdir/$(TARGET).ngd: workdir/$(TARGET).edf + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- EDIF 2 NGD---------------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + edif2ngd -l $(FAMILYNAME) -d $(DEVICENAME) \$(TARGET).edf $(TARGET).ngo + cd workdir && \ + edfupdate -t $(TARGET).tcy -w $(TARGET).ngo -m $(TARGET).ngo \ + $(TARGET).ngx + cd workdir && \ + ngdbuild -a $(FAMILYNAME) -d $(DEVICENAME) -dt $(TARGET).ngo \ + $(TARGET).ngd + +# VHDL / Verilog Compiler +workdir/$(TARGET).edf: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- VHDL Compiler ----------------------------------------" + @echo "----------------------------------------------------------------------" + $(MAKE) workdir + $(MAKE) version + $(MAKE) checkenv + synpwrap -prj $(TARGET).prj || \ + (grep "@E" workdir/$(TARGET).srr && exit 2) + +# ------------------------------------------------------------------------------------ + +# Version File +.PHONY: version +version: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "--------------- Version File -----------------------------------------" + @echo "----------------------------------------------------------------------" + @echo "-- attention, automatically generated. Don't change by hand." > version.vhd + @echo "library ieee;" >> version.vhd + @echo "USE IEEE.std_logic_1164.ALL;" >> version.vhd + @echo "USE IEEE.std_logic_ARITH.ALL;" >> version.vhd + @echo "USE IEEE.std_logic_UNSIGNED.ALL;" >> version.vhd + @echo "use ieee.numeric_std.all;" >> version.vhd + @echo "" >> version.vhd + @echo "package version is" >> version.vhd + @echo "" >> version.vhd + @echo " constant VERSION_NUMBER_TIME : integer := $(TIMESTAMP);" >> version.vhd + @echo -n " constant VERSION_NUMBER : integer := " >> version.vhd + @echo "to_integer(x\"$(VERSION)\");" >> version.vhd + @echo "" >> version.vhd + @echo "end package version;" >> version.vhd + @cat version.vhd + +# Setup Workdir +.PHONY: workdir +workdir: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Setup Workdir -----------------------------------------" + @echo "----------------------------------------------------------------------" + mkdir -p workdir + cd workdir && ../../base/linkdesignfiles.sh + cp $(TARGET).lpf workdir/$(TARGET).lpf + cat $(TARGET)_constraints.lpf >> workdir/$(TARGET).lpf + cp nodelist.txt workdir/ + +# Timing Report +.PHONY: report +report: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Timing Report -----------------------------------------" + @echo "----------------------------------------------------------------------" + cd workdir && \ + iotiming -s $(TARGET).ncd $(TARGET).prf + cd workdir && \ + trce -c -v 15 -o $(TARGET).twr.setup $(TARGET).ncd $(TARGET).prf + cd workdir && \ + trce -hld -c -v 5 -o $(TARGET).twr.hold $(TARGET).ncd $(TARGET).prf + cd workdir && \ + ltxt2ptxt $(TARGET).ncd + +# Error Check +.PHONY: error +error: + @echo "" + @echo "----------------------------------------------------------------------" + @echo "-------------- Error Check -----------------------------------------" + @echo "----------------------------------------------------------------------" + @echo -e "\n$(TARGET).mrp:" + @grep "Semantic error" ./workdir/$(TARGET).mrp || exit 0 + + @echo -e "\n$(TARGET).twr.setup:" + @grep 'Error: The following path exceeds requirements by' ./workdir/$(TARGET).twr.setup \ + || exit 0 + + @echo -e "\n$(TARGET).twr.hold:" + @grep "Error:" ./workdir/$(TARGET).twr.hold || exit 0 + + @echo -e "\nCircuit Loops:" + @grep "potential circuit loops" ./workdir/* || exit 0 + +# ------------------------------------------------------------------------------------ +# Extract dependencies from project file +#.PHONY: $(TARGET).dep +#$(TARGET).dep: +# @echo "" +# @echo "----------------------------------------------------------------------" +# @echo "--------------- Extract Dependencies from Project File ---------------" +# @echo "----------------------------------------------------------------------" +# grep 'add_file' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ +# | xargs echo "workdir/$(TARGET).edf:" > $(TARGET).dep +# grep 'map_dep' $(TARGET).prj | grep -v '#' | sed -r 's/^.*"(.*)"$$/\1/' \ +# | xargs echo "workdir/$(TARGET)_map.ncd:" >> $(TARGET).dep +# +#-include $(TARGET).dep + diff --git a/nxyter/compile_munich20.pl b/nxyter/compile_munich20.pl deleted file mode 100755 index 1a9415f..0000000 --- a/nxyter/compile_munich20.pl +++ /dev/null @@ -1,155 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.0'; -my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ./$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - - -$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/nxyter/compile_munich20.sh b/nxyter/compile_munich20.sh deleted file mode 100755 index 7994aa3..0000000 --- a/nxyter/compile_munich20.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -. /usr/local/opt/lattice_diamond/diamond/2.0/bin/lin/diamond_env - -exec ./compile_munich20.pl - -grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup -grep 'Error:' ./workdir/trb3_periph.twr.hold -grep 'potential circuit loops' ./workdir/* - -echo "Script DONE!" - diff --git a/nxyter/compile_munich21.pl b/nxyter/compile_munich21.pl deleted file mode 100755 index 5290d32..0000000 --- a/nxyter/compile_munich21.pl +++ /dev/null @@ -1,157 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; -my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ./$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); -system("rm $TOPNAME.dir/*"); - -$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; -execute($c); - -system("cp -a ${TOPNAME}.dir/*.ncd ./${TOPNAME}.ncd"); - -# IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/nxyter/compile_munich21.sh b/nxyter/compile_munich21.sh deleted file mode 100755 index 99940f1..0000000 --- a/nxyter/compile_munich21.sh +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -. /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env - -./compile_munich21.pl - -#grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup" -grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup -grep 'Error:' ./workdir/trb3_periph.twr.hold -grep 'potential circuit loops' ./workdir/* - -echo "Script DONE!" diff --git a/nxyter/compile_munich32.pl b/nxyter/compile_munich32.pl index 9f7ae7e..08dc214 100755 --- a/nxyter/compile_munich32.pl +++ b/nxyter/compile_munich32.pl @@ -20,7 +20,7 @@ use FileHandle; $ENV{'SYNPLIFY'}=$synplify_path; $ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; +#$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="LatticeECP3"; my $DEVICENAME="LFE3-150EA"; diff --git a/nxyter/cores/adc_ddr_generic.ipx b/nxyter/cores/adc_ddr_generic.ipx index ed5d317..12b7d6e 100644 --- a/nxyter/cores/adc_ddr_generic.ipx +++ b/nxyter/cores/adc_ddr_generic.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/nxyter/cores/adc_ddr_generic.lpc b/nxyter/cores/adc_ddr_generic.lpc index 08beafb..98dd658 100644 --- a/nxyter/cores/adc_ddr_generic.lpc +++ b/nxyter/cores/adc_ddr_generic.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=DDR_GENERIC -CoreRevision=5.3 +CoreRevision=5.6 ModuleName=adc_ddr_generic SourceFormat=VHDL ParameterFileVersion=1.0 -Date=05/01/2014 -Time=16:42:34 +Date=10/16/2014 +Time=12:18:36 [Parameters] Verilog=0 @@ -30,7 +30,7 @@ IO=0 mode=Receive trioddr=0 io_type=LVDS25 -num_int=2 +num_int=1 width=5 freq_in=187.5 bandwidth=1875.0 @@ -42,13 +42,13 @@ io_type2=LVDS25 freq_in2=187.5 gear=2x aligned2=Centered -num_int2=2 +num_int2=1 width2=5 -Interface=GDDRX2_RX.DQS.Centered -Delay=Bypass -Number=2 -dqs1=5 -dqs2=5 +Interface=GDDRX2_RX.ECLK.Centered +Delay=Fixed +Number= +dqs1= +dqs2= dqs3= dqs4= dqs5= @@ -60,3 +60,6 @@ Phase=TRDLLB/DLLDELB Divider=CLKDIVB Multiplier=2 PllFreq=94 + +[Command] +cmd_line= -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk eclk diff --git a/nxyter/cores/adc_ddr_generic.vhd b/nxyter/cores/adc_ddr_generic.vhd index 67fe282..1fad2a1 100644 --- a/nxyter/cores/adc_ddr_generic.vhd +++ b/nxyter/cores/adc_ddr_generic.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.6 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk eclk --- Thu May 1 16:42:34 2014 +-- Thu Oct 16 12:18:37 2014 library IEEE; use IEEE.std_logic_1164.all; @@ -13,17 +13,12 @@ use ecp3.components.all; entity adc_ddr_generic is port ( - clk_0: in std_logic; - clk_1: in std_logic; + clk: in std_logic; clkdiv_reset: in std_logic; - eclk: in std_logic; - reset_0: in std_logic; - reset_1: in std_logic; + eclk: out std_logic; sclk: out std_logic; - datain_0: in std_logic_vector(4 downto 0); - datain_1: in std_logic_vector(4 downto 0); - q_0: out std_logic_vector(19 downto 0); - q_1: out std_logic_vector(19 downto 0)); + datain: in std_logic_vector(4 downto 0); + q: out std_logic_vector(19 downto 0)); attribute dont_touch : boolean; attribute dont_touch of adc_ddr_generic : entity is true; end adc_ddr_generic; @@ -31,114 +26,48 @@ end adc_ddr_generic; architecture Structure of adc_ddr_generic is -- internal signal declarations - signal datain_1i_t4: std_logic; - signal datain_1i_t3: std_logic; - signal datain_1i_t2: std_logic; - signal datain_1i_t1: std_logic; - signal datain_1i_t0: std_logic; - signal buf_datain_1i4: std_logic; - signal buf_datain_1i3: std_logic; - signal buf_datain_1i2: std_logic; - signal buf_datain_1i1: std_logic; - signal buf_datain_1i0: std_logic; - signal datain_0i_t4: std_logic; - signal datain_0i_t3: std_logic; - signal datain_0i_t2: std_logic; - signal datain_0i_t1: std_logic; - signal datain_0i_t0: std_logic; - signal buf_datain_0i4: std_logic; - signal buf_datain_0i3: std_logic; - signal buf_datain_0i2: std_logic; - signal buf_datain_0i1: std_logic; - signal buf_datain_0i0: std_logic; - signal qb19: std_logic; - signal qa19: std_logic; - signal qb09: std_logic; - signal qa09: std_logic; - signal datain_t9: std_logic; - signal qb18: std_logic; - signal qa18: std_logic; - signal qb08: std_logic; - signal qa08: std_logic; - signal datain_t8: std_logic; - signal qb17: std_logic; - signal qa17: std_logic; - signal qb07: std_logic; - signal qa07: std_logic; - signal datain_t7: std_logic; - signal qb16: std_logic; - signal qa16: std_logic; - signal qb06: std_logic; - signal qa06: std_logic; - signal datain_t6: std_logic; - signal qb15: std_logic; - signal qa15: std_logic; - signal qb05: std_logic; - signal qa05: std_logic; - signal datain_t5: std_logic; signal qb14: std_logic; signal qa14: std_logic; signal qb04: std_logic; signal qa04: std_logic; - signal datain_t4: std_logic; signal qb13: std_logic; signal qa13: std_logic; signal qb03: std_logic; signal qa03: std_logic; - signal datain_t3: std_logic; signal qb12: std_logic; signal qa12: std_logic; signal qb02: std_logic; signal qa02: std_logic; - signal datain_t2: std_logic; signal qb11: std_logic; signal qa11: std_logic; signal qb01: std_logic; signal qa01: std_logic; - signal datain_t1: std_logic; signal qb10: std_logic; signal qa10: std_logic; signal qb00: std_logic; signal qa00: std_logic; - signal datain_t0: std_logic; - signal dqclk11: std_logic; - signal dqclk01: std_logic; - signal eclkdqsr1: std_logic; - signal ddrlat1: std_logic; - signal datavalid1: std_logic; - signal prmbdet1: std_logic; - signal ddrclkpol1: std_logic; - signal dqsw1: std_logic; - signal dqclk10: std_logic; - signal dqclk00: std_logic; - signal eclkdqsr0: std_logic; - signal ddrlat0: std_logic; - signal datavalid0: std_logic; - signal prmbdet0: std_logic; - signal ddrclkpol0: std_logic; - signal dqsw0: std_logic; - signal scuba_vlo: std_logic; - signal dqsdel: std_logic; - signal dqsdll_lock: std_logic; - signal dqsdll_uddcntln: std_logic; - signal dqsdll_reset: std_logic; - signal clkos: std_logic; signal cdiv8: std_logic; signal cdiv4: std_logic; signal cdiv1: std_logic; signal scuba_vhi: std_logic; - signal clkok: std_logic; - signal buf_clk_1: std_logic; - signal buf_clk_0: std_logic; + signal eclk_t: std_logic; + signal dataini_t4: std_logic; + signal dataini_t3: std_logic; + signal dataini_t2: std_logic; + signal dataini_t1: std_logic; + signal dataini_t0: std_logic; + signal buf_clk: std_logic; + signal buf_dataini4: std_logic; + signal buf_dataini3: std_logic; + signal buf_dataini2: std_logic; + signal buf_dataini1: std_logic; + signal buf_dataini0: std_logic; signal sclk_t: std_logic; -- local component declarations component VHI port (Z: out std_logic); end component; - component VLO - port (Z: out std_logic); - end component; component IB port (I: in std_logic; O: out std_logic); end component; @@ -148,61 +77,26 @@ architecture Structure of adc_ddr_generic is CDIV2: out std_logic; CDIV4: out std_logic; CDIV8: out std_logic); end component; - component IDDRX2D - generic (DELAYMODE : in String; SCLKLATENCY : in Integer); + component IDDRX2D1 + generic (DR_CONFIG : in String); port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic; - ECLKDQSR: in std_logic; DDRLAT: in std_logic; - DDRCLKPOL: in std_logic; QA0: out std_logic; - QB0: out std_logic; QA1: out std_logic; - QB1: out std_logic); - end component; - component DQSBUFD - generic (NRZMODE : in String; DYNDEL_CNTL : in String; - DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String); - port (DQSI: in std_logic; SCLK: in std_logic; - READ: in std_logic; DQSDEL: in std_logic; - ECLK: in std_logic; ECLKW: in std_logic; - RST: in std_logic; DYNDELPOL: in std_logic; - DYNDELAY6: in std_logic; DYNDELAY5: in std_logic; - DYNDELAY4: in std_logic; DYNDELAY3: in std_logic; - DYNDELAY2: in std_logic; DYNDELAY1: in std_logic; - DYNDELAY0: in std_logic; DQSW: out std_logic; - DDRCLKPOL: out std_logic; PRMBDET: out std_logic; - DATAVALID: out std_logic; DDRLAT: out std_logic; - ECLKDQSR: out std_logic; DQCLK0: out std_logic; - DQCLK1: out std_logic); - end component; - component DQSDLLB - generic (LOCK_SENSITIVITY : in String); - port (CLK: in std_logic; RST: in std_logic; - UDDCNTLN: in std_logic; LOCK: out std_logic; - DQSDEL: out std_logic); + QA0: out std_logic; QB0: out std_logic; + QA1: out std_logic; QB1: out std_logic); end component; component DELAYC port (A: in std_logic; Z: out std_logic); end component; attribute IDDRAPPS : string; attribute IO_TYPE : string; - attribute IO_TYPE of Inst6_IB4 : label is "LVDS25"; - attribute IO_TYPE of Inst6_IB3 : label is "LVDS25"; - attribute IO_TYPE of Inst6_IB2 : label is "LVDS25"; - attribute IO_TYPE of Inst6_IB1 : label is "LVDS25"; - attribute IO_TYPE of Inst6_IB0 : label is "LVDS25"; - attribute IO_TYPE of Inst5_IB4 : label is "LVDS25"; - attribute IO_TYPE of Inst5_IB3 : label is "LVDS25"; - attribute IO_TYPE of Inst5_IB2 : label is "LVDS25"; - attribute IO_TYPE of Inst5_IB1 : label is "LVDS25"; - attribute IO_TYPE of Inst5_IB0 : label is "LVDS25"; - attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED"; - attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_4 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_3 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_2 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_1 : label is "ECLK_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D1_0_0 : label is "ECLK_CENTERED"; + attribute IO_TYPE of Inst2_IB : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB2 : label is "LVDS25"; attribute IO_TYPE of Inst1_IB1 : label is "LVDS25"; attribute IO_TYPE of Inst1_IB0 : label is "LVDS25"; attribute syn_keep : boolean; @@ -213,227 +107,93 @@ architecture Structure of adc_ddr_generic is begin -- component instantiation statements - udel_datain_1i4: DELAYC - port map (A=>buf_datain_1i4, Z=>datain_1i_t4); - - udel_datain_1i3: DELAYC - port map (A=>buf_datain_1i3, Z=>datain_1i_t3); - - udel_datain_1i2: DELAYC - port map (A=>buf_datain_1i2, Z=>datain_1i_t2); - - udel_datain_1i1: DELAYC - port map (A=>buf_datain_1i1, Z=>datain_1i_t1); - - udel_datain_1i0: DELAYC - port map (A=>buf_datain_1i0, Z=>datain_1i_t0); - - Inst6_IB4: IB - port map (I=>datain_1(4), O=>buf_datain_1i4); - - Inst6_IB3: IB - port map (I=>datain_1(3), O=>buf_datain_1i3); - - Inst6_IB2: IB - port map (I=>datain_1(2), O=>buf_datain_1i2); - - Inst6_IB1: IB - port map (I=>datain_1(1), O=>buf_datain_1i1); - - Inst6_IB0: IB - port map (I=>datain_1(0), O=>buf_datain_1i0); - - udel_datain_0i4: DELAYC - port map (A=>buf_datain_0i4, Z=>datain_0i_t4); - - udel_datain_0i3: DELAYC - port map (A=>buf_datain_0i3, Z=>datain_0i_t3); - - udel_datain_0i2: DELAYC - port map (A=>buf_datain_0i2, Z=>datain_0i_t2); - - udel_datain_0i1: DELAYC - port map (A=>buf_datain_0i1, Z=>datain_0i_t1); + Inst_IDDRX2D1_0_4: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t4, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa04, + QB0=>qb04, QA1=>qa14, QB1=>qb14); + + Inst_IDDRX2D1_0_3: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t3, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa03, + QB0=>qb03, QA1=>qa13, QB1=>qb13); + + Inst_IDDRX2D1_0_2: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t2, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa02, + QB0=>qb02, QA1=>qa12, QB1=>qb12); + + Inst_IDDRX2D1_0_1: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t1, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa01, + QB0=>qb01, QA1=>qa11, QB1=>qb11); + + Inst_IDDRX2D1_0_0: IDDRX2D1 + generic map (DR_CONFIG=> "DISABLED") + port map (D=>dataini_t0, SCLK=>sclk_t, ECLK=>eclk_t, QA0=>qa00, + QB0=>qb00, QA1=>qa10, QB1=>qb10); - udel_datain_0i0: DELAYC - port map (A=>buf_datain_0i0, Z=>datain_0i_t0); - - Inst5_IB4: IB - port map (I=>datain_0(4), O=>buf_datain_0i4); - - Inst5_IB3: IB - port map (I=>datain_0(3), O=>buf_datain_0i3); - - Inst5_IB2: IB - port map (I=>datain_0(2), O=>buf_datain_0i2); - - Inst5_IB1: IB - port map (I=>datain_0(1), O=>buf_datain_0i1); - - Inst5_IB0: IB - port map (I=>datain_0(0), O=>buf_datain_0i0); - - Inst_IDDRX2D_1_4: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, - QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19); - - Inst_IDDRX2D_1_3: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, - QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18); - - Inst_IDDRX2D_1_2: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, - QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17); - - Inst_IDDRX2D_1_1: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, - QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16); - - Inst_IDDRX2D_1_0: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, - QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15); - - Inst_IDDRX2D_0_4: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, - QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14); + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); - Inst_IDDRX2D_0_3: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, - QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13); + Inst3_CLKDIVB: CLKDIVB + port map (CLKI=>eclk_t, RST=>clkdiv_reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>sclk_t, CDIV4=>cdiv4, CDIV8=>cdiv8); - Inst_IDDRX2D_0_2: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, - QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12); + udel_dataini4: DELAYC + port map (A=>buf_dataini4, Z=>dataini_t4); - Inst_IDDRX2D_0_1: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, - QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11); + udel_dataini3: DELAYC + port map (A=>buf_dataini3, Z=>dataini_t3); - Inst_IDDRX2D_0_0: IDDRX2D - generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) - port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, - ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, - QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10); + udel_dataini2: DELAYC + port map (A=>buf_dataini2, Z=>dataini_t2); - Inst4_DQSBUFD1: DQSBUFD - generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", - DYNDEL_TYPE=> "NORMAL") - port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, - DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, - DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, - DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, - DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, - DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, - DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, - DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, - DQCLK0=>dqclk01, DQCLK1=>dqclk11); + udel_dataini1: DELAYC + port map (A=>buf_dataini1, Z=>dataini_t1); - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); + udel_dataini0: DELAYC + port map (A=>buf_dataini0, Z=>dataini_t0); - Inst4_DQSBUFD0: DQSBUFD - generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", - DYNDEL_TYPE=> "NORMAL") - port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, - DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, - DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, - DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, - DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, - DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, - DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, - DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, - DQCLK0=>dqclk00, DQCLK1=>dqclk10); + Inst2_IB: IB + port map (I=>clk, O=>buf_clk); - Inst3_DQSDLLB: DQSDLLB - generic map (LOCK_SENSITIVITY=> "LOW") - port map (CLK=>clkos, RST=>dqsdll_reset, - UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel); + Inst1_IB4: IB + port map (I=>datain(4), O=>buf_dataini4); - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); + Inst1_IB3: IB + port map (I=>datain(3), O=>buf_dataini3); - Inst2_CLKDIVB: CLKDIVB - port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, - CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8); + Inst1_IB2: IB + port map (I=>datain(2), O=>buf_dataini2); Inst1_IB1: IB - port map (I=>clk_1, O=>buf_clk_1); + port map (I=>datain(1), O=>buf_dataini1); Inst1_IB0: IB - port map (I=>clk_0, O=>buf_clk_0); - - q_1(19) <= qb19; - q_1(18) <= qb18; - q_1(17) <= qb17; - q_1(16) <= qb16; - q_1(15) <= qb15; - q_1(14) <= qa19; - q_1(13) <= qa18; - q_1(12) <= qa17; - q_1(11) <= qa16; - q_1(10) <= qa15; - q_1(9) <= qb09; - q_1(8) <= qb08; - q_1(7) <= qb07; - q_1(6) <= qb06; - q_1(5) <= qb05; - q_1(4) <= qa09; - q_1(3) <= qa08; - q_1(2) <= qa07; - q_1(1) <= qa06; - q_1(0) <= qa05; - datain_t9 <= datain_1i_t4; - datain_t8 <= datain_1i_t3; - datain_t7 <= datain_1i_t2; - datain_t6 <= datain_1i_t1; - datain_t5 <= datain_1i_t0; - q_0(19) <= qb14; - q_0(18) <= qb13; - q_0(17) <= qb12; - q_0(16) <= qb11; - q_0(15) <= qb10; - q_0(14) <= qa14; - q_0(13) <= qa13; - q_0(12) <= qa12; - q_0(11) <= qa11; - q_0(10) <= qa10; - q_0(9) <= qb04; - q_0(8) <= qb03; - q_0(7) <= qb02; - q_0(6) <= qb01; - q_0(5) <= qb00; - q_0(4) <= qa04; - q_0(3) <= qa03; - q_0(2) <= qa02; - q_0(1) <= qa01; - q_0(0) <= qa00; - datain_t4 <= datain_0i_t4; - datain_t3 <= datain_0i_t3; - datain_t2 <= datain_0i_t2; - datain_t1 <= datain_0i_t1; - datain_t0 <= datain_0i_t0; - dqsdll_uddcntln <= scuba_vhi; - dqsdll_reset <= scuba_vhi; - clkos <= eclk; - sclk_t <= clkok; + port map (I=>datain(0), O=>buf_dataini0); + + eclk <= eclk_t; + q(19) <= qb14; + q(18) <= qb13; + q(17) <= qb12; + q(16) <= qb11; + q(15) <= qb10; + q(14) <= qa14; + q(13) <= qa13; + q(12) <= qa12; + q(11) <= qa11; + q(10) <= qa10; + q(9) <= qb04; + q(8) <= qb03; + q(7) <= qb02; + q(6) <= qb01; + q(5) <= qb00; + q(4) <= qa04; + q(3) <= qa03; + q(2) <= qa02; + q(1) <= qa01; + q(0) <= qa00; + eclk_t <= buf_clk; sclk <= sclk_t; end Structure; @@ -442,12 +202,9 @@ library ecp3; configuration Structure_CON of adc_ddr_generic is for Structure for all:VHI use entity ecp3.VHI(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; for all:IB use entity ecp3.IB(V); end for; for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; - for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for; - for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for; - for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for; + for all:IDDRX2D1 use entity ecp3.IDDRX2D1(V); end for; for all:DELAYC use entity ecp3.DELAYC(V); end for; end for; end Structure_CON; diff --git a/nxyter/cores/dynamic_shift_register33x64.ipx b/nxyter/cores/dynamic_shift_register33x64.ipx new file mode 100644 index 0000000..ed7fb9a --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/nxyter/cores/dynamic_shift_register33x64.lpc b/nxyter/cores/dynamic_shift_register33x64.lpc new file mode 100644 index 0000000..9edcd22 --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_Based_Shift_Register +CoreRevision=5.1 +ModuleName=dynamic_shift_register33x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/09/2014 +Time=14:16:23 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +DataWidth=33 +Type=VarLossless +NoOfShifts=16 +MaxLossyShifts=16 +MaxLosslessShifts=64 +EOR=1 +MemFile= +MemFormat=orca +RamType=bram + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output diff --git a/nxyter/cores/dynamic_shift_register33x64.vhd b/nxyter/cores/dynamic_shift_register33x64.vhd new file mode 100644 index 0000000..911426a --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.vhd @@ -0,0 +1,291 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.1 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output + +-- Sat Aug 9 14:16:23 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dynamic_shift_register33x64 is + port ( + Din: in std_logic_vector(32 downto 0); + Addr: in std_logic_vector(5 downto 0); + Clock: in std_logic; + ClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(32 downto 0)); +end dynamic_shift_register33x64; + +architecture Structure of dynamic_shift_register33x64 is + + -- internal signal declarations + signal Reset_inv: std_logic; + signal ishreg_addr_w0: std_logic; + signal ishreg_addr_w1: std_logic; + signal sreg_0_ctr_1_ci: std_logic; + signal ishreg_addr_w2: std_logic; + signal ishreg_addr_w3: std_logic; + signal co0: std_logic; + signal ishreg_addr_w4: std_logic; + signal ishreg_addr_w5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal shreg_addr_r0: std_logic; + signal precin: std_logic; + signal high_inv: std_logic; + signal scuba_vhi: std_logic; + signal shreg_addr_w0: std_logic; + signal shreg_addr_r1: std_logic; + signal shreg_addr_r2: std_logic; + signal co0_1: std_logic; + signal shreg_addr_w1: std_logic; + signal shreg_addr_w2: std_logic; + signal shreg_addr_r3: std_logic; + signal shreg_addr_r4: std_logic; + signal co1_1: std_logic; + signal shreg_addr_w3: std_logic; + signal shreg_addr_w4: std_logic; + signal shreg_addr_r5: std_logic; + signal co2_1: std_logic; + signal shreg_addr_w5: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of sram_1_0_0_0 : label is "dynamic_shift_register33x64.lpc"; + attribute MEM_INIT_FILE of sram_1_0_0_0 : label is ""; + attribute RESETMODE of sram_1_0_0_0 : label is "SYNC"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_1: INV + port map (A=>Reset, Z=>Reset_inv); + + INV_0: INV + port map (A=>scuba_vhi, Z=>high_inv); + + sram_1_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + DI4=>Din(4), DI5=>Din(5), DI6=>Din(6), DI7=>Din(7), + DI8=>Din(8), DI9=>Din(9), DI10=>Din(10), DI11=>Din(11), + DI12=>Din(12), DI13=>Din(13), DI14=>Din(14), DI15=>Din(15), + DI16=>Din(16), DI17=>Din(17), DI18=>Din(18), DI19=>Din(19), + DI20=>Din(20), DI21=>Din(21), DI22=>Din(22), DI23=>Din(23), + DI24=>Din(24), DI25=>Din(25), DI26=>Din(26), DI27=>Din(27), + DI28=>Din(28), DI29=>Din(29), DI30=>Din(30), DI31=>Din(31), + DI32=>Din(32), DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>shreg_addr_w0, ADW1=>shreg_addr_w1, + ADW2=>shreg_addr_w2, ADW3=>shreg_addr_w3, + ADW4=>shreg_addr_w4, ADW5=>shreg_addr_w5, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>ClockEn, + CLKW=>Clock, CSW0=>Reset_inv, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>shreg_addr_r0, ADR6=>shreg_addr_r1, + ADR7=>shreg_addr_r2, ADR8=>shreg_addr_r3, + ADR9=>shreg_addr_r4, ADR10=>shreg_addr_r5, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>ClockEn, + CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>open, + DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_5: FD1P3DX + port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w0); + + FF_4: FD1P3DX + port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w1); + + FF_3: FD1P3DX + port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w2); + + FF_2: FD1P3DX + port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w3); + + FF_1: FD1P3DX + port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w4); + + FF_0: FD1P3DX + port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w5); + + sreg_0_ctr_1_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, + S0=>open, S1=>open); + + sreg_0_ctr_1_0: CU2 + port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, + PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, + NC1=>ishreg_addr_w1); + + sreg_0_ctr_1_1: CU2 + port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, + CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); + + sreg_0_ctr_1_2: CU2 + port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, + CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); + + precin_inst101: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + raddr_sub_1_0: FSUB2B + port map (A0=>scuba_vhi, A1=>shreg_addr_w0, B0=>high_inv, + B1=>Addr(0), BI=>precin, BOUT=>co0_1, S0=>open, + S1=>shreg_addr_r0); + + raddr_sub_1_1: FSUB2B + port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), + B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, + S1=>shreg_addr_r2); + + raddr_sub_1_2: FSUB2B + port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), + B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, + S1=>shreg_addr_r4); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + raddr_sub_1_3: FSUB2B + port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5), + B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5, + S1=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dynamic_shift_register33x64 is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/fifo_adc_status_4to4_dc.ipx b/nxyter/cores/fifo_adc_status_4to4_dc.ipx new file mode 100644 index 0000000..696acd9 --- /dev/null +++ b/nxyter/cores/fifo_adc_status_4to4_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_adc_status_4to4_dc.lpc b/nxyter/cores/fifo_adc_status_4to4_dc.lpc new file mode 100644 index 0000000..e0e24ef --- /dev/null +++ b/nxyter/cores/fifo_adc_status_4to4_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_adc_status_4to4_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/25/2014 +Time=02:08:24 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=2 +Width=4 +RDepth=2 +RWidth=4 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_adc_status_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 1 -data_width 4 -num_words 2 -rdata_width 4 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/nxyter/cores/fifo_adc_status_4to4_dc.vhd b/nxyter/cores/fifo_adc_status_4to4_dc.vhd new file mode 100644 index 0000000..039d808 --- /dev/null +++ b/nxyter/cores/fifo_adc_status_4to4_dc.vhd @@ -0,0 +1,482 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n fifo_adc_status_4to4_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2 -width 4 -depth 2 -rdata_width 4 -regout -no_enable -pe -1 -pf -1 + +-- Mon Aug 25 02:08:25 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_adc_status_4to4_dc is + port ( + Data: in std_logic_vector(3 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(3 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_adc_status_4to4_dc; + +architecture Structure of fifo_adc_status_4to4_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal r_gdata_0: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal co0: std_logic; + signal w_gctr_ci: std_logic; + signal wcount_1: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal co0_1: std_logic; + signal r_gctr_ci: std_logic; + signal rcount_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal empty_cmp_clr: std_logic; + signal rcount_0: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal full_cmp_clr: std_logic; + signal wcount_0: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KC + generic (GSR : in String; WRITEMODE_B : in String; + WRITEMODE_A : in String; CSDECODE_B : in String; + CSDECODE_A : in String; REGMODE_B : in String; + REGMODE_A : in String; DATA_WIDTH_B : in Integer; + DATA_WIDTH_A : in Integer); + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; + WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; + WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_adc_status_4to4_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t2: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t1: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_1, AD2=>rcount_1, AD1=>w_gcount_r21, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_1, AD2=>wcount_1, AD1=>r_gcount_w21, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 4, + DATA_WIDTH_A=> 4) + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, + ADA3=>scuba_vlo, ADA4=>scuba_vlo, ADA5=>scuba_vlo, + ADA6=>scuba_vlo, ADA7=>scuba_vlo, ADA8=>scuba_vlo, + ADA9=>scuba_vlo, ADA10=>scuba_vlo, ADA11=>scuba_vlo, + ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>wren_i, + CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>rptr_0, + ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>scuba_vlo, + ADB6=>scuba_vlo, ADB7=>scuba_vlo, ADB8=>scuba_vlo, + ADB9=>scuba_vlo, ADB10=>scuba_vlo, ADB11=>scuba_vlo, + ADB12=>scuba_vlo, ADB13=>scuba_vlo, CEB=>rden_i, + CLKB=>RdClock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), + DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open, DOB8=>open, + DOB9=>open, DOB10=>open, DOB11=>open, DOB12=>open, + DOB13=>open, DOB14=>open, DOB15=>open, DOB16=>open, + DOB17=>open); + + FF_21: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_20: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_19: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_18: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_17: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_16: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_15: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_14: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_13: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_12: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_11: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_10: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_9: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_8: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_7: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_6: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_5: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_4: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_3: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_2: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>empty_cmp_set, B0=>wcount_r0, + B1=>empty_cmp_clr, CI=>cmp_ci, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>full_cmp_set, B0=>rcount_w0, + B1=>full_cmp_clr, CI=>cmp_ci_1, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_adc_status_4to4_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:DP16KC use entity ecp3.DP16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/pll_adc_clk.ipx b/nxyter/cores/pll_adc_clk.ipx deleted file mode 100644 index 46f3f23..0000000 --- a/nxyter/cores/pll_adc_clk.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/nxyter/cores/pll_adc_clk.lpc b/nxyter/cores/pll_adc_clk.lpc deleted file mode 100644 index 916c5ed..0000000 --- a/nxyter/cores/pll_adc_clk.lpc +++ /dev/null @@ -1,66 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PLL -CoreRevision=5.3 -ModuleName=pll_adc_clk -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/07/2014 -Time=15:14:44 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=None -Order=None -IO=0 -Type=ehxpllb -mode=normal -IFrq=200 -Div=16 -ClkOPBp=0 -Post=4 -U_OFrq=187.5 -OP_Tol=0.0 -OFrq=187.500000 -DutyTrimP=Rising -DelayMultP=0 -fb_mode=CLKOP -Mult=15 -Phase=0.0 -Duty=8 -DelayMultS=0 -DPD=50% Duty -DutyTrimS=Rising -DelayMultD=0 -ClkOSDelay=0 -PhaseDuty=Static -CLKOK_INPUT=CLKOP -SecD=2 -U_KFrq=50 -OK_Tol=0.0 -KFrq= -ClkRst=0 -PCDR=1 -FINDELA=0 -VcoRate= -Bandwidth=1.826303 -;DelayControl=No -EnCLKOS=0 -ClkOSBp=0 -EnCLKOK=0 -ClkOKBp=0 -enClkOK2=0 diff --git a/nxyter/cores/pll_adc_clk.vhd b/nxyter/cores/pll_adc_clk.vhd deleted file mode 100644 index 5244e69..0000000 --- a/nxyter/cores/pll_adc_clk.vhd +++ /dev/null @@ -1,99 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 187.5 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e - --- Mon Apr 7 15:14:44 2014 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity pll_adc_clk is - port ( - CLK: in std_logic; - RESET: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic); - attribute dont_touch : boolean; - attribute dont_touch of pll_adc_clk : entity is true; -end pll_adc_clk; - -architecture Structure of pll_adc_clk is - - -- internal signal declarations - signal CLKOP_t: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component EHXPLLF - generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; - DELAY_PWD : in String; DELAY_VAL : in Integer; - CLKOS_TRIM_DELAY : in Integer; - CLKOS_TRIM_POL : in String; - CLKOP_TRIM_DELAY : in Integer; - CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; - CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; - PHASE_DELAY_CNTL : in String; DUTY : in Integer; - PHASEADJ : in String; CLKOK_DIV : in Integer; - CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; - CLKI_DIV : in Integer; FIN : in String); - port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; - RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; - DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; - DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; - DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; - FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; - CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; - LOCK: out std_logic; CLKINTFB: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "187.500000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; - attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; - attribute NGD_DRC_MASK : integer; - attribute NGD_DRC_MASK of Structure : architecture is 1; - -begin - -- component instantiation statements - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - PLLInst_0: EHXPLLF - generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", - CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", - CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, - CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", - CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", - PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", - CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 15, CLKI_DIV=> 16, - FIN=> "200.000000") - port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, - WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, - DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, - DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, - FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, - FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, - CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); - - CLKOP <= CLKOP_t; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of pll_adc_clk is - for Structure - for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/nxyter/nodelist.txt b/nxyter/nodelist.txt index b7ca533..0c760d8 100755 --- a/nxyter/nodelist.txt +++ b/nxyter/nodelist.txt @@ -1,3 +1,8 @@ +[pbs1] +system = linux +corenum = 2 +env = /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ [pbs2] system = linux corenum = 2 diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 92cc132..6c958f3 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -13,46 +13,25 @@ entity adc_ad9228 is port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - CLK_ADCDAT_IN : in std_logic; RESET_ADCS : in std_logic; - ADC0_SCLK_IN : in std_logic; -- Sampling Clock ADC0 - ADC0_SCLK_OUT : out std_logic; - ADC0_DATA_A_IN : in std_logic; - ADC0_DATA_B_IN : in std_logic; - ADC0_DATA_C_IN : in std_logic; - ADC0_DATA_D_IN : in std_logic; - ADC0_DCLK_IN : in std_logic; -- Data Clock from ADC0 - ADC0_FCLK_IN : in std_logic; -- Frame Clock from ADC0 - - ADC1_SCLK_IN : in std_logic; -- Sampling Clock ADC1 - ADC1_SCLK_OUT : out std_logic; - ADC1_DATA_A_IN : in std_logic; - ADC1_DATA_B_IN : in std_logic; - ADC1_DATA_C_IN : in std_logic; - ADC1_DATA_D_IN : in std_logic; - ADC1_DCLK_IN : in std_logic; -- Data Clock from ADC1 - ADC1_FCLK_IN : in std_logic; -- Frame Clock from ADC1 + + ADC_SCLK_IN : in std_logic; -- Sampling Clock ADC0 + ADC_SCLK_OUT : out std_logic; + ADC_DATA_A_IN : in std_logic; + ADC_DATA_B_IN : in std_logic; + ADC_DATA_C_IN : in std_logic; + ADC_DATA_D_IN : in std_logic; + ADC_DCLK_IN : in std_logic; -- Data Clock from ADC0 + ADC_FCLK_IN : in std_logic; -- Frame Clock from ADC0 + + ADC_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_CLK_OUT : out std_logic; - ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_CLK_OUT : out std_logic; - - ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_CLK_OUT : out std_logic; - - ADC0_LOCKED_OUT : out std_logic; - ADC1_LOCKED_OUT : out std_logic; - - ADC0_SLOPPY_FRAME_IN : in std_logic; - ADC1_SLOPPY_FRAME_IN : in std_logic; - - ADC0_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); - ADC1_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC_LOCKED_OUT : out std_logic; + ADC_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) @@ -66,33 +45,59 @@ architecture Behavioral of adc_ad9228 is signal q_0_ff : std_logic_vector(19 downto 0); signal q_0_f : std_logic_vector(19 downto 0); signal q_0 : std_logic_vector(19 downto 0); - signal q_1_ff : std_logic_vector(19 downto 0); - signal q_1_f : std_logic_vector(19 downto 0); - signal q_1 : std_logic_vector(19 downto 0); - - -- ADC Data Handler - signal adc0_error_status_o : std_logic_vector(2 downto 0); - signal adc1_error_status_o : std_logic_vector(2 downto 0); + + -- ADC Frame Lock Handler + type adc_data_s is array(0 to 4) of std_logic_vector(14 downto 0); + type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + + type BYTE_STATUS is (B_INVALID, + B_ALIGNED, + B_ALIGNED_BIT_SHIFTED, + B_BYTE_SHIFTED, + B_BIT_SHIFTED, + B_BYTE_BIT_SHIFTED + ); + signal adc_data_shift : adc_data_s; - signal adc0_sloppy_frame_f : std_logic; - signal adc0_sloppy_frame_c : std_logic; - signal adc1_sloppy_frame_f : std_logic; - signal adc1_sloppy_frame_c : std_logic; - signal adc0_debug : std_logic_vector(15 downto 0); + signal adc_data_m : adc_data_t; + signal adc_data_clk_m : std_logic; + signal adc_byte_status : BYTE_STATUS; + signal adc_byte_status_last : BYTE_STATUS; + signal adc_frame_clk_ok : std_logic; + signal adc_frame_clk_ok_hist : std_logic_vector(15 downto 0); + signal adc_frame_locked : std_logic; + signal adc_status_fifo_clk : std_logic; + signal adc_status : std_logic_vector(3 downto 0); + signal adc_status_last : std_logic_vector(3 downto 0); + + -- Clock Domain Transfer ADC Data + signal adc_data : adc_data_t; + signal adc_fifo_empty : std_logic; + signal adc_fifo_full : std_logic; + signal adc_write_enable : std_logic; + signal adc_read_enable : std_logic; + signal adc_read_enable_t : std_logic; + signal adc_read_enable_tt : std_logic; - -- Data Types - type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + -- Clock Domain Transfer ADC Status + signal status : std_logic_vector(3 downto 0); + signal status_fifo_empty : std_logic; + signal status_fifo_full : std_logic; + signal status_write_enable : std_logic; + signal status_read_enable : std_logic; + signal status_read_enable_t : std_logic; + signal status_read_enable_tt : std_logic; + signal status_locked_ff : std_logic; + signal frame_locked_o : std_logic; + signal adc_status_o : std_logic_vector(2 downto 0); + signal status_clk_o : std_logic; + -- Output - signal adc0_data_clk_o : std_logic; - signal adc0_data_o : adc_data_t; - signal adc0_locked_o : std_logic; - signal adc0_error_o : std_logic; - - signal adc1_data_clk_o : std_logic; - signal adc1_data_o : adc_data_t; - signal adc1_locked_o : std_logic; - signal adc1_error_o : std_logic; + signal adc_data_clk_o : std_logic; + signal adc_data_o : adc_data_t; + signal adc_locked_o : std_logic; + signal adc_error_status_o : std_logic_vector(2 downto 0); -- RESET Handler type R_STATES is (R_IDLE, @@ -107,8 +112,8 @@ architecture Behavioral of adc_ad9228 is signal wait_timer_start : std_logic; signal wait_timer_done : std_logic; signal RESET_CLKDIV : std_logic; - signal RESET_ADC0 : std_logic; - signal RESET_ADC1 : std_logic; + signal RESET_ADC : std_logic; + signal debug_state : std_logic_vector(1 downto 0); @@ -117,26 +122,12 @@ architecture Behavioral of adc_ad9228 is attribute syn_keep of q_0_ff : signal is true; attribute syn_keep of q_0_f : signal is true; - attribute syn_keep of q_1_ff : signal is true; - attribute syn_keep of q_1_f : signal is true; - - attribute syn_keep of adc0_sloppy_frame_f : signal is true; - attribute syn_keep of adc0_sloppy_frame_c : signal is true; - attribute syn_keep of adc1_sloppy_frame_f : signal is true; - attribute syn_keep of adc1_sloppy_frame_c : signal is true; - + attribute syn_preserve : boolean; attribute syn_preserve of q_0_ff : signal is true; attribute syn_preserve of q_0_f : signal is true; - attribute syn_preserve of q_1_ff : signal is true; - attribute syn_preserve of q_1_f : signal is true; - - attribute syn_preserve of adc0_sloppy_frame_f : signal is true; - attribute syn_preserve of adc0_sloppy_frame_c : signal is true; - attribute syn_preserve of adc1_sloppy_frame_f : signal is true; - attribute syn_preserve of adc1_sloppy_frame_c : signal is true; - + begin ----------------------------------------------------------------------------- @@ -154,7 +145,11 @@ begin begin case DEBUG_IN is when x"1" => - DEBUG_OUT <= adc0_debug; + DEBUG_OUT(0) <= DDR_DATA_CLK; + DEBUG_OUT(1) <= adc_status(0); + DEBUG_OUT(2) <= adc_status(1); + DEBUG_OUT(3) <= adc_status(2); + DEBUG_OUT(15 downto 4) <= adc_data_shift(4)(11 downto 0); when others => DEBUG_OUT(0) <= CLK_IN; @@ -165,7 +160,7 @@ begin DEBUG_OUT(5) <= '0'; DEBUG_OUT(6) <= RESET_CLKDIV; DEBUG_OUT(7) <= '0'; - DEBUG_OUT(8) <= RESET_ADC0; + DEBUG_OUT(8) <= RESET_ADC; DEBUG_OUT(9) <= '0'; DEBUG_OUT(11 downto 10) <= debug_state; DEBUG_OUT(15 downto 12) <= (others => '0'); @@ -180,86 +175,276 @@ begin ----------------------------------------------------------------------------- adc_ddr_generic_1: entity work.adc_ddr_generic port map ( - clk_0 => ADC0_DCLK_IN, - clk_1 => ADC1_DCLK_IN, - clkdiv_reset => RESET_CLKDIV, - eclk => CLK_ADCDAT_IN, - reset_0 => RESET_ADC0, - reset_1 => RESET_ADC1, - sclk => DDR_DATA_CLK, - - datain_0(0) => ADC0_DATA_A_IN, - datain_0(1) => ADC0_DATA_B_IN, - datain_0(2) => ADC0_DATA_C_IN, - datain_0(3) => ADC0_DATA_D_IN, - datain_0(4) => ADC0_FCLK_IN, - - datain_1(0) => ADC1_DATA_A_IN, - datain_1(1) => ADC1_DATA_B_IN, - datain_1(2) => ADC1_DATA_C_IN, - datain_1(3) => ADC1_DATA_D_IN, - datain_1(4) => ADC1_FCLK_IN, - - q_0 => q_0_ff, - q_1 => q_1_ff + clk => ADC_DCLK_IN, + clkdiv_reset => '0', --RESET_CLKDIV, + eclk => open, + sclk => DDR_DATA_CLK, + datain(0) => ADC_DATA_A_IN, + datain(1) => ADC_DATA_B_IN, + datain(2) => ADC_DATA_C_IN, + datain(3) => ADC_DATA_D_IN, + datain(4) => ADC_FCLK_IN, + q => q_0_ff ); -- Two FIFOs to relaxe timing q_0_f <= q_0_ff when rising_edge(DDR_DATA_CLK); q_0 <= q_0_f when rising_edge(DDR_DATA_CLK); - q_1_f <= q_1_ff when rising_edge(DDR_DATA_CLK); - q_1 <= q_1_f when rising_edge(DDR_DATA_CLK); + ----------------------------------------------------------------------------- + -- Lock to ADC Frame Data + ----------------------------------------------------------------------------- - -- The ADC Data Handlers - adc0_sloppy_frame_f <= ADC0_SLOPPY_FRAME_IN when rising_edge(CLK_IN); - adc0_sloppy_frame_c <= adc0_sloppy_frame_f when rising_edge(CLK_IN); + PROC_LOCK_TO_ADC_FRAME: process(DDR_DATA_CLK) + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_IN = '1') then + for I in 0 to 4 loop + adc_data_shift(I) <= (others => '0'); + end loop; + + for I in 0 to 3 loop + adc_data_m(I) <= (others => '0'); + end loop; + adc_data_clk_m <= '0'; + + adc_byte_status <= B_INVALID; + adc_byte_status_last <= B_INVALID; + adc_frame_clk_ok <= '0'; + adc_frame_clk_ok_hist <= (others => '0'); + adc_frame_locked <= '0'; + adc_status <= (others => '0'); + else + -- Store new incoming Data in Shift Registers + for I in 0 to 4 loop + adc_data_shift(I)(3) <= q_0(I + 0); + adc_data_shift(I)(2) <= q_0(I + 5); + adc_data_shift(I)(1) <= q_0(I + 10); + adc_data_shift(I)(0) <= q_0(I + 15); + adc_data_shift(I)(14 downto 4) <= adc_data_shift(I)(10 downto 0); + end loop; + + ----------------------------------------------------------------------- + -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock + ----------------------------------------------------------------------- + case adc_data_shift(4)(14 downto 0) is + when "000111111000000" => + -- Input Data is correct and new Frame is available + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(11 downto 0); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED; + + when "001111110000001" => + -- Input Data is correct and new Frame is available, + -- but bit shifted by one + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(12 downto 1); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED_BIT_SHIFTED; + + when "011111100000011" => + -- Input Data is correct and new Frame is available, + -- but byte shifted by one + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(13 downto 2); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_BYTE_SHIFTED; + + when "111111000000111" => + -- Input Data is correct and new Frame is available, + -- but byte and bit shifted by one + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(14 downto 3); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_BYTE_BIT_SHIFTED; + + + when "111110000001111" | "100000011111100" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED; + + when "111100000011111" | "000000111111000" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED_BIT_SHIFTED; + + when "111000000111111" | "000001111110000" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_BYTE_SHIFTED; + + when "110000001111110" | "000011111100000" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_BYTE_BIT_SHIFTED; + + when others => + -- Input Data is invalid, Fatal Error + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '0'; + adc_byte_status <= B_INVALID; + + end case; + + -- Determin ADC Frame Lock Status + adc_frame_clk_ok_hist(0) <= adc_frame_clk_ok; + adc_frame_clk_ok_hist(15 downto 1) <= + adc_frame_clk_ok_hist(14 downto 0); + + if (adc_frame_clk_ok_hist = x"ffff") then + adc_frame_locked <= '1'; + adc_status(0) <= '1'; + else + adc_frame_locked <= '0'; + adc_status(0) <= '0'; + end if; + + -- Error Status + adc_byte_status_last <= adc_byte_status; + if (adc_byte_status /= adc_byte_status_last) then + adc_status(3) <= '1'; + else + adc_status(3) <= '0'; + end if; + + if (adc_byte_status = B_BYTE_SHIFTED or + adc_byte_status = B_BYTE_BIT_SHIFTED ) then + adc_status(1) <= '1'; + else + adc_status(1) <= '0'; + end if; + + if (adc_byte_status = B_BIT_SHIFTED or + adc_byte_status = B_ALIGNED_BIT_SHIFTED or + adc_byte_status = B_BYTE_BIT_SHIFTED) then + adc_status(2) <= '1'; + else + adc_status(2) <= '0'; + end if; + + adc_status_last <= adc_status; + if (adc_status /= adc_status_last) then + adc_status_fifo_clk <= '1'; + else + adc_status_fifo_clk <= '0'; + end if; + + end if; + + end if; + end process PROC_LOCK_TO_ADC_FRAME; - adc_ad9228_data_handler_adc0: entity work.adc_ad9228_data_handler - generic map ( - DEBUG_ENABLE => DEBUG_ENABLE - ) + ----------------------------------------------------------------------------- + -- Domain Tansfer of Data to CLK_IN + ----------------------------------------------------------------------------- + + fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC0, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_0, - DATA_A_OUT => adc0_data_o(0), - DATA_B_OUT => adc0_data_o(1), - DATA_C_OUT => adc0_data_o(2), - DATA_D_OUT => adc0_data_o(3), - DATA_CLK_OUT => adc0_data_clk_o, - SLOPPY_FRAME_IN => adc0_sloppy_frame_c, - FRAME_LOCKED_OUT => adc0_locked_o, - STATUS_OUT => adc0_error_status_o, - STATUS_CLK_OUT => open, - DEBUG_OUT => adc0_debug + Data(11 downto 0) => adc_data_m(0), + Data(23 downto 12) => adc_data_m(1), + Data(35 downto 24) => adc_data_m(2), + Data(47 downto 36) => adc_data_m(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc_write_enable, + RdEn => adc_read_enable, + Reset => RESET_IN, + RPReset => RESET_IN, + Q(11 downto 0) => adc_data(0), + Q(23 downto 12) => adc_data(1), + Q(35 downto 24) => adc_data(2), + Q(47 downto 36) => adc_data(3), + Empty => adc_fifo_empty, + Full => adc_fifo_full ); + + -- Readout Handler + adc_write_enable <= adc_data_clk_m and not adc_fifo_full; + adc_read_enable <= not adc_fifo_empty; - adc1_sloppy_frame_f <= ADC1_SLOPPY_FRAME_IN when rising_edge(CLK_IN); - adc1_sloppy_frame_c <= adc1_sloppy_frame_f when rising_edge(CLK_IN); + PROC_ADC_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + adc_read_enable_tt <= adc_read_enable; + if (RESET_IN = '1') then + adc_read_enable_t <= '0'; + for I in 0 to 3 loop + adc_data_o(I) <= (others => '0'); + end loop; + adc_data_clk_o <= '0'; + else + -- Read enable + adc_read_enable_t <= adc_read_enable_tt; + + if (adc_read_enable_t = '1') then + for I in 0 to 3 loop + adc_data_o(I) <= adc_data(I); + end loop; + adc_data_clk_o <= '1'; + else + adc_data_clk_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC_FIFO_READ; - adc_ad9228_data_handler_adc1: entity work.adc_ad9228_data_handler - generic map ( - DEBUG_ENABLE => DEBUG_ENABLE - ) + ----------------------------------------------------------------------------- + -- Domain Tansfer of Status to CLK_IN + ----------------------------------------------------------------------------- + + fifo_adc_status_4to4_dc_1: entity work.fifo_adc_status_4to4_dc port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_ADC1, - DDR_DATA_CLK => DDR_DATA_CLK, - DDR_DATA_IN => q_1, - DATA_A_OUT => adc1_data_o(0), - DATA_B_OUT => adc1_data_o(1), - DATA_C_OUT => adc1_data_o(2), - DATA_D_OUT => adc1_data_o(3), - DATA_CLK_OUT => adc1_data_clk_o, - SLOPPY_FRAME_IN => adc1_sloppy_frame_c, - FRAME_LOCKED_OUT => adc1_locked_o, - STATUS_OUT => adc1_error_status_o, - STATUS_CLK_OUT => open, - DEBUG_OUT => open + Data => adc_status, + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => status_write_enable, + RdEn => status_read_enable, + Reset => RESET_IN, + RPReset => RESET_IN, + Q => status, + Empty => status_fifo_empty, + Full => status_fifo_full ); + -- Readout Handler + status_write_enable <= adc_status_fifo_clk and not status_fifo_full; + status_read_enable <= not status_fifo_empty; + + PROC_ADC_STATUS_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + status_read_enable_tt <= status_read_enable; + if (RESET_IN = '1') then + status_read_enable_t <= '0'; + adc_status_o <= (others => '0'); + status_clk_o <= '0'; + else + -- Read enable + status_read_enable_t <= status_read_enable_tt; + + if (status_read_enable_t = '1') then + frame_locked_o <= status(0); + adc_status_o <= status(3 downto 1); + status_clk_o <= '1'; + end if; + end if; + end if; + end process PROC_ADC_STATUS_FIFO_READ; + ----------------------------------------------------------------------------- -- Error Status Handler ----------------------------------------------------------------------------- @@ -285,16 +470,14 @@ begin if (rising_edge(CLK_IN)) then if (RESET_IN = '1') then RESET_CLKDIV <= '0'; - RESET_ADC0 <= '0'; - RESET_ADC1 <= '0'; + RESET_ADC <= '0'; wait_timer_start <= '0'; timer_reset <= '1'; R_STATE <= R_IDLE; debug_state <= "00"; else RESET_CLKDIV <= '0'; - RESET_ADC0 <= '0'; - RESET_ADC1 <= '0'; + RESET_ADC <= '0'; wait_timer_start <= '0'; timer_reset <= '0'; @@ -303,8 +486,7 @@ begin if (RESET_ADCS = '1') then -- Start Reset RESET_CLKDIV <= '1'; - RESET_ADC0 <= '1'; - RESET_ADC1 <= '1'; + RESET_ADC <= '1'; wait_timer_start <= '1'; R_STATE <= R_WAIT_CLKDIV; else @@ -316,13 +498,11 @@ begin when R_WAIT_CLKDIV => if (wait_timer_done = '0') then RESET_CLKDIV <= '1'; - RESET_ADC0 <= '1'; - RESET_ADC1 <= '1'; + RESET_ADC <= '1'; R_STATE <= R_WAIT_CLKDIV; else -- Release RESET_CLKDIV - RESET_ADC0 <= '1'; - RESET_ADC1 <= '1'; + RESET_ADC <= '1'; wait_timer_start <= '1'; R_STATE <= R_WAIT_RESET_ADC; end if; @@ -330,8 +510,7 @@ begin when R_WAIT_RESET_ADC => if (wait_timer_done = '0') then - RESET_ADC0 <= '1'; - RESET_ADC1 <= '1'; + RESET_ADC <= '1'; R_STATE <= R_WAIT_RESET_ADC; else -- Release reset_adc @@ -355,24 +534,15 @@ begin ----------------------------------------------------------------------------- -- Outputs ----------------------------------------------------------------------------- - ADC0_SCLK_OUT <= ADC0_SCLK_IN; - ADC1_SCLK_OUT <= ADC1_SCLK_IN; + ADC_SCLK_OUT <= ADC_SCLK_IN; - ADC0_DATA_A_OUT <= adc0_data_o(0); - ADC0_DATA_B_OUT <= adc0_data_o(1); - ADC0_DATA_C_OUT <= adc0_data_o(2); - ADC0_DATA_D_OUT <= adc0_data_o(3); - ADC0_DATA_CLK_OUT <= adc0_data_clk_o; - - ADC1_DATA_A_OUT <= adc1_data_o(0); - ADC1_DATA_B_OUT <= adc1_data_o(1); - ADC1_DATA_C_OUT <= adc1_data_o(2); - ADC1_DATA_D_OUT <= adc1_data_o(3); - ADC1_DATA_CLK_OUT <= adc1_data_clk_o; - - ADC0_LOCKED_OUT <= adc0_locked_o; - ADC1_LOCKED_OUT <= adc1_locked_o; - - ADC0_ERROR_STATUS_OUT <= adc0_error_status_o; - ADC1_ERROR_STATUS_OUT <= adc1_error_status_o; + ADC_DATA_A_OUT <= adc_data_o(0); + ADC_DATA_B_OUT <= adc_data_o(1); + ADC_DATA_C_OUT <= adc_data_o(2); + ADC_DATA_D_OUT <= adc_data_o(3); + ADC_DATA_CLK_OUT <= adc_data_clk_o; + + ADC_LOCKED_OUT <= adc_locked_o; + ADC_ERROR_STATUS_OUT <= adc_status_o; + end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index df95b98..1440a2b 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -24,15 +24,15 @@ entity nx_data_receiver is NX_TIMESTAMP_RESET_OUT : out std_logic; -- ADC Ports - ADC_CLK_DAT_IN : in std_logic; - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); ADC_SCLK_LOCK_OUT : out std_logic; + + ADC_FCLK_IN : in std_logic; + ADC_DCLK_IN : in std_logic; + ADC_A_IN : in std_logic; + ADC_B_IN : in std_logic; + ADC_NX_IN : in std_logic; + ADC_D_IN : in std_logic; -- Outputs DATA_OUT : out std_logic_vector(43 downto 0); @@ -467,7 +467,7 @@ begin DEBUG_OUT(12) <= '0'; DEBUG_OUT(13) <= '0'; DEBUG_OUT(14) <= '0'; - DEBUG_OUT(15) <= ADC_SAMPLE_CLK_OUT; + DEBUG_OUT(15) <= '0'; --ADC_SAMPLE_CLK_OUT; (not readable) when others => -- Default @@ -853,50 +853,28 @@ begin DEBUG_ENABLE => true ) port map ( - CLK_IN => NX_DATA_CLK_IN, - RESET_IN => RESET_NX_DATA_CLK_IN, - CLK_ADCDAT_IN => ADC_CLK_DAT_IN, - RESET_ADCS => ADC_RESET_AD9228, - - ADC0_SCLK_IN => pll_adc_sampling_clk_o, - ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT, - ADC0_DATA_A_IN => ADC_NX_IN(0), - ADC0_DATA_B_IN => ADC_B_IN(0), - ADC0_DATA_C_IN => ADC_A_IN(0), - ADC0_DATA_D_IN => ADC_D_IN(0), - ADC0_DCLK_IN => ADC_DCLK_IN(0), - ADC0_FCLK_IN => ADC_FCLK_IN(0), - - ADC1_SCLK_IN => pll_adc_sampling_clk_o, - ADC1_SCLK_OUT => open, - ADC1_DATA_A_IN => ADC_NX_IN(1), - ADC1_DATA_B_IN => ADC_A_IN(1), - ADC1_DATA_C_IN => ADC_B_IN(1), - ADC1_DATA_D_IN => ADC_D_IN(1), - ADC1_DCLK_IN => ADC_DCLK_IN(1), - ADC1_FCLK_IN => ADC_FCLK_IN(1), - - ADC0_DATA_A_OUT => adc_data, - ADC0_DATA_B_OUT => open, - ADC0_DATA_C_OUT => open, - ADC0_DATA_D_OUT => open, - ADC0_DATA_CLK_OUT => adc_data_clk, - - ADC1_DATA_A_OUT => open, - ADC1_DATA_B_OUT => open, - ADC1_DATA_C_OUT => open, - ADC1_DATA_D_OUT => open, - ADC1_DATA_CLK_OUT => open, - - ADC0_LOCKED_OUT => adc_locked, - ADC1_LOCKED_OUT => open, - - ADC0_SLOPPY_FRAME_IN => adc_sloppy_frame, - ADC1_SLOPPY_FRAME_IN => '0', + CLK_IN => NX_DATA_CLK_IN, + RESET_IN => RESET_NX_DATA_CLK_IN, + RESET_ADCS => ADC_RESET_AD9228, + + ADC_SCLK_IN => pll_adc_sampling_clk_o, + ADC_SCLK_OUT => ADC_SAMPLE_CLK_OUT, + ADC_DATA_A_IN => ADC_NX_IN, + ADC_DATA_B_IN => ADC_B_IN, + ADC_DATA_C_IN => ADC_A_IN, + ADC_DATA_D_IN => ADC_D_IN, + ADC_DCLK_IN => ADC_DCLK_IN, + ADC_FCLK_IN => ADC_FCLK_IN, + + ADC_DATA_A_OUT => adc_data, + ADC_DATA_B_OUT => open, + ADC_DATA_C_OUT => open, + ADC_DATA_D_OUT => open, + ADC_DATA_CLK_OUT => adc_data_clk, + + ADC_LOCKED_OUT => adc_locked, + ADC_ERROR_STATUS_OUT => adc_error_status_i, - ADC0_ERROR_STATUS_OUT => adc_error_status_i, - ADC1_ERROR_STATUS_OUT => open, - DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG ); diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 8b831c1..da5242a 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -7,6 +7,7 @@ package nxyter_components is ------------------------------------------------------------------------------- -- TRBNet interfaces ------------------------------------------------------------------------------- + component nXyter_FEE_board generic ( BOARD_ID : std_logic_vector(1 downto 0)); @@ -14,9 +15,7 @@ package nxyter_components is CLK_IN : in std_logic; RESET_IN : in std_logic; CLK_NX_MAIN_IN : in std_logic; - CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; - PLL_ADC_DCLK_LOCK_IN : in std_logic; PLL_RESET_OUT : out std_logic; TRIGGER_OUT : out std_logic; I2C_SDA_INOUT : inout std_logic; @@ -31,13 +30,13 @@ package nxyter_components is NX_RESET_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; NX_TIMESTAMP_TRIGGER_OUT : out std_logic; - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); + ADC_FCLK_IN : in std_logic; + ADC_DCLK_IN : in std_logic; + ADC_A_IN : in std_logic; + ADC_B_IN : in std_logic; + ADC_NX_IN : in std_logic; + ADC_D_IN : in std_logic; TIMING_TRIGGER_IN : in std_logic; LVL1_TRG_DATA_VALID_IN : in std_logic; LVL1_VALID_TIMING_TRG_IN : in std_logic; @@ -67,785 +66,765 @@ package nxyter_components is DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) ); end component; - + ------------------------------------------------------------------------------- -- nXyter I2C Interface ------------------------------------------------------------------------------- -component nx_i2c_master - generic ( - I2C_SPEED : unsigned(11 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SDA_INOUT : inout std_logic; - SCL_INOUT : inout std_logic; - INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); - COMMAND_BUSY_OUT : out std_logic; - I2C_DATA_OUT : out std_logic_vector(31 downto 0); - I2C_DATA_BYTES_OUT : out std_logic_vector(31 downto 0); - I2C_LOCK_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_i2c_startstop - generic ( - I2C_SPEED : unsigned(11 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; -- Start Sequence - SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop - SEQUENCE_DONE_OUT : out std_logic; - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - NREADY_OUT : out std_logic - ); -end component; - -component nx_i2c_sendbyte - generic ( - I2C_SPEED : unsigned(11 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - BYTE_IN : in std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - SDA_IN : in std_logic; - SCL_IN : in std_logic; - ACK_OUT : out std_logic - ); -end component; - -component nx_i2c_readbyte - generic ( - I2C_SPEED : unsigned(11 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - NUM_BYTES_IN : in unsigned(2 downto 0); - BYTE_OUT : out std_logic_vector(31 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - SDA_OUT : out std_logic; - SCL_OUT : out std_logic; - SDA_IN : in std_logic - ); -end component; + component nx_i2c_master + generic ( + I2C_SPEED : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); + COMMAND_BUSY_OUT : out std_logic; + I2C_DATA_OUT : out std_logic_vector(31 downto 0); + I2C_DATA_BYTES_OUT : out std_logic_vector(31 downto 0); + I2C_LOCK_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_i2c_startstop + generic ( + I2C_SPEED : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; -- Start Sequence + SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop + SEQUENCE_DONE_OUT : out std_logic; + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + NREADY_OUT : out std_logic + ); + end component; + + component nx_i2c_sendbyte + generic ( + I2C_SPEED : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic; + SCL_IN : in std_logic; + ACK_OUT : out std_logic + ); + end component; + + component nx_i2c_readbyte + generic ( + I2C_SPEED : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + NUM_BYTES_IN : in unsigned(2 downto 0); + BYTE_OUT : out std_logic_vector(31 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic + ); + end component; ------------------------------------------------------------------------------- -- ADC SPI Interface ------------------------------------------------------------------------------- -component adc_spi_master - generic ( - SPI_SPEED : unsigned(7 downto 0)); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SCLK_OUT : out std_logic; - SDIO_INOUT : inout std_logic; - CSB_OUT : out std_logic; - INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); - COMMAND_ACK_OUT : out std_logic; - SPI_DATA_OUT : out std_logic_vector(31 downto 0); - SPI_LOCK_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component adc_spi_sendbyte - generic ( - SPI_SPEED : unsigned(7 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - BYTE_IN : in std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - SCLK_OUT : out std_logic; - SDIO_OUT : out std_logic - ); -end component; - -component adc_spi_readbyte - generic ( - SPI_SPEED : unsigned(7 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - START_IN : in std_logic; - BYTE_OUT : out std_logic_vector(7 downto 0); - SEQUENCE_DONE_OUT : out std_logic; - SDIO_IN : in std_logic; - SCLK_OUT : out std_logic - ); -end component; + component adc_spi_master + generic ( + SPI_SPEED : unsigned(7 downto 0)); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SCLK_OUT : out std_logic; + SDIO_INOUT : inout std_logic; + CSB_OUT : out std_logic; + INTERNAL_COMMAND_IN : in std_logic_vector(31 downto 0); + COMMAND_ACK_OUT : out std_logic; + SPI_DATA_OUT : out std_logic_vector(31 downto 0); + SPI_LOCK_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component adc_spi_sendbyte + generic ( + SPI_SPEED : unsigned(7 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SCLK_OUT : out std_logic; + SDIO_OUT : out std_logic + ); + end component; + + component adc_spi_readbyte + generic ( + SPI_SPEED : unsigned(7 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_OUT : out std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SDIO_IN : in std_logic; + SCLK_OUT : out std_logic + ); + end component; ------------------------------------------------------------------------------- -- ADC Data Handler ------------------------------------------------------------------------------- -component adc_ad9228 - generic ( - DEBUG_ENABLE : boolean); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_ADCDAT_IN : in std_logic; - RESET_ADCS : in std_logic; - ADC0_SCLK_IN : in std_logic; - ADC0_SCLK_OUT : out std_logic; - ADC0_DATA_A_IN : in std_logic; - ADC0_DATA_B_IN : in std_logic; - ADC0_DATA_C_IN : in std_logic; - ADC0_DATA_D_IN : in std_logic; - ADC0_DCLK_IN : in std_logic; - ADC0_FCLK_IN : in std_logic; - ADC1_SCLK_IN : in std_logic; - ADC1_SCLK_OUT : out std_logic; - ADC1_DATA_A_IN : in std_logic; - ADC1_DATA_B_IN : in std_logic; - ADC1_DATA_C_IN : in std_logic; - ADC1_DATA_D_IN : in std_logic; - ADC1_DCLK_IN : in std_logic; - ADC1_FCLK_IN : in std_logic; - ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_CLK_OUT : out std_logic; - ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_CLK_OUT : out std_logic; - ADC0_LOCKED_OUT : out std_logic; - ADC1_LOCKED_OUT : out std_logic; - ADC0_SLOPPY_FRAME_IN : in std_logic; - ADC1_SLOPPY_FRAME_IN : in std_logic; - ADC0_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); - ADC1_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); - DEBUG_IN : in std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; + component adc_ad9228 + generic ( + DEBUG_ENABLE : boolean); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + RESET_ADCS : in std_logic; + ADC_SCLK_IN : in std_logic; + ADC_SCLK_OUT : out std_logic; + ADC_DATA_A_IN : in std_logic; + ADC_DATA_B_IN : in std_logic; + ADC_DATA_C_IN : in std_logic; + ADC_DATA_D_IN : in std_logic; + ADC_DCLK_IN : in std_logic; + ADC_FCLK_IN : in std_logic; + ADC_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC_DATA_CLK_OUT : out std_logic; + ADC_LOCKED_OUT : out std_logic; + ADC_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + DEBUG_IN : in std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0)); + end component; ------------------------------------------------------------------------------- -- TRBNet Registers ------------------------------------------------------------------------------- -component nx_register_setup - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - I2C_ONLINE_IN : in std_logic; - I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); - I2C_COMMAND_BUSY_IN : in std_logic; - I2C_DATA_IN : in std_logic_vector(31 downto 0); - I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0); - I2C_LOCK_OUT : out std_logic; - I2C_REG_RESET_IN : in std_logic; - SPI_COMMAND_OUT : out std_logic_vector(31 downto 0); - SPI_COMMAND_BUSY_IN : in std_logic; - SPI_DATA_IN : in std_logic_vector(31 downto 0); - SPI_LOCK_OUT : out std_logic; - INT_READ_IN : in std_logic; - INT_ADDR_IN : in std_logic_vector(15 downto 0); - INT_ACK_OUT : out std_logic; - INT_DATA_OUT : out std_logic_vector(31 downto 0); - NX_CLOCK_ON_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_status - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - PLL_NX_CLK_LOCK_IN : in std_logic; - PLL_ADC_DCLK_LOCK_IN : in std_logic; - PLL_ADC_SCLK_LOCK_IN : in std_logic; - PLL_RESET_OUT : out std_logic; - I2C_SM_RESET_OUT : inout std_logic; - I2C_REG_RESET_OUT : out std_logic; - NX_ONLINE_OUT : out std_logic; - ERROR_ALL_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component fifo_data_stream_44to44_dc - port ( - Data : in std_logic_vector(43 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(43 downto 0); - Empty : out std_logic; - Full : out std_logic - ); -end component; - -component fifo_44_data_delay_my - port ( - Data : in std_logic_vector(43 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - AmEmptyThresh : in std_logic_vector(7 downto 0); - Q : out std_logic_vector(43 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_data_receiver - generic ( - DEBUG_ENABLE : boolean - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TRIGGER_IN : in std_logic; - NX_ONLINE_IN : in std_logic; - NX_CLOCK_ON_IN : in std_logic; - NX_DATA_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_TIMESTAMP_RESET_OUT : out std_logic; - ADC_CLK_DAT_IN : in std_logic; - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); - ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); - ADC_SCLK_LOCK_OUT : out std_logic; - DATA_OUT : out std_logic_vector(43 downto 0); - DATA_CLK_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - ADC_TR_ERROR_IN : in std_logic; - DISABLE_ADC_OUT : out std_logic; - ERROR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_data_delay - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DATA_IN : in std_logic_vector(43 downto 0); - DATA_CLK_IN : in std_logic; - DATA_OUT : out std_logic_vector(43 downto 0); - DATA_CLK_OUT : out std_logic; - FIFO_DELAY_IN : in std_logic_vector(7 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_data_validate - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DATA_IN : in std_logic_vector(43 downto 0); - DATA_CLK_IN : in std_logic; - TIMESTAMP_OUT : out std_logic_vector(13 downto 0); - CHANNEL_OUT : out std_logic_vector(6 downto 0); - TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); - ADC_DATA_OUT : out std_logic_vector(11 downto 0); - DATA_CLK_OUT : out std_logic; - NX_TOKEN_RETURN_OUT : out std_logic; - NX_NOMORE_DATA_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - ADC_TR_ERROR_OUT : out std_logic; - DISABLE_ADC_IN : in std_logic; - ERROR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_trigger_validate - generic ( - BOARD_ID : std_logic_vector(1 downto 0); - VERSION_NUMBER : std_logic_vector(3 downto 0)); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DATA_CLK_IN : in std_logic; - TIMESTAMP_IN : in std_logic_vector(13 downto 0); - CHANNEL_IN : in std_logic_vector(6 downto 0); - TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); - ADC_DATA_IN : in std_logic_vector(11 downto 0); - NX_TOKEN_RETURN_IN : in std_logic; - NX_NOMORE_DATA_IN : in std_logic; - TRIGGER_IN : in std_logic; - TRIGGER_CALIBRATION_IN : in std_logic; - TRIGGER_BUSY_IN : in std_logic; - FAST_CLEAR_IN : in std_logic; - TRIGGER_BUSY_OUT : out std_logic; - TIMESTAMP_FPGA_IN : in unsigned(11 downto 0); - DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(31 downto 0); - DATA_CLK_OUT : out std_logic; - NOMORE_DATA_OUT : out std_logic; - EVT_BUFFER_CLEAR_OUT : out std_logic; - EVT_BUFFER_FULL_IN : in std_logic; - HISTOGRAM_RESET_OUT : out std_logic; - HISTOGRAM_FILL_OUT : out std_logic; - HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); - HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0); - HISTOGRAM_TS_OUT : out std_logic_vector(8 downto 0); - HISTOGRAM_PILEUP_OUT : out std_logic; - HISTOGRAM_OVERFLOW_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_event_buffer - generic ( - BOARD_ID : std_logic_vector(1 downto 0) - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - RESET_DATA_BUFFER_IN : in std_logic; - NXYTER_OFFLINE_IN : in std_logic; - DATA_IN : in std_logic_vector(31 downto 0); - DATA_CLK_IN : in std_logic; - EVT_NOMORE_DATA_IN : in std_logic; - TRIGGER_IN : in std_logic; - FAST_CLEAR_IN : in std_logic; - TRIGGER_BUSY_OUT : out std_logic; - EVT_BUFFER_FULL_OUT : out std_logic; - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_ALMOST_FULL_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - ERROR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_status_event - generic ( - BOARD_ID : std_logic_vector(1 downto 0); - VERSION_NUMBER : std_logic_vector(3 downto 0)); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NXYTER_OFFLINE_IN : in std_logic; - TRIGGER_IN : in std_logic; - FAST_CLEAR_IN : in std_logic; - TRIGGER_BUSY_OUT : out std_logic; - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_ALMOST_FULL_IN : in std_logic; - INT_READ_OUT : out std_logic; - INT_ADDR_OUT : out std_logic_vector(15 downto 0); - INT_ACK_IN : in std_logic; - INT_DATA_IN : in std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; + component nx_register_setup + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + I2C_ONLINE_IN : in std_logic; + I2C_COMMAND_OUT : out std_logic_vector(31 downto 0); + I2C_COMMAND_BUSY_IN : in std_logic; + I2C_DATA_IN : in std_logic_vector(31 downto 0); + I2C_DATA_BYTES_IN : in std_logic_vector(31 downto 0); + I2C_LOCK_OUT : out std_logic; + I2C_REG_RESET_IN : in std_logic; + SPI_COMMAND_OUT : out std_logic_vector(31 downto 0); + SPI_COMMAND_BUSY_IN : in std_logic; + SPI_DATA_IN : in std_logic_vector(31 downto 0); + SPI_LOCK_OUT : out std_logic; + INT_READ_IN : in std_logic; + INT_ADDR_IN : in std_logic_vector(15 downto 0); + INT_ACK_OUT : out std_logic; + INT_DATA_OUT : out std_logic_vector(31 downto 0); + NX_CLOCK_ON_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_status + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PLL_NX_CLK_LOCK_IN : in std_logic; + PLL_ADC_DCLK_LOCK_IN : in std_logic; + PLL_ADC_SCLK_LOCK_IN : in std_logic; + PLL_RESET_OUT : out std_logic; + I2C_SM_RESET_OUT : inout std_logic; + I2C_REG_RESET_OUT : out std_logic; + NX_ONLINE_OUT : out std_logic; + ERROR_ALL_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component fifo_data_stream_44to44_dc + port ( + Data : in std_logic_vector(43 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(43 downto 0); + Empty : out std_logic; + Full : out std_logic + ); + end component; + + component fifo_44_data_delay_my + port ( + Data : in std_logic_vector(43 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmEmptyThresh : in std_logic_vector(7 downto 0); + Q : out std_logic_vector(43 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_data_receiver + generic ( + DEBUG_ENABLE : boolean); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TRIGGER_IN : in std_logic; + NX_ONLINE_IN : in std_logic; + NX_CLOCK_ON_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + NX_TIMESTAMP_RESET_OUT : out std_logic; + ADC_SAMPLE_CLK_OUT : out std_logic; + ADC_SCLK_LOCK_OUT : out std_logic; + ADC_FCLK_IN : in std_logic; + ADC_DCLK_IN : in std_logic; + ADC_A_IN : in std_logic; + ADC_B_IN : in std_logic; + ADC_NX_IN : in std_logic; + ADC_D_IN : in std_logic; + DATA_OUT : out std_logic_vector(43 downto 0); + DATA_CLK_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + ADC_TR_ERROR_IN : in std_logic; + DISABLE_ADC_OUT : out std_logic; + ERROR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_data_delay + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DATA_IN : in std_logic_vector(43 downto 0); + DATA_CLK_IN : in std_logic; + DATA_OUT : out std_logic_vector(43 downto 0); + DATA_CLK_OUT : out std_logic; + FIFO_DELAY_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_data_validate + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DATA_IN : in std_logic_vector(43 downto 0); + DATA_CLK_IN : in std_logic; + TIMESTAMP_OUT : out std_logic_vector(13 downto 0); + CHANNEL_OUT : out std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC_DATA_OUT : out std_logic_vector(11 downto 0); + DATA_CLK_OUT : out std_logic; + NX_TOKEN_RETURN_OUT : out std_logic; + NX_NOMORE_DATA_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + ADC_TR_ERROR_OUT : out std_logic; + DISABLE_ADC_IN : in std_logic; + ERROR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_trigger_validate + generic ( + BOARD_ID : std_logic_vector(1 downto 0); + VERSION_NUMBER : std_logic_vector(3 downto 0)); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DATA_CLK_IN : in std_logic; + TIMESTAMP_IN : in std_logic_vector(13 downto 0); + CHANNEL_IN : in std_logic_vector(6 downto 0); + TIMESTAMP_STATUS_IN : in std_logic_vector(2 downto 0); + ADC_DATA_IN : in std_logic_vector(11 downto 0); + NX_TOKEN_RETURN_IN : in std_logic; + NX_NOMORE_DATA_IN : in std_logic; + TRIGGER_IN : in std_logic; + TRIGGER_CALIBRATION_IN : in std_logic; + TRIGGER_BUSY_IN : in std_logic; + FAST_CLEAR_IN : in std_logic; + TRIGGER_BUSY_OUT : out std_logic; + TIMESTAMP_FPGA_IN : in unsigned(11 downto 0); + DATA_FIFO_DELAY_OUT : out std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATA_CLK_OUT : out std_logic; + NOMORE_DATA_OUT : out std_logic; + EVT_BUFFER_CLEAR_OUT : out std_logic; + EVT_BUFFER_FULL_IN : in std_logic; + HISTOGRAM_RESET_OUT : out std_logic; + HISTOGRAM_FILL_OUT : out std_logic; + HISTOGRAM_BIN_OUT : out std_logic_vector(6 downto 0); + HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0); + HISTOGRAM_TS_OUT : out std_logic_vector(8 downto 0); + HISTOGRAM_PILEUP_OUT : out std_logic; + HISTOGRAM_OVERFLOW_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_event_buffer + generic ( + BOARD_ID : std_logic_vector(1 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + RESET_DATA_BUFFER_IN : in std_logic; + NXYTER_OFFLINE_IN : in std_logic; + DATA_IN : in std_logic_vector(31 downto 0); + DATA_CLK_IN : in std_logic; + EVT_NOMORE_DATA_IN : in std_logic; + TRIGGER_IN : in std_logic; + FAST_CLEAR_IN : in std_logic; + TRIGGER_BUSY_OUT : out std_logic; + EVT_BUFFER_FULL_OUT : out std_logic; + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + ERROR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_status_event + generic ( + BOARD_ID : std_logic_vector(1 downto 0); + VERSION_NUMBER : std_logic_vector(3 downto 0)); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NXYTER_OFFLINE_IN : in std_logic; + TRIGGER_IN : in std_logic; + FAST_CLEAR_IN : in std_logic; + TRIGGER_BUSY_OUT : out std_logic; + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_ALMOST_FULL_IN : in std_logic; + INT_READ_OUT : out std_logic; + INT_ADDR_OUT : out std_logic_vector(15 downto 0); + INT_ACK_IN : in std_logic; + INT_DATA_IN : in std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; ------------------------------------------------------------------------------- -component nx_histogram - generic ( - BUS_WIDTH : integer - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NUM_AVERAGES_IN : in unsigned(2 downto 0); - AVERAGE_ENABLE_IN : in std_logic; - CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); - CHANNEL_DATA_IN : in std_logic_vector(31 downto 0); - CHANNEL_ADD_IN : in std_logic; - CHANNEL_WRITE_IN : in std_logic; - CHANNEL_WRITE_BUSY_OUT : out std_logic; - CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); - CHANNEL_READ_IN : in std_logic; - CHANNEL_DATA_OUT : out std_logic_vector(31 downto 0); - CHANNEL_DATA_VALID_OUT : out std_logic; - CHANNEL_READ_BUSY_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0)); -end component; - -component nx_histograms - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - RESET_HISTS_IN : in std_logic; - CHANNEL_FILL_IN : in std_logic; - CHANNEL_ID_IN : in std_logic_vector(6 downto 0); - CHANNEL_ADC_IN : in std_logic_vector(11 downto 0); - CHANNEL_TS_IN : in std_logic_vector(8 downto 0); - CHANNEL_PILEUP_IN : in std_logic; - CHANNEL_OVERFLOW_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; + component nx_histogram + generic ( + BUS_WIDTH : integer + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NUM_AVERAGES_IN : in unsigned(2 downto 0); + AVERAGE_ENABLE_IN : in std_logic; + CHANNEL_ID_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); + CHANNEL_DATA_IN : in std_logic_vector(31 downto 0); + CHANNEL_ADD_IN : in std_logic; + CHANNEL_WRITE_IN : in std_logic; + CHANNEL_WRITE_BUSY_OUT : out std_logic; + CHANNEL_ID_READ_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); + CHANNEL_READ_IN : in std_logic; + CHANNEL_DATA_OUT : out std_logic_vector(31 downto 0); + CHANNEL_DATA_VALID_OUT : out std_logic; + CHANNEL_READ_BUSY_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0)); + end component; + + component nx_histograms + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + RESET_HISTS_IN : in std_logic; + CHANNEL_FILL_IN : in std_logic; + CHANNEL_ID_IN : in std_logic_vector(6 downto 0); + CHANNEL_ADC_IN : in std_logic_vector(11 downto 0); + CHANNEL_TS_IN : in std_logic_vector(8 downto 0); + CHANNEL_PILEUP_IN : in std_logic; + CHANNEL_OVERFLOW_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; ------------------------------------------------------------------------------- -component level_to_pulse - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - LEVEL_IN : in std_logic; - PULSE_OUT : out std_logic - ); -end component; - -component pulse_to_level - generic ( - NUM_CYCLES : integer range 2 to 15 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - PULSE_IN : in std_logic; - LEVEL_OUT : out std_logic - ); -end component; - -component signal_async_to_pulse - generic ( - NUM_FF : integer range 2 to 4 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - PULSE_A_IN : in std_logic; - PULSE_OUT : out std_logic - ); -end component; - -component signal_async_trans - generic ( - NUM_FF : integer range 2 to 5 - ); - port ( - CLK_IN : in std_logic; - SIGNAL_A_IN : in std_logic; - SIGNAL_OUT : out std_logic - ); -end component; - -component bus_async_trans - generic ( - BUS_WIDTH : integer range 2 to 32; - NUM_FF : integer range 2 to 4); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SIGNAL_A_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); - SIGNAL_OUT : out std_logic_vector(BUS_WIDTH - 1 downto 0) - ); -end component; - -component pulse_dtrans - generic ( - CLK_RATIO : integer range 2 to 15 - ); - port ( - CLK_A_IN : in std_logic; - RESET_A_IN : in std_logic; - PULSE_A_IN : in std_logic; - CLK_B_IN : in std_logic; - RESET_B_IN : in std_logic; - PULSE_B_OUT : out std_logic - ); -end component; - -component Gray_Decoder - generic ( - WIDTH : integer range 2 to 32 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0); - BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0) - ); -end component; - -component Gray_Encoder - generic ( - WIDTH : integer range 2 to 32 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0); - GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0) - ); -end component; - -component pulse_delay - generic ( - DELAY : integer range 2 to 16777216); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - PULSE_IN : in std_logic; - PULSE_OUT : out std_logic - ); -end component; - -component nx_fpga_timestamp - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; - TIMESTAMP_RESET_IN : in std_logic; - TIMESTAMP_RESET_OUT : out std_logic; - TRIGGER_IN : in std_logic; - TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); - TIMESTAMP_TRIGGER_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_trigger_handler - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NX_MAIN_CLK_IN : in std_logic; - NXYTER_OFFLINE_IN : in std_logic; - TIMING_TRIGGER_IN : in std_logic; - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_VALID_TIMING_TRG_IN : in std_logic; - LVL1_VALID_NOTIMING_TRG_IN : in std_logic; - LVL1_INVALID_TRG_IN : in std_logic; - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - FEE_DATA_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_WRITE_OUT : out std_logic; - FEE_DATA_FINISHED_OUT : out std_logic; - FEE_TRG_RELEASE_OUT : out std_logic; - FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); - FEE_DATA_0_IN : in std_logic_vector(31 downto 0); - FEE_DATA_WRITE_0_IN : in std_logic; - FEE_DATA_1_IN : in std_logic_vector(31 downto 0); - FEE_DATA_WRITE_1_IN : in std_logic; - INTERNAL_TRIGGER_IN : in std_logic; - TRIGGER_VALIDATE_BUSY_IN : in std_logic; - TRIGGER_BUSY_0_IN : in std_logic; - TRIGGER_BUSY_1_IN : in std_logic; - VALID_TRIGGER_OUT : out std_logic; - TIMESTAMP_TRIGGER_OUT : out std_logic; - TRIGGER_TIMING_OUT : out std_logic; - TRIGGER_STATUS_OUT : out std_logic; - TRIGGER_CALIBRATION_OUT : out std_logic; - FAST_CLEAR_OUT : out std_logic; - TRIGGER_BUSY_OUT : out std_logic; - NX_TESTPULSE_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - -component nx_trigger_generator - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TRIGGER_BUSY_IN : in std_logic; - EXTERNAL_TRIGGER_OUT : out std_logic; - INTERNAL_TRIGGER_OUT : out std_logic; - DATA_IN : in std_logic_vector(43 downto 0); - DATA_CLK_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; + component level_to_pulse + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + LEVEL_IN : in std_logic; + PULSE_OUT : out std_logic + ); + end component; + + component pulse_to_level + generic ( + NUM_CYCLES : integer range 2 to 15 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_IN : in std_logic; + LEVEL_OUT : out std_logic + ); + end component; + + component signal_async_to_pulse + generic ( + NUM_FF : integer range 2 to 4 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_A_IN : in std_logic; + PULSE_OUT : out std_logic + ); + end component; + + component signal_async_trans + generic ( + NUM_FF : integer range 2 to 5 + ); + port ( + CLK_IN : in std_logic; + SIGNAL_A_IN : in std_logic; + SIGNAL_OUT : out std_logic + ); + end component; + + component bus_async_trans + generic ( + BUS_WIDTH : integer range 2 to 32; + NUM_FF : integer range 2 to 4); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SIGNAL_A_IN : in std_logic_vector(BUS_WIDTH - 1 downto 0); + SIGNAL_OUT : out std_logic_vector(BUS_WIDTH - 1 downto 0) + ); + end component; + + component pulse_dtrans + generic ( + CLK_RATIO : integer range 2 to 15 + ); + port ( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); + end component; + + component Gray_Decoder + generic ( + WIDTH : integer range 2 to 32 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0); + BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0) + ); + end component; + + component Gray_Encoder + generic ( + WIDTH : integer range 2 to 32 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0); + GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0) + ); + end component; + + component pulse_delay + generic ( + DELAY : integer range 2 to 16777216); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PULSE_IN : in std_logic; + PULSE_OUT : out std_logic + ); + end component; + + component nx_fpga_timestamp + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; + TIMESTAMP_RESET_IN : in std_logic; + TIMESTAMP_RESET_OUT : out std_logic; + TRIGGER_IN : in std_logic; + TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); + TIMESTAMP_TRIGGER_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_trigger_handler + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; + NXYTER_OFFLINE_IN : in std_logic; + TIMING_TRIGGER_IN : in std_logic; + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; + LVL1_INVALID_TRG_IN : in std_logic; + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + FEE_DATA_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_WRITE_OUT : out std_logic; + FEE_DATA_FINISHED_OUT : out std_logic; + FEE_TRG_RELEASE_OUT : out std_logic; + FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); + FEE_DATA_0_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_0_IN : in std_logic; + FEE_DATA_1_IN : in std_logic_vector(31 downto 0); + FEE_DATA_WRITE_1_IN : in std_logic; + INTERNAL_TRIGGER_IN : in std_logic; + TRIGGER_VALIDATE_BUSY_IN : in std_logic; + TRIGGER_BUSY_0_IN : in std_logic; + TRIGGER_BUSY_1_IN : in std_logic; + VALID_TRIGGER_OUT : out std_logic; + TIMESTAMP_TRIGGER_OUT : out std_logic; + TRIGGER_TIMING_OUT : out std_logic; + TRIGGER_STATUS_OUT : out std_logic; + TRIGGER_CALIBRATION_OUT : out std_logic; + FAST_CLEAR_OUT : out std_logic; + TRIGGER_BUSY_OUT : out std_logic; + NX_TESTPULSE_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + component nx_trigger_generator + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TRIGGER_BUSY_IN : in std_logic; + EXTERNAL_TRIGGER_OUT : out std_logic; + INTERNAL_TRIGGER_OUT : out std_logic; + DATA_IN : in std_logic_vector(43 downto 0); + DATA_CLK_IN : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; ------------------------------------------------------------------------------- -- Misc Tools ------------------------------------------------------------------------------- -component timer - generic ( - CTR_WIDTH : integer range 2 to 32; - STEP_SIZE : integer range 1 to 100 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TIMER_START_IN : in std_logic; - TIMER_END_IN : in unsigned(CTR_WIDTH - 1 downto 0); - TIMER_DONE_OUT : out std_logic - ); -end component; - -component timer_static - generic ( - CTR_WIDTH : integer range 2 to 32; - CTR_END : integer; - STEP_SIZE : integer range 1 to 100 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TIMER_START_IN : in std_logic; - TIMER_BUSY_OUT : out std_logic; - TIMER_DONE_OUT : out std_logic - ); -end component; + component timer + generic ( + CTR_WIDTH : integer range 2 to 32; + STEP_SIZE : integer range 1 to 100 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMER_START_IN : in std_logic; + TIMER_END_IN : in unsigned(CTR_WIDTH - 1 downto 0); + TIMER_DONE_OUT : out std_logic + ); + end component; + + component timer_static + generic ( + CTR_WIDTH : integer range 2 to 32; + CTR_END : integer; + STEP_SIZE : integer range 1 to 100 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMER_START_IN : in std_logic; + TIMER_BUSY_OUT : out std_logic; + TIMER_DONE_OUT : out std_logic + ); + end component; ------------------------------------------------------------------------------- -- Simulations ------------------------------------------------------------------------------- -component nxyter_timestamp_sim - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - TIMESTAMP_OUT : out std_logic_vector(7 downto 0); - CLK128_OUT : out std_logic - ); -end component; - -type debug_array_t is array(integer range <>) of std_logic_vector(15 downto 0); - -component debug_multiplexer - generic ( - NUM_PORTS : integer range 1 to 32 - ); - port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); - DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic - ); -end component; + component nxyter_timestamp_sim + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMESTAMP_OUT : out std_logic_vector(7 downto 0); + CLK128_OUT : out std_logic + ); + end component; + + type debug_array_t is array(integer range <>) + of std_logic_vector(15 downto 0); + + component debug_multiplexer + generic ( + NUM_PORTS : integer range 1 to 32 + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + DEBUG_LINE_IN : in debug_array_t(0 to NUM_PORTS-1); + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); + end component; end package; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index f0da8ca..596733e 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -21,9 +21,7 @@ entity nXyter_FEE_board is CLK_IN : in std_logic; RESET_IN : in std_logic; CLK_NX_MAIN_IN : in std_logic; - CLK_ADC_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; - PLL_ADC_DCLK_LOCK_IN : in std_logic; PLL_RESET_OUT : out std_logic; TRIGGER_OUT : out std_logic; @@ -46,13 +44,13 @@ entity nXyter_FEE_board is NX_TIMESTAMP_TRIGGER_OUT : out std_logic; -- ADC nXyter Pulse Hight Ports - ADC_FCLK_IN : in std_logic_vector(1 downto 0); - ADC_DCLK_IN : in std_logic_vector(1 downto 0); ADC_SAMPLE_CLK_OUT : out std_logic; - ADC_A_IN : in std_logic_vector(1 downto 0); - ADC_B_IN : in std_logic_vector(1 downto 0); - ADC_NX_IN : in std_logic_vector(1 downto 0); - ADC_D_IN : in std_logic_vector(1 downto 0); + ADC_FCLK_IN : in std_logic; + ADC_DCLK_IN : in std_logic; + ADC_A_IN : in std_logic; + ADC_B_IN : in std_logic; + ADC_NX_IN : in std_logic; + ADC_D_IN : in std_logic; -- Input Triggers TIMING_TRIGGER_IN : in std_logic; @@ -320,7 +318,7 @@ begin RESET_IN => RESET_IN, PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN, - PLL_ADC_DCLK_LOCK_IN => PLL_ADC_DCLK_LOCK_IN, + PLL_ADC_DCLK_LOCK_IN => '1', PLL_ADC_SCLK_LOCK_IN => pll_sadc_clk_lock, PLL_RESET_OUT => PLL_RESET_OUT, @@ -565,16 +563,16 @@ begin NX_DATA_CLK_IN => NX_TIMESTAMP_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset, + + ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT, + ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock, - ADC_CLK_DAT_IN => CLK_ADC_IN, ADC_FCLK_IN => ADC_FCLK_IN, ADC_DCLK_IN => ADC_DCLK_IN, - ADC_SAMPLE_CLK_OUT => ADC_SAMPLE_CLK_OUT, ADC_A_IN => ADC_A_IN, ADC_B_IN => ADC_B_IN, ADC_NX_IN => ADC_NX_IN, ADC_D_IN => ADC_D_IN, - ADC_SCLK_LOCK_OUT => pll_sadc_clk_lock, DATA_OUT => data_recv, DATA_CLK_OUT => data_clk_recv, @@ -837,8 +835,6 @@ begin SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(11) ); - --DEBUG_LINE_OUT <= (others => '0'); - ------------------------------------------------------------------------------- -- END ------------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph.p2t b/nxyter/trb3_periph.p2t deleted file mode 120000 index c93d3a2..0000000 --- a/nxyter/trb3_periph.p2t +++ /dev/null @@ -1 +0,0 @@ -trb3_periph_multi.p2t \ No newline at end of file diff --git a/nxyter/trb3_periph.p2t_single b/nxyter/trb3_periph.p2t_single deleted file mode 100644 index 2968146..0000000 --- a/nxyter/trb3_periph.p2t_single +++ /dev/null @@ -1,20 +0,0 @@ --w --i 15 --l 5 --n 1 --y --s 12 --t 69 --c 1 --e 2 --m nodelist.txt -# -w -# -i 6 -# -l 5 -# -n 1 -# -t 1 -# -s 1 -# -c 0 -# -e 0 -# --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: diff --git a/nxyter/trb3_periph.p3t b/nxyter/trb3_periph.p3t deleted file mode 100644 index 2534469..0000000 --- a/nxyter/trb3_periph.p3t +++ /dev/null @@ -1,5 +0,0 @@ --rem --distrce --log "trb3_gbe_trb3_gbe.log" --o "trb3_gbe_trb3_gbe.csv" --pr "trb3_gbe_trb3_gbe.prf" diff --git a/nxyter/trb3_periph.pt b/nxyter/trb3_periph.pt deleted file mode 100644 index b5319a3..0000000 --- a/nxyter/trb3_periph.pt +++ /dev/null @@ -1,10 +0,0 @@ --v -10 - - - - --gt --sethld --sp 8 --sphld m diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd deleted file mode 120000 index f09a079..0000000 --- a/nxyter/trb3_periph.vhd +++ /dev/null @@ -1 +0,0 @@ -trb3_periph_nx1.vhd \ No newline at end of file diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_nxyter.p2t similarity index 100% rename from nxyter/trb3_periph_multi.p2t rename to nxyter/trb3_periph_nxyter.p2t diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph_nxyter.prj similarity index 98% rename from nxyter/trb3_periph.prj rename to nxyter/trb3_periph_nxyter.prj index f88cadf..ddc6a9d 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph_nxyter.prj @@ -12,7 +12,7 @@ set_option -part_companion "" # compilation/mapping options set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3_periph" +set_option -top_module "trb3_periph_nxyter" set_option -resource_sharing true # map options @@ -37,7 +37,7 @@ set_option -write_apr_constraint 0 # set result format/file last project -result_format "edif" -project -result_file "workdir/trb3_periph.edf" +project -result_file "workdir/trb3_periph_nxyter.edf" #implementation attributes @@ -144,7 +144,6 @@ add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" # nXyter Files add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" -add_file -vhdl -lib "work" "cores/pll_adc_clk.vhd" add_file -vhdl -lib "work" "cores/pll_adc_sampling_clk.vhd" add_file -vhdl -lib "work" "cores/fifo_data_stream_44to44_dc.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x40.vhd" @@ -159,7 +158,7 @@ add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" add_file -vhdl -lib "work" "cores/dynamic_shift_register33x64.vhd" add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" -add_file -vhdl -lib "work" "trb3_periph.vhd" +add_file -vhdl -lib "work" "trb3_periph_nxyter.vhd" add_file -vhdl -lib "work" "source/nxyter_components.vhd" add_file -vhdl -lib "work" "source/level_to_pulse.vhd" diff --git a/nxyter/trb3_periph_nxyter.vhd b/nxyter/trb3_periph_nxyter.vhd new file mode 120000 index 0000000..3fa57e5 --- /dev/null +++ b/nxyter/trb3_periph_nxyter.vhd @@ -0,0 +1 @@ +trb3_periph_nxyter_nx1.vhd \ No newline at end of file diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_nxyter_constraints.lpf similarity index 88% rename from nxyter/trb3_periph_constraints.lpf rename to nxyter/trb3_periph_nxyter_constraints.lpf index 4f99e4d..dfd77fa 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_nxyter_constraints.lpf @@ -24,30 +24,22 @@ BLOCK RD_DURING_WR_PATHS ; # | # |----> Johnson 1/4 --> ADC SCLK # -# CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1 -# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1 -# -# CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2 -# (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2 +# ADC_DATA_CLK --> ADC Data Clk -----> FPGA ADC Handler +# DDR (187.5 MHz) + # Speed for the configuration Flash access SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; +FREQUENCY PORT NX1_ADC_DCLK_IN 187.5 MHz; +FREQUENCY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c" 93.750000 MHz; -#USE PRIMARY NET "nx_main_clk_c"; -#USE PRIMARY NET "clk_100_i_c"; -#USE PRIMARY NET "CLK_PCLK_RIGHT_c"; - -FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; - -USE PRIMARY NET "nx_main_clk_c"; -USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; -USE EDGE2EDGE NET "NX_CLK_ADC_DAT"; -USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/DDR_DATA_CLK_c"; +USE PRIMARY NET "clk_100_i_c"; +USE PRIMARY NET "nx_main_clk_c"; +USE PRIMARY NET "nXyter_FEE_board_0/nx_data_receiver_1/DDR_DATA_CLK_c"; ################################################################# # Reset Nets @@ -67,6 +59,10 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLI # Relax some of the timing constraints ################################################################# +#SPI Interface +REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; + ################################################# # Muelleimer: # #LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ; @@ -109,8 +105,6 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_sloppy_frame_c*" 200 ns; - MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns; @@ -126,20 +120,14 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; - MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ; MULTICYCLE TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; MAXDELAY TO GROUP "TEST_LINE_group" 500.000000 ns ; MAXDELAY TO GROUP "NX1_DEBUG_LINE_group" 500.000000 ns ; -#SPI Interface -REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - ################################################################# # Constraints for nxyter inputs ################################################################# @@ -147,15 +135,8 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; # look at .par and .twr.setup file for clocks # IN .mrp you find the semantic errors -# DDR Generic PLL Setup, very important, do never remove! -LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ; - PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN"; - -#UGROUP NXYTER1 BBOX 100 70 - #BLKNAME nXyter_FEE_board_0; -#LOCATE UGROUP NXYTER1 SITE "R2C2D"; diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nxyter_nx1.vhd similarity index 96% rename from nxyter/trb3_periph_nx1.vhd rename to nxyter/trb3_periph_nxyter_nx1.vhd index 4b8e195..9867f99 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nxyter_nx1.vhd @@ -13,7 +13,7 @@ library ecp3; use ecp3.components.all; -entity trb3_periph is +entity trb3_periph_nxyter is port( --Clocks CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA @@ -126,7 +126,7 @@ entity trb3_periph is end entity; -architecture trb3_periph_arch of trb3_periph is +architecture Behavioral of trb3_periph_nxyter is constant NUM_NXYTER : integer := 1; @@ -265,8 +265,6 @@ architecture trb3_periph_arch of trb3_periph is signal nx_pll_clk_lock : std_logic; signal nx_pll_reset : std_logic; - signal NX_CLK_ADC_DAT : std_logic; - signal nx_pll_adc_clk_lock : std_logic; signal nx1_adc_sample_clk : std_logic; -- nXyter 1 Regio Bus @@ -657,9 +655,7 @@ begin CLK_IN => clk_100_i, RESET_IN => reset_i, CLK_NX_MAIN_IN => nx_main_clk, - CLK_ADC_IN => NX_CLK_ADC_DAT, PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock, - PLL_ADC_DCLK_LOCK_IN => nx_pll_adc_clk_lock, PLL_RESET_OUT => nx_pll_reset, TRIGGER_OUT => fee1_trigger, @@ -679,20 +675,14 @@ begin NX_RESET_OUT => NX1_RESET_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT, - - ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN, - ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN, - ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN, - ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN, + ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk, - ADC_A_IN(0) => NX1_ADC_A_IN, - ADC_A_IN(1) => NX1B_ADC_A_IN, - ADC_B_IN(0) => NX1_ADC_B_IN, - ADC_B_IN(1) => NX1B_ADC_B_IN, - ADC_NX_IN(0) => NX1_ADC_NX_IN, - ADC_NX_IN(1) => NX1B_ADC_NX_IN, - ADC_D_IN(0) => NX1_ADC_D_IN, - ADC_D_IN(1) => NX1B_ADC_D_IN, + ADC_FCLK_IN => NX1_ADC_FCLK_IN, + ADC_DCLK_IN => NX1_ADC_DCLK_IN, + ADC_A_IN => NX1_ADC_A_IN, + ADC_B_IN => NX1_ADC_B_IN, + ADC_NX_IN => NX1_ADC_NX_IN, + ADC_D_IN => NX1_ADC_D_IN, TIMING_TRIGGER_IN => TRIGGER_RIGHT, LVL1_TRG_DATA_VALID_IN => trg_data_valid_i, @@ -767,14 +757,4 @@ begin NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk; - -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be - -- based on same ClockSource as nXyter Main Clock) - pll_adc_clk_1: entity work.pll_adc_clk - port map ( - CLK => CLK_PCLK_RIGHT, - RESET => nx_pll_reset, - CLKOP => NX_CLK_ADC_DAT, - LOCK => nx_pll_adc_clk_lock - ); - end architecture; diff --git a/nxyter/trb3_periph_nx2.vhd b/nxyter/trb3_periph_nxyter_nx2.vhd similarity index 99% rename from nxyter/trb3_periph_nx2.vhd rename to nxyter/trb3_periph_nxyter_nx2.vhd index 8c86162..ed4c3a6 100644 --- a/nxyter/trb3_periph_nx2.vhd +++ b/nxyter/trb3_periph_nxyter_nx2.vhd @@ -13,7 +13,7 @@ library ecp3; use ecp3.components.all; -entity trb3_periph is +entity trb3_periph_nxyter is generic ( NUM_NXYTER : integer := 1; ); @@ -161,7 +161,7 @@ entity trb3_periph is end entity; -architecture trb3_periph_arch of trb3_periph is +architecture Behavioral of trb3_periph_nxyter is -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1 attribute ODDRAPPS : string; diff --git a/nxyter/version-major-minor.txt b/nxyter/version-major-minor.txt new file mode 100644 index 0000000..092ce5f --- /dev/null +++ b/nxyter/version-major-minor.txt @@ -0,0 +1 @@ +0200 -- 2.43.0