From 730899e0ffd77c5cce12049e8bb270244bdb8999 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 23 Jun 2020 16:55:30 +0200 Subject: [PATCH] Update trb5sc with new Serdes files --- .gitignore | 3 + cores/pcs.sbx | 2061 ------------------------- cores/serdes_sync_0/serdes_sync_0.lpc | 97 -- cores/serdes_sync_0/serdes_sync_0.vhd | 436 ------ mimosis/trb5sc_mimosis.prj | 17 +- tdc16clk/trb5sc_mdctdc.prj | 18 +- template/config_compile_frankfurt.pl | 2 +- template/trb5sc_template.prj | 17 +- 8 files changed, 47 insertions(+), 2604 deletions(-) delete mode 100644 cores/pcs.sbx delete mode 100644 cores/serdes_sync_0/serdes_sync_0.lpc delete mode 100644 cores/serdes_sync_0/serdes_sync_0.vhd diff --git a/.gitignore b/.gitignore index b23dea2..9f5d28d 100644 --- a/.gitignore +++ b/.gitignore @@ -33,3 +33,6 @@ old config_compile.pl ._Real_._Math_.vhd diamond +cores/serdes_sync_0 +cores/pcs.vhd +archv diff --git a/cores/pcs.sbx b/cores/pcs.sbx deleted file mode 100644 index c6dff14..0000000 --- a/cores/pcs.sbx +++ /dev/null @@ -1,2061 +0,0 @@ - - - - LATTICE - LOCAL - pcs - 1.0 - - - Diamond_Synthesis - synthesis - - ./pcs.vhd - vhdlSource - - - - Diamond_Simulation - simulation - - ./pcs.vhd - vhdlSource - - - - - - - - - serdes_sync_0_cyawstn - serdes_sync_0_cyawstn - - in - - - - serdes_sync_0.cyawstn - - - - - serdes_sync_0_hdinn - serdes_sync_0_hdinn - - in - - - - serdes_sync_0.hdinn - - - - - serdes_sync_0_hdinp - serdes_sync_0_hdinp - - in - - - - serdes_sync_0.hdinp - - - - - serdes_sync_0_hdoutn - serdes_sync_0_hdoutn - - out - - - - serdes_sync_0.hdoutn - - - - - serdes_sync_0_hdoutp - serdes_sync_0_hdoutp - - out - - - - serdes_sync_0.hdoutp - - - - - serdes_sync_0_lsm_status_s - serdes_sync_0_lsm_status_s - - out - - - - serdes_sync_0.lsm_status_s - - - - - serdes_sync_0_pll_lol - serdes_sync_0_pll_lol - - out - - - - serdes_sync_0.pll_lol - - - - - serdes_sync_0_rsl_disable - serdes_sync_0_rsl_disable - - in - - - - serdes_sync_0.rsl_disable - - - - - serdes_sync_0_rsl_rst - serdes_sync_0_rsl_rst - - in - - - - serdes_sync_0.rsl_rst - - - - - serdes_sync_0_rsl_rx_rdy - serdes_sync_0_rsl_rx_rdy - - out - - - - serdes_sync_0.rsl_rx_rdy - - - - - serdes_sync_0_rsl_tx_rdy - serdes_sync_0_rsl_tx_rdy - - out - - - - serdes_sync_0.rsl_tx_rdy - - - - - serdes_sync_0_rst_dual_c - serdes_sync_0_rst_dual_c - - in - - - - serdes_sync_0.rst_dual_c - - - - - serdes_sync_0_rx_cdr_lol_s - serdes_sync_0_rx_cdr_lol_s - - out - - - - serdes_sync_0.rx_cdr_lol_s - - - - - serdes_sync_0_rx_los_low_s - serdes_sync_0_rx_los_low_s - - out - - - - serdes_sync_0.rx_los_low_s - - - - - serdes_sync_0_rx_pclk - serdes_sync_0_rx_pclk - - out - - - - serdes_sync_0.rx_pclk - - - - - serdes_sync_0_rx_pcs_rst_c - serdes_sync_0_rx_pcs_rst_c - - in - - - - serdes_sync_0.rx_pcs_rst_c - - - - - serdes_sync_0_rx_pwrup_c - serdes_sync_0_rx_pwrup_c - - in - - - - serdes_sync_0.rx_pwrup_c - - - - - serdes_sync_0_rx_serdes_rst_c - serdes_sync_0_rx_serdes_rst_c - - in - - - - serdes_sync_0.rx_serdes_rst_c - - - - - serdes_sync_0_sci_en - serdes_sync_0_sci_en - - in - - - - serdes_sync_0.sci_en - - - - - serdes_sync_0_sci_en_dual - serdes_sync_0_sci_en_dual - - in - - - - serdes_sync_0.sci_en_dual - - - - - serdes_sync_0_sci_int - serdes_sync_0_sci_int - - out - - - - serdes_sync_0.sci_int - - - - - serdes_sync_0_sci_rd - serdes_sync_0_sci_rd - - in - - - - serdes_sync_0.sci_rd - - - - - serdes_sync_0_sci_sel - serdes_sync_0_sci_sel - - in - - - - serdes_sync_0.sci_sel - - - - - serdes_sync_0_sci_sel_dual - serdes_sync_0_sci_sel_dual - - in - - - - serdes_sync_0.sci_sel_dual - - - - - serdes_sync_0_sci_wrn - serdes_sync_0_sci_wrn - - in - - - - serdes_sync_0.sci_wrn - - - - - serdes_sync_0_serdes_pdb - serdes_sync_0_serdes_pdb - - in - - - - serdes_sync_0.serdes_pdb - - - - - serdes_sync_0_serdes_rst_dual_c - serdes_sync_0_serdes_rst_dual_c - - in - - - - serdes_sync_0.serdes_rst_dual_c - - - - - serdes_sync_0_signal_detect_c - serdes_sync_0_signal_detect_c - - in - - - - serdes_sync_0.signal_detect_c - - - - - serdes_sync_0_tx_idle_c - serdes_sync_0_tx_idle_c - - in - - - - serdes_sync_0.tx_idle_c - - - - - serdes_sync_0_tx_pclk - serdes_sync_0_tx_pclk - - out - - - - serdes_sync_0.tx_pclk - - - - - serdes_sync_0_tx_pcs_rst_c - serdes_sync_0_tx_pcs_rst_c - - in - - - - serdes_sync_0.tx_pcs_rst_c - - - - - serdes_sync_0_tx_pwrup_c - serdes_sync_0_tx_pwrup_c - - in - - - - serdes_sync_0.tx_pwrup_c - - - - - serdes_sync_0_tx_serdes_rst_c - serdes_sync_0_tx_serdes_rst_c - - in - - - - serdes_sync_0.tx_serdes_rst_c - - - - - serdes_sync_0_rx_cv_err - serdes_sync_0_rx_cv_err - - out - - 0 - 0 - - - - - serdes_sync_0.rx_cv_err - - - - - serdes_sync_0_rx_disp_err - serdes_sync_0_rx_disp_err - - out - - 0 - 0 - - - - - serdes_sync_0.rx_disp_err - - - - - serdes_sync_0_rx_k - serdes_sync_0_rx_k - - out - - 0 - 0 - - - - - serdes_sync_0.rx_k - - - - - serdes_sync_0_rxdata - serdes_sync_0_rxdata - - out - - 7 - 0 - - - - - serdes_sync_0.rxdata - - - - - serdes_sync_0_sci_addr - serdes_sync_0_sci_addr - - in - - 5 - 0 - - - - - serdes_sync_0.sci_addr - - - - - serdes_sync_0_sci_rddata - serdes_sync_0_sci_rddata - - out - - 7 - 0 - - - - - serdes_sync_0.sci_rddata - - - - - serdes_sync_0_sci_wrdata - serdes_sync_0_sci_wrdata - - in - - 7 - 0 - - - - - serdes_sync_0.sci_wrdata - - - - - serdes_sync_0_tx_disp_sel - serdes_sync_0_tx_disp_sel - - in - - 0 - 0 - - - - - serdes_sync_0.tx_disp_sel - - - - - serdes_sync_0_tx_force_disp - serdes_sync_0_tx_force_disp - - in - - 0 - 0 - - - - - serdes_sync_0.tx_force_disp - - - - - serdes_sync_0_tx_k - serdes_sync_0_tx_k - - in - - 0 - 0 - - - - - serdes_sync_0.tx_k - - - - - serdes_sync_0_txdata - serdes_sync_0_txdata - - in - - 7 - 0 - - - - - serdes_sync_0.txdata - - - - - - - LFE5UM-85F-8BG756C - synplify - 2016-06-21.01:49:01 PM - 2018-10-17.11:38:53 AM - 3.10.1.112 - VHDL - - false - false - false - false - false - false - false - false - false - false - false - - - - - - - - LATTICE - LOCAL - pcs - 1.0 - - - serdes_sync_0 - - Lattice Semiconductor Corporation - LEGACY - PCS - 8.2 - - - Diamond_Simulation - simulation - - ./serdes_sync_0/serdes_sync_0_softlogic.v - verilogSource - - - ./serdes_sync_0/serdes_sync_0.vhd - vhdlSource - - - - Diamond_Synthesis - synthesis - - ./serdes_sync_0/serdes_sync_0_softlogic.v - verilogSource - - - ./serdes_sync_0/serdes_sync_0.vhd - vhdlSource - - - - - - Configuration - none - ${sbp_path}/${instance}/generate_core.tcl - CONFIG - - - CreateNGD - none - ${sbp_path}/${instance}/generate_ngd.tcl - CONFIG - - - Generation - none - ${sbp_path}/${instance}/generate_core.tcl - GENERATE - - - - - - - cyawstn - cyawstn - - in - - - - hdinn - hdinn - - in - - - - true - - - - - hdinp - hdinp - - in - - - - true - - - - - hdoutn - hdoutn - - out - - - - true - - - - - hdoutp - hdoutp - - out - - - - true - - - - - lsm_status_s - lsm_status_s - - out - - - - pll_lol - pll_lol - - out - - - - pll_refclki - pll_refclki - - in - - - - rsl_disable - rsl_disable - - in - - - - rsl_rst - rsl_rst - - in - - - - rsl_rx_rdy - rsl_rx_rdy - - out - - - - rsl_tx_rdy - rsl_tx_rdy - - out - - - - rst_dual_c - rst_dual_c - - in - - - - rx_cdr_lol_s - rx_cdr_lol_s - - out - - - - rx_los_low_s - rx_los_low_s - - out - - - - rx_pclk - rx_pclk - - out - - - - rx_pcs_rst_c - rx_pcs_rst_c - - in - - - - rx_pwrup_c - rx_pwrup_c - - in - - - - rx_serdes_rst_c - rx_serdes_rst_c - - in - - - - rxrefclk - rxrefclk - - in - - - - sci_en - sci_en - - in - - - - sci_en_dual - sci_en_dual - - in - - - - sci_int - sci_int - - out - - - - sci_rd - sci_rd - - in - - - - sci_sel - sci_sel - - in - - - - sci_sel_dual - sci_sel_dual - - in - - - - sci_wrn - sci_wrn - - in - - - - serdes_pdb - serdes_pdb - - in - - - - serdes_rst_dual_c - serdes_rst_dual_c - - in - - - - signal_detect_c - signal_detect_c - - in - - - - sli_rst - sli_rst - - in - - - - true - - - - - tx_idle_c - tx_idle_c - - in - - - - tx_pclk - tx_pclk - - out - - - - tx_pcs_rst_c - tx_pcs_rst_c - - in - - - - tx_pwrup_c - tx_pwrup_c - - in - - - - tx_serdes_rst_c - tx_serdes_rst_c - - in - - - - rx_cv_err - rx_cv_err - - out - - 0 - 0 - - - - - rx_disp_err - rx_disp_err - - out - - 0 - 0 - - - - - rx_k - rx_k - - out - - 0 - 0 - - - - - rxdata - rxdata - - out - - 7 - 0 - - - - - sci_addr - sci_addr - - in - - 5 - 0 - - - - - sci_rddata - sci_rddata - - out - - 7 - 0 - - - - - sci_wrdata - sci_wrdata - - in - - 7 - 0 - - - - - tx_disp_sel - tx_disp_sel - - in - - 0 - 0 - - - - - tx_force_disp - tx_force_disp - - in - - 0 - 0 - - - - - tx_k - tx_k - - in - - 0 - 0 - - - - - txdata - txdata - - in - - 7 - 0 - - - - - - - LFE5UM-85F-8BG756C - synplify - 2018-10-17.11:38:53 AM - - false - false - false - false - false - false - false - false - false - false - LPM - PRIMARY - PRIMARY - false - false - - - - Lane0 - DCUCHANNEL - - true - false - DCUCHANNEL - 6 - - - - - - - Family - ecp5um - - - OperatingCondition - COM - - - Package - CABGA756 - - - PartName - LFE5UM-85F-8BG756C - - - PartType - LFE5UM-85F - - - SpeedGrade - 8 - - - Status - P - - - - CoreName - PCS - - - CoreRevision - 8.2 - - - CoreStatus - Demo - - - CoreType - LPM - - - Date - 10/17/2018 - - - ModuleName - serdes_sync_0 - - - ParameterFileVersion - 1.0 - - - SourceFormat - vhdl - - - Time - 11:31:35 - - - VendorName - Lattice Semiconductor Corporation - - - - ;ACHARA - 0 00H - - - ;ACHARB - 0 00H - - - ;ACHARM - 0 00H - - - ;RXMCAENABLE - Disabled - - - CDRLOLACTION - Full Recalibration - - - CDRLOLRANGE - 3 - - - CDR_MAX_RATE - 2 - - - CDR_MULT - 10X - - - CDR_REF_RATE - 200.0000 - - - CH_MODE - Rx and Tx - - - Destination - Synplicity - - - EDIF - 1 - - - Expression - BusA(0 to 7) - - - IO - 0 - - - IO_TYPE - G8B10B - - - LEQ - Disabled - - - LOOPBACK - Disabled - - - LOSPORT - Enabled - - - NUM_CHS - 1 - - - Order - Big Endian [MSB:LSB] - - - PPORT_RX_RDY - Enabled - - - PPORT_TX_RDY - Enabled - - - PROTOCOL - G8B10B - - - PWAIT_RX_RDY - 3000 - - - PWAIT_TX_RDY - 3000 - - - RCSRC - Disabled - - - REFCLK_RATE - 200.0000 - - - RSTSEQSEL - Enabled - - - RX8B10B - Enabled - - - RXCOMMAA - 1100000100 - - - RXCOMMAB - 0011111000 - - - RXCOMMAM - 1111111100 - - - RXCOUPLING - AC - - - RXCTC - Disabled - - - RXCTCBYTEN - 0 00H - - - RXCTCBYTEN1 - 0 00H - - - RXCTCBYTEN2 - 0 00H - - - RXCTCBYTEN3 - 0 00H - - - RXCTCMATCHPATTERN - M4-S4 - - - RXDIFFTERM - 50 ohms - - - RXFIFO_ENABLE - Enabled - - - RXINVPOL - Non-invert - - - RXLDR - Off - - - RXLOSTHRESHOLD - 0 - - - RXLSM - Enabled - - - RXSC - K28P157 - - - RXWA - Barrel Shift - - - RX_DATA_WIDTH - 8/10-Bit - - - RX_FICLK_RATE - 200.0000 - - - RX_LINE_RATE - 2.0000 - - - RX_RATE_DIV - Full Rate - - - SCIPORT - Enabled - - - SOFTLOL - Enabled - - - TX8B10B - Enabled - - - TXAMPLITUDE - 800 - - - TXDEPOST - Disabled - - - TXDEPRE - Disabled - - - TXDIFFTERM - 50 ohms - - - TXFIFO_ENABLE - Enabled - - - TXINVPOL - Non-invert - - - TXLDR - Off - - - TXPLLLOLTHRESHOLD - 1 - - - TXPLLMULT - 10X - - - TX_DATA_WIDTH - 8/10-Bit - - - TX_FICLK_RATE - 200.0000 - - - TX_LINE_RATE - 2.0000 - - - TX_MAX_RATE - 2 - - - TX_RATE_DIV - Full Rate - - - VHDL - 1 - - - Verilog - 0 - - - - serdes_sync_0.pp - pp - - - serdes_sync_0.sym - sym - - - serdes_sync_0.tft - tft - - - serdes_sync_0.txt - pcs_module - - - - - DCUCHANNEL - 1 - - true - false - DCUCHANNEL - - Lane0 - - - - - - - - - serdes_sync_0_cyawstn - serdes_sync_0_cyawstn - - - - - serdes_sync_0_hdinn - serdes_sync_0_hdinn - - - sys_yes - - - - - - - serdes_sync_0_hdinp - serdes_sync_0_hdinp - - - sys_yes - - - - - - - serdes_sync_0_hdoutn - serdes_sync_0_hdoutn - - - sys_yes - - - - - - - serdes_sync_0_hdoutp - serdes_sync_0_hdoutp - - - sys_yes - - - - - - - serdes_sync_0_lsm_status_s - serdes_sync_0_lsm_status_s - - - - - serdes_sync_0_pll_lol - serdes_sync_0_pll_lol - - - - - serdes_sync_0_rsl_disable - serdes_sync_0_rsl_disable - - - - - serdes_sync_0_rsl_rst - serdes_sync_0_rsl_rst - - - - - serdes_sync_0_rsl_rx_rdy - serdes_sync_0_rsl_rx_rdy - - - - - serdes_sync_0_rsl_tx_rdy - serdes_sync_0_rsl_tx_rdy - - - - - serdes_sync_0_rst_dual_c - serdes_sync_0_rst_dual_c - - - - - serdes_sync_0_rx_cdr_lol_s - serdes_sync_0_rx_cdr_lol_s - - - - - serdes_sync_0_rx_los_low_s - serdes_sync_0_rx_los_low_s - - - - - serdes_sync_0_rx_pclk - serdes_sync_0_rx_pclk - - - - - serdes_sync_0_rx_pcs_rst_c - serdes_sync_0_rx_pcs_rst_c - - - - - serdes_sync_0_rx_pwrup_c - serdes_sync_0_rx_pwrup_c - - - - - serdes_sync_0_rx_serdes_rst_c - serdes_sync_0_rx_serdes_rst_c - - - - - serdes_sync_0_sci_en - serdes_sync_0_sci_en - - - - - serdes_sync_0_sci_en_dual - serdes_sync_0_sci_en_dual - - - - - serdes_sync_0_sci_int - serdes_sync_0_sci_int - - - - - serdes_sync_0_sci_rd - serdes_sync_0_sci_rd - - - - - serdes_sync_0_sci_sel - serdes_sync_0_sci_sel - - - - - serdes_sync_0_sci_sel_dual - serdes_sync_0_sci_sel_dual - - - - - serdes_sync_0_sci_wrn - serdes_sync_0_sci_wrn - - - - - serdes_sync_0_serdes_pdb - serdes_sync_0_serdes_pdb - - - - - serdes_sync_0_serdes_rst_dual_c - serdes_sync_0_serdes_rst_dual_c - - - - - serdes_sync_0_signal_detect_c - serdes_sync_0_signal_detect_c - - - - - serdes_sync_0_tx_idle_c - serdes_sync_0_tx_idle_c - - - - - serdes_sync_0_tx_pclk - serdes_sync_0_tx_pclk - - - - - serdes_sync_0_tx_pcs_rst_c - serdes_sync_0_tx_pcs_rst_c - - - - - serdes_sync_0_tx_pwrup_c - serdes_sync_0_tx_pwrup_c - - - - - serdes_sync_0_tx_serdes_rst_c - serdes_sync_0_tx_serdes_rst_c - - - - - serdes_sync_0_rx_cv_err - serdes_sync_0_rx_cv_err - - - - - serdes_sync_0_rx_cv_err[0] - serdes_sync_0_rx_cv_err[0] - - - - - serdes_sync_0_rx_disp_err - serdes_sync_0_rx_disp_err - - - - - serdes_sync_0_rx_disp_err[0] - serdes_sync_0_rx_disp_err[0] - - - - - serdes_sync_0_rx_k - serdes_sync_0_rx_k - - - - - serdes_sync_0_rx_k[0] - serdes_sync_0_rx_k[0] - - - - - serdes_sync_0_rxdata - serdes_sync_0_rxdata - - - - - serdes_sync_0_rxdata[0] - serdes_sync_0_rxdata[0] - - - - - serdes_sync_0_rxdata[1] - serdes_sync_0_rxdata[1] - - - - - serdes_sync_0_rxdata[2] - serdes_sync_0_rxdata[2] - - - - - serdes_sync_0_rxdata[3] - serdes_sync_0_rxdata[3] - - - - - serdes_sync_0_rxdata[4] - serdes_sync_0_rxdata[4] - - - - - serdes_sync_0_rxdata[5] - serdes_sync_0_rxdata[5] - - - - - serdes_sync_0_rxdata[6] - serdes_sync_0_rxdata[6] - - - - - serdes_sync_0_rxdata[7] - serdes_sync_0_rxdata[7] - - - - - serdes_sync_0_sci_addr - serdes_sync_0_sci_addr - - - - - serdes_sync_0_sci_addr[0] - serdes_sync_0_sci_addr[0] - - - - - serdes_sync_0_sci_addr[1] - serdes_sync_0_sci_addr[1] - - - - - serdes_sync_0_sci_addr[2] - serdes_sync_0_sci_addr[2] - - - - - serdes_sync_0_sci_addr[3] - serdes_sync_0_sci_addr[3] - - - - - serdes_sync_0_sci_addr[4] - serdes_sync_0_sci_addr[4] - - - - - serdes_sync_0_sci_addr[5] - serdes_sync_0_sci_addr[5] - - - - - serdes_sync_0_sci_rddata - serdes_sync_0_sci_rddata - - - - - serdes_sync_0_sci_rddata[0] - serdes_sync_0_sci_rddata[0] - - - - - serdes_sync_0_sci_rddata[1] - serdes_sync_0_sci_rddata[1] - - - - - serdes_sync_0_sci_rddata[2] - serdes_sync_0_sci_rddata[2] - - - - - serdes_sync_0_sci_rddata[3] - serdes_sync_0_sci_rddata[3] - - - - - serdes_sync_0_sci_rddata[4] - serdes_sync_0_sci_rddata[4] - - - - - serdes_sync_0_sci_rddata[5] - serdes_sync_0_sci_rddata[5] - - - - - serdes_sync_0_sci_rddata[6] - serdes_sync_0_sci_rddata[6] - - - - - serdes_sync_0_sci_rddata[7] - serdes_sync_0_sci_rddata[7] - - - - - serdes_sync_0_sci_wrdata - serdes_sync_0_sci_wrdata - - - - - serdes_sync_0_sci_wrdata[0] - serdes_sync_0_sci_wrdata[0] - - - - - serdes_sync_0_sci_wrdata[1] - serdes_sync_0_sci_wrdata[1] - - - - - serdes_sync_0_sci_wrdata[2] - serdes_sync_0_sci_wrdata[2] - - - - - serdes_sync_0_sci_wrdata[3] - serdes_sync_0_sci_wrdata[3] - - - - - serdes_sync_0_sci_wrdata[4] - serdes_sync_0_sci_wrdata[4] - - - - - serdes_sync_0_sci_wrdata[5] - serdes_sync_0_sci_wrdata[5] - - - - - serdes_sync_0_sci_wrdata[6] - serdes_sync_0_sci_wrdata[6] - - - - - serdes_sync_0_sci_wrdata[7] - serdes_sync_0_sci_wrdata[7] - - - - - serdes_sync_0_tx_disp_sel - serdes_sync_0_tx_disp_sel - - - - - serdes_sync_0_tx_disp_sel[0] - serdes_sync_0_tx_disp_sel[0] - - - - - serdes_sync_0_tx_force_disp - serdes_sync_0_tx_force_disp - - - - - serdes_sync_0_tx_force_disp[0] - serdes_sync_0_tx_force_disp[0] - - - - - serdes_sync_0_tx_k - serdes_sync_0_tx_k - - - - - serdes_sync_0_tx_k[0] - serdes_sync_0_tx_k[0] - - - - - serdes_sync_0_txdata - serdes_sync_0_txdata - - - - - serdes_sync_0_txdata[0] - serdes_sync_0_txdata[0] - - - - - serdes_sync_0_txdata[1] - serdes_sync_0_txdata[1] - - - - - serdes_sync_0_txdata[2] - serdes_sync_0_txdata[2] - - - - - serdes_sync_0_txdata[3] - serdes_sync_0_txdata[3] - - - - - serdes_sync_0_txdata[4] - serdes_sync_0_txdata[4] - - - - - serdes_sync_0_txdata[5] - serdes_sync_0_txdata[5] - - - - - serdes_sync_0_txdata[6] - serdes_sync_0_txdata[6] - - - - - serdes_sync_0_txdata[7] - serdes_sync_0_txdata[7] - - - - - - diff --git a/cores/serdes_sync_0/serdes_sync_0.lpc b/cores/serdes_sync_0/serdes_sync_0.lpc deleted file mode 100644 index 807bce9..0000000 --- a/cores/serdes_sync_0/serdes_sync_0.lpc +++ /dev/null @@ -1,97 +0,0 @@ -[Device] -Family=ecp5um -OperatingCondition=COM -Package=CABGA756 -PartName=LFE5UM-85F-8BG756C -PartType=LFE5UM-85F -SpeedGrade=8 -Status=P -[IP] -CoreName=PCS -CoreRevision=8.2 -CoreStatus=Demo -CoreType=LPM -Date=10/17/2018 -ModuleName=serdes_sync_0 -ParameterFileVersion=1.0 -SourceFormat=vhdl -Time=11:31:35 -VendorName=Lattice Semiconductor Corporation -[Parameters] -;ACHARA=0 00H -;ACHARB=0 00H -;ACHARM=0 00H -;RXMCAENABLE=Disabled -CDRLOLACTION=Full Recalibration -CDRLOLRANGE=3 -CDR_MAX_RATE=2 -CDR_MULT=10X -CDR_REF_RATE=200.0000 -CH_MODE=Rx and Tx -Destination=Synplicity -EDIF=1 -Expression=BusA(0 to 7) -IO=0 -IO_TYPE=G8B10B -LEQ=Disabled -LOOPBACK=Disabled -LOSPORT=Enabled -NUM_CHS=1 -Order=Big Endian [MSB:LSB] -PPORT_RX_RDY=Enabled -PPORT_TX_RDY=Enabled -PROTOCOL=G8B10B -PWAIT_RX_RDY=3000 -PWAIT_TX_RDY=3000 -RCSRC=Disabled -REFCLK_RATE=200.0000 -RSTSEQSEL=Enabled -RX8B10B=Enabled -RXCOMMAA=1100000100 -RXCOMMAB=0011111000 -RXCOMMAM=1111111100 -RXCOUPLING=AC -RXCTC=Disabled -RXCTCBYTEN=0 00H -RXCTCBYTEN1=0 00H -RXCTCBYTEN2=0 00H -RXCTCBYTEN3=0 00H -RXCTCMATCHPATTERN=M4-S4 -RXDIFFTERM=50 ohms -RXFIFO_ENABLE=Enabled -RXINVPOL=Non-invert -RXLDR=Off -RXLOSTHRESHOLD=0 -RXLSM=Enabled -RXSC=K28P157 -RXWA=Barrel Shift -RX_DATA_WIDTH=8/10-Bit -RX_FICLK_RATE=200.0000 -RX_LINE_RATE=2.0000 -RX_RATE_DIV=Full Rate -SCIPORT=Enabled -SOFTLOL=Enabled -TX8B10B=Enabled -TXAMPLITUDE=800 -TXDEPOST=Disabled -TXDEPRE=Disabled -TXDIFFTERM=50 ohms -TXFIFO_ENABLE=Enabled -TXINVPOL=Non-invert -TXLDR=Off -TXPLLLOLTHRESHOLD=1 -TXPLLMULT=10X -TX_DATA_WIDTH=8/10-Bit -TX_FICLK_RATE=200.0000 -TX_LINE_RATE=2.0000 -TX_MAX_RATE=2 -TX_RATE_DIV=Full Rate -VHDL=1 -Verilog=0 -[FilesGenerated] -serdes_sync_0.pp=pp -serdes_sync_0.sym=sym -serdes_sync_0.tft=tft -serdes_sync_0.txt=pcs_module -[SYSTEMPNR] -LN0=DCU0_CH1 diff --git a/cores/serdes_sync_0/serdes_sync_0.vhd b/cores/serdes_sync_0/serdes_sync_0.vhd deleted file mode 100644 index 2e69f7a..0000000 --- a/cores/serdes_sync_0/serdes_sync_0.vhd +++ /dev/null @@ -1,436 +0,0 @@ - --- --- Verific VHDL Description of module DCUA --- - --- DCUA is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0rsl_core --- - --- serdes_sync_0rsl_core is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0sll_core --- - --- serdes_sync_0sll_core is a black-box. Cannot print a valid VHDL entity description for it - --- --- Verific VHDL Description of module serdes_sync_0 --- - -library ieee ; -use ieee.std_logic_1164.all ; - -library ecp5um ; -use ecp5um.components.all ; - -entity serdes_sync_0 is - port (hdoutp: out std_logic; - hdoutn: out std_logic; - hdinp: in std_logic; - hdinn: in std_logic; - rxrefclk: in std_logic; - rx_pclk: out std_logic; - tx_pclk: out std_logic; - txdata: in std_logic_vector(7 downto 0); - tx_k: in std_logic_vector(0 downto 0); - tx_force_disp: in std_logic_vector(0 downto 0); - tx_disp_sel: in std_logic_vector(0 downto 0); - rxdata: out std_logic_vector(7 downto 0); - rx_k: out std_logic_vector(0 downto 0); - rx_disp_err: out std_logic_vector(0 downto 0); - rx_cv_err: out std_logic_vector(0 downto 0); - tx_idle_c: in std_logic; - signal_detect_c: in std_logic; - rx_los_low_s: out std_logic; - lsm_status_s: out std_logic; - rx_cdr_lol_s: out std_logic; - sli_rst: in std_logic; - tx_pwrup_c: in std_logic; - rx_pwrup_c: in std_logic; - sci_wrdata: in std_logic_vector(7 downto 0); - sci_addr: in std_logic_vector(5 downto 0); - sci_rddata: out std_logic_vector(7 downto 0); - sci_en_dual: in std_logic; - sci_sel_dual: in std_logic; - sci_en: in std_logic; - sci_sel: in std_logic; - sci_rd: in std_logic; - sci_wrn: in std_logic; - sci_int: out std_logic; - cyawstn: in std_logic; - serdes_pdb: in std_logic; - pll_refclki: in std_logic; - rsl_disable: in std_logic; - rsl_rst: in std_logic; - serdes_rst_dual_c: in std_logic; - rst_dual_c: in std_logic; - tx_serdes_rst_c: in std_logic; - tx_pcs_rst_c: in std_logic; - pll_lol: out std_logic; - rsl_tx_rdy: out std_logic; - rx_serdes_rst_c: in std_logic; - rx_pcs_rst_c: in std_logic; - rsl_rx_rdy: out std_logic - ); - -end entity serdes_sync_0; - -architecture v1 of serdes_sync_0 is - component serdes_sync_0rsl_core is - generic (pnum_channels: integer := 1; - pprotocol: string := "G8B10B"; - pserdes_mode: string := "RX AND TX"; - pport_tx_rdy: string := "ENABLED"; - pwait_tx_rdy: integer := 3000; - pport_rx_rdy: string := "ENABLED"; - pwait_rx_rdy: integer := 3000); - port (rui_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(132) - rui_serdes_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(133) - rui_rst_dual_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(134) - rui_rsl_disable: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(135) - rui_tx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(137) - rui_tx_serdes_rst_c: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(138) - rui_tx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(139) - rdi_pll_lol: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(140) - rui_rx_ref_clk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(142) - rui_rx_serdes_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(143) - rui_rx_pcs_rst_c: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(144) - rdi_rx_los_low_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(145) - rdi_rx_cdr_lol_s: in std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(146) - rdo_serdes_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(149) - rdo_rst_dual_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(150) - ruo_tx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(152) - rdo_tx_serdes_rst_c: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(153) - rdo_tx_pcs_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(154) - ruo_rx_rdy: out std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(156) - rdo_rx_serdes_rst_c: out std_logic_vector(3 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(157) - rdo_rx_pcs_rst_c: out std_logic_vector(3 downto 0) -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(158) - ); - - end component serdes_sync_0rsl_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/rsl_core_syn.v(88) - component serdes_sync_0sll_core is - generic (PPROTOCOL: string := "G8B10B"; - PLOL_SETTING: integer := 1; - PDYN_RATE_CTRL: string := "DISABLED"; - PPCIE_MAX_RATE: string := "2.5"; - PDIFF_VAL_LOCK: integer := 19; - PDIFF_VAL_UNLOCK: integer := 131; - PPCLK_TC: integer := 65536; - PDIFF_DIV11_VAL_LOCK: integer := 0; - PDIFF_DIV11_VAL_UNLOCK: integer := 0; - PPCLK_DIV11_TC: integer := 0); - port (sli_rst: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(125) - sli_refclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(126) - sli_pclk: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(127) - sli_div2_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(128) - sli_div11_rate: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(129) - sli_gear_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(130) - sli_cpri_mode: in std_logic_vector(2 downto 0); -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(131) - sli_pcie_mode: in std_logic; -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(132) - slo_plol: out std_logic -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(135) - ); - - end component serdes_sync_0sll_core; -- syn_black_box=1 -- /d/jspc29/lattice/diamond/3.10_x64/ispfpga/sa5p00/data/sll_core_template.v(107) - signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9, - n10,n11,n12,rx_los_low_s_c,n13,n14,n15,n16,rx_cdr_lol_s_c,n17, - n18,rsl_tx_pcs_rst_c,rsl_rx_pcs_rst_c,rsl_rx_serdes_rst_c,rsl_rst_dual_c, - rsl_serdes_rst_dual_c,rsl_tx_serdes_rst_c,n19,n20,n21,n22,n23, - n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37, - n38,n39,n40,n41,n42,n43,n44,n45,n46,n49,n106,n105,n50,n51, - n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65, - n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79, - n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93, - n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n115,n114, - n113,pll_lol_c,n125,n124,n116,n117,n118,n119,n120,n121,n122, - n123,\_Z\,n127,n126,gnd,pwr : std_logic; - attribute LOC : string; - attribute LOC of DCU0_inst : label is "DCU0"; - attribute CHAN : string; - attribute CHAN of DCU0_inst : label is "CH1"; -begin - rx_pclk <= rx_pclk_c; - tx_pclk <= tx_pclk_c; - rx_los_low_s <= rx_los_low_s_c; - rx_cdr_lol_s <= rx_cdr_lol_s_c; - pll_lol <= pll_lol_c; - DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1", - D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0", - D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1", - D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1", - D_SYNC_ND_EN=>"0b0",CH1_UC_MODE=>"0b1",CH1_PCIE_MODE=>"0b0",CH1_RIO_MODE=>"0b0", - CH1_WA_MODE=>"0b0",CH1_INVERT_RX=>"0b0",CH1_INVERT_TX=>"0b0",CH1_PRBS_SELECTION=>"0b0", - CH1_GE_AN_ENABLE=>"0b0",CH1_PRBS_LOCK=>"0b0",CH1_PRBS_ENABLE=>"0b0", - CH1_ENABLE_CG_ALIGN=>"0b1",CH1_TX_GEAR_MODE=>"0b0",CH1_RX_GEAR_MODE=>"0b0", - CH1_PCS_DET_TIME_SEL=>"0b00",CH1_PCIE_EI_EN=>"0b0",CH1_TX_GEAR_BYPASS=>"0b0", - CH1_ENC_BYPASS=>"0b0",CH1_SB_BYPASS=>"0b0",CH1_RX_SB_BYPASS=>"0b0", - CH1_WA_BYPASS=>"0b0",CH1_DEC_BYPASS=>"0b0",CH1_CTC_BYPASS=>"0b1", - CH1_RX_GEAR_BYPASS=>"0b0",CH1_LSM_DISABLE=>"0b0",CH1_MATCH_2_ENABLE=>"0b0", - CH1_MATCH_4_ENABLE=>"0b1",CH1_MIN_IPG_CNT=>"0b11",CH1_CC_MATCH_1=>"0x1BC", - CH1_CC_MATCH_2=>"0x11C",CH1_CC_MATCH_3=>"0x11C",CH1_CC_MATCH_4=>"0x11C", - CH1_UDF_COMMA_MASK=>"0x0ff",CH1_UDF_COMMA_A=>"0x083",CH1_UDF_COMMA_B=>"0x07C", - CH1_RX_DCO_CK_DIV=>"0b000",CH1_RCV_DCC_EN=>"0b0",CH1_TPWDNB=>"0b1", - CH1_RATE_MODE_TX=>"0b0",CH1_RTERM_TX=>"0d19",CH1_TX_CM_SEL=>"0b00", - CH1_TDRV_PRE_EN=>"0b0",CH1_TDRV_SLICE0_SEL=>"0b00",CH1_TDRV_SLICE1_SEL=>"0b00", - CH1_TDRV_SLICE2_SEL=>"0b01",CH1_TDRV_SLICE3_SEL=>"0b01",CH1_TDRV_SLICE4_SEL=>"0b01", - CH1_TDRV_SLICE5_SEL=>"0b00",CH1_TDRV_SLICE0_CUR=>"0b000",CH1_TDRV_SLICE1_CUR=>"0b000", - CH1_TDRV_SLICE2_CUR=>"0b11",CH1_TDRV_SLICE3_CUR=>"0b11",CH1_TDRV_SLICE4_CUR=>"0b01", - CH1_TDRV_SLICE5_CUR=>"0b00",CH1_TDRV_DAT_SEL=>"0b00",CH1_TX_DIV11_SEL=>"0b0", - CH1_RPWDNB=>"0b1",CH1_RATE_MODE_RX=>"0b0",CH1_RX_DIV11_SEL=>"0b0", - CH1_SEL_SD_RX_CLK=>"0b1",CH1_FF_RX_H_CLK_EN=>"0b0",CH1_FF_RX_F_CLK_DIS=>"0b0", - CH1_FF_TX_H_CLK_EN=>"0b0",CH1_FF_TX_F_CLK_DIS=>"0b0",CH1_TDRV_POST_EN=>"0b0", - CH1_TX_POST_SIGN=>"0b0",CH1_TX_PRE_SIGN=>"0b0",CH1_REQ_LVL_SET=>"0b00", - CH1_REQ_EN=>"0b0",CH1_RTERM_RX=>"0d22",CH1_RXTERM_CM=>"0b11",CH1_PDEN_SEL=>"0b1", - CH1_RXIN_CM=>"0b11",CH1_LEQ_OFFSET_SEL=>"0b0",CH1_LEQ_OFFSET_TRIM=>"0b000", - CH1_RLOS_SEL=>"0b1",CH1_RX_LOS_LVL=>"0b000",CH1_RX_LOS_CEQ=>"0b11", - CH1_RX_LOS_HYST_EN=>"0b0",CH1_RX_LOS_EN=>"0b1",CH1_LDR_RX2CORE_SEL=>"0b0", - CH1_LDR_CORE2TX_SEL=>"0b0",D_TX_MAX_RATE=>"2",CH1_CDR_MAX_RATE=>"2", - CH1_TXAMPLITUDE=>"0d800",CH1_TXDEPRE=>"DISABLED",CH1_TXDEPOST=>"DISABLED", - CH1_PROTOCOL=>"G8B10B",D_ISETLOS=>"0d0",D_SETIRPOLY_AUX=>"0b10",D_SETICONST_AUX=>"0b01", - D_SETIRPOLY_CH=>"0b10",D_SETICONST_CH=>"0b10",D_REQ_ISET=>"0b001", - D_PD_ISET=>"0b00",D_DCO_CALIB_TIME_SEL=>"0b00",CH1_CDR_CNT4SEL=>"0b00", - CH1_CDR_CNT8SEL=>"0b00",CH1_DCOATDCFG=>"0b00",CH1_DCOATDDLY=>"0b00", - CH1_DCOBYPSATD=>"0b1",CH1_DCOCALDIV=>"0b000",CH1_DCOCTLGI=>"0b011", - CH1_DCODISBDAVOID=>"0b0",CH1_DCOFLTDAC=>"0b00",CH1_DCOFTNRG=>"0b001", - CH1_DCOIOSTUNE=>"0b010",CH1_DCOITUNE=>"0b00",CH1_DCOITUNE4LSB=>"0b010", - CH1_DCOIUPDNX2=>"0b1",CH1_DCONUOFLSB=>"0b100",CH1_DCOSCALEI=>"0b01", - CH1_DCOSTARTVAL=>"0b010",CH1_DCOSTEP=>"0b11",CH1_BAND_THRESHOLD=>"0d0", - CH1_AUTO_FACQ_EN=>"0b1",CH1_AUTO_CALIB_EN=>"0b1",CH1_CALIB_CK_MODE=>"0b0", - CH1_REG_BAND_OFFSET=>"0d0",CH1_REG_BAND_SEL=>"0d0",CH1_REG_IDAC_SEL=>"0d0", - CH1_REG_IDAC_EN=>"0b0",D_CMUSETISCL4VCO=>"0b000",D_CMUSETI4VCO=>"0b00", - D_CMUSETINITVCT=>"0b00",D_CMUSETZGM=>"0b000",D_CMUSETP2AGM=>"0b000", - D_CMUSETP1GM=>"0b000",D_CMUSETI4CPZ=>"0d3",D_CMUSETI4CPP=>"0d3",D_CMUSETICP4Z=>"0b101", - D_CMUSETICP4P=>"0b01",D_CMUSETBIASI=>"0b00",D_SETPLLRC=>"0d1",CH1_RX_RATE_SEL=>"0d10", - D_REFCK_MODE=>"0b001",D_TX_VCO_CK_DIV=>"0b000",D_PLL_LOL_SET=>"0b01", - D_RG_EN=>"0b0",D_RG_SET=>"0b00") - port map (CH0_HDINP=>n106,CH1_HDINP=>hdinp,CH0_HDINN=>n106,CH1_HDINN=>hdinn, - D_TXBIT_CLKP_FROM_ND=>n47,D_TXBIT_CLKN_FROM_ND=>n47,D_SYNC_ND=>n47,D_TXPLL_LOL_FROM_ND=>n47, - CH0_RX_REFCLK=>n106,CH1_RX_REFCLK=>rxrefclk,CH0_FF_RXI_CLK=>n105,CH1_FF_RXI_CLK=>rx_pclk_c, - CH0_FF_TXI_CLK=>n105,CH1_FF_TXI_CLK=>tx_pclk_c,CH0_FF_EBRD_CLK=>n105, - CH1_FF_EBRD_CLK=>n48,CH0_FF_TX_D_0=>n106,CH1_FF_TX_D_0=>txdata(0),CH0_FF_TX_D_1=>n106, - CH1_FF_TX_D_1=>txdata(1),CH0_FF_TX_D_2=>n106,CH1_FF_TX_D_2=>txdata(2), - CH0_FF_TX_D_3=>n106,CH1_FF_TX_D_3=>txdata(3),CH0_FF_TX_D_4=>n106,CH1_FF_TX_D_4=>txdata(4), - CH0_FF_TX_D_5=>n106,CH1_FF_TX_D_5=>txdata(5),CH0_FF_TX_D_6=>n106,CH1_FF_TX_D_6=>txdata(6), - CH0_FF_TX_D_7=>n106,CH1_FF_TX_D_7=>txdata(7),CH0_FF_TX_D_8=>n106,CH1_FF_TX_D_8=>tx_k(0), - CH0_FF_TX_D_9=>n106,CH1_FF_TX_D_9=>tx_force_disp(0),CH0_FF_TX_D_10=>n106, - CH1_FF_TX_D_10=>tx_disp_sel(0),CH0_FF_TX_D_11=>n106,CH1_FF_TX_D_11=>n47, - CH0_FF_TX_D_12=>n106,CH1_FF_TX_D_12=>n106,CH0_FF_TX_D_13=>n106,CH1_FF_TX_D_13=>n106, - CH0_FF_TX_D_14=>n106,CH1_FF_TX_D_14=>n106,CH0_FF_TX_D_15=>n106,CH1_FF_TX_D_15=>n106, - CH0_FF_TX_D_16=>n106,CH1_FF_TX_D_16=>n106,CH0_FF_TX_D_17=>n106,CH1_FF_TX_D_17=>n106, - CH0_FF_TX_D_18=>n106,CH1_FF_TX_D_18=>n106,CH0_FF_TX_D_19=>n106,CH1_FF_TX_D_19=>n106, - CH0_FF_TX_D_20=>n106,CH1_FF_TX_D_20=>n106,CH0_FF_TX_D_21=>n106,CH1_FF_TX_D_21=>n106, - CH0_FF_TX_D_22=>n106,CH1_FF_TX_D_22=>n106,CH0_FF_TX_D_23=>n106,CH1_FF_TX_D_23=>n47, - CH0_FFC_EI_EN=>n106,CH1_FFC_EI_EN=>tx_idle_c,CH0_FFC_PCIE_DET_EN=>n106, - CH1_FFC_PCIE_DET_EN=>n47,CH0_FFC_PCIE_CT=>n106,CH1_FFC_PCIE_CT=>n47,CH0_FFC_SB_INV_RX=>n106, - CH1_FFC_SB_INV_RX=>n106,CH0_FFC_ENABLE_CGALIGN=>n106,CH1_FFC_ENABLE_CGALIGN=>n106, - CH0_FFC_SIGNAL_DETECT=>n106,CH1_FFC_SIGNAL_DETECT=>signal_detect_c,CH0_FFC_FB_LOOPBACK=>n106, - CH1_FFC_FB_LOOPBACK=>n47,CH0_FFC_SB_PFIFO_LP=>n106,CH1_FFC_SB_PFIFO_LP=>n47, - CH0_FFC_PFIFO_CLR=>n106,CH1_FFC_PFIFO_CLR=>n47,CH0_FFC_RATE_MODE_RX=>n106, - CH1_FFC_RATE_MODE_RX=>n106,CH0_FFC_RATE_MODE_TX=>n106,CH1_FFC_RATE_MODE_TX=>n106, - CH0_FFC_DIV11_MODE_RX=>n106,CH1_FFC_DIV11_MODE_RX=>n47,CH0_FFC_DIV11_MODE_TX=>n106, - CH1_FFC_DIV11_MODE_TX=>n47,CH0_FFC_RX_GEAR_MODE=>n106,CH1_FFC_RX_GEAR_MODE=>n47, - CH0_FFC_TX_GEAR_MODE=>n106,CH1_FFC_TX_GEAR_MODE=>n47,CH0_FFC_LDR_CORE2TX_EN=>n106, - CH1_FFC_LDR_CORE2TX_EN=>n106,CH0_FFC_LANE_TX_RST=>n106,CH1_FFC_LANE_TX_RST=>rsl_tx_pcs_rst_c, - CH0_FFC_LANE_RX_RST=>n106,CH1_FFC_LANE_RX_RST=>rsl_rx_pcs_rst_c,CH0_FFC_RRST=>n106, - CH1_FFC_RRST=>rsl_rx_serdes_rst_c,CH0_FFC_TXPWDNB=>n106,CH1_FFC_TXPWDNB=>tx_pwrup_c, - CH0_FFC_RXPWDNB=>n106,CH1_FFC_RXPWDNB=>rx_pwrup_c,CH0_LDR_CORE2TX=>n106, - CH1_LDR_CORE2TX=>n106,D_SCIWDATA0=>sci_wrdata(0),D_SCIWDATA1=>sci_wrdata(1), - D_SCIWDATA2=>sci_wrdata(2),D_SCIWDATA3=>sci_wrdata(3),D_SCIWDATA4=>sci_wrdata(4), - D_SCIWDATA5=>sci_wrdata(5),D_SCIWDATA6=>sci_wrdata(6),D_SCIWDATA7=>sci_wrdata(7), - D_SCIADDR0=>sci_addr(0),D_SCIADDR1=>sci_addr(1),D_SCIADDR2=>sci_addr(2), - D_SCIADDR3=>sci_addr(3),D_SCIADDR4=>sci_addr(4),D_SCIADDR5=>sci_addr(5), - D_SCIENAUX=>sci_en_dual,D_SCISELAUX=>sci_sel_dual,CH0_SCIEN=>n106,CH1_SCIEN=>sci_en, - CH0_SCISEL=>n106,CH1_SCISEL=>sci_sel,D_SCIRD=>sci_rd,D_SCIWSTN=>sci_wrn, - D_CYAWSTN=>cyawstn,D_FFC_SYNC_TOGGLE=>n106,D_FFC_DUAL_RST=>rsl_rst_dual_c, - D_FFC_MACRO_RST=>rsl_serdes_rst_dual_c,D_FFC_MACROPDB=>serdes_pdb,D_FFC_TRST=>rsl_tx_serdes_rst_c, - CH0_FFC_CDR_EN_BITSLIP=>n106,CH1_FFC_CDR_EN_BITSLIP=>n47,D_SCAN_ENABLE=>n47, - D_SCAN_IN_0=>n47,D_SCAN_IN_1=>n47,D_SCAN_IN_2=>n47,D_SCAN_IN_3=>n47, - D_SCAN_IN_4=>n47,D_SCAN_IN_5=>n47,D_SCAN_IN_6=>n47,D_SCAN_IN_7=>n47, - D_SCAN_MODE=>n47,D_SCAN_RESET=>n47,D_CIN0=>n47,D_CIN1=>n47,D_CIN2=>n47, - D_CIN3=>n47,D_CIN4=>n47,D_CIN5=>n47,D_CIN6=>n47,D_CIN7=>n47,D_CIN8=>n47, - D_CIN9=>n47,D_CIN10=>n47,D_CIN11=>n47,CH0_HDOUTP=>n50,CH1_HDOUTP=>hdoutp, - CH0_HDOUTN=>n51,CH1_HDOUTN=>hdoutn,D_TXBIT_CLKP_TO_ND=>n1,D_TXBIT_CLKN_TO_ND=>n2, - D_SYNC_PULSE2ND=>n3,D_TXPLL_LOL_TO_ND=>n4,CH0_FF_RX_F_CLK=>n52,CH1_FF_RX_F_CLK=>n5, - CH0_FF_RX_H_CLK=>n53,CH1_FF_RX_H_CLK=>n6,CH0_FF_TX_F_CLK=>n54,CH1_FF_TX_F_CLK=>n7, - CH0_FF_TX_H_CLK=>n55,CH1_FF_TX_H_CLK=>n8,CH0_FF_RX_PCLK=>n56,CH1_FF_RX_PCLK=>rx_pclk_c, - CH0_FF_TX_PCLK=>n57,CH1_FF_TX_PCLK=>tx_pclk_c,CH0_FF_RX_D_0=>n58,CH1_FF_RX_D_0=>rxdata(0), - CH0_FF_RX_D_1=>n59,CH1_FF_RX_D_1=>rxdata(1),CH0_FF_RX_D_2=>n60,CH1_FF_RX_D_2=>rxdata(2), - CH0_FF_RX_D_3=>n61,CH1_FF_RX_D_3=>rxdata(3),CH0_FF_RX_D_4=>n62,CH1_FF_RX_D_4=>rxdata(4), - CH0_FF_RX_D_5=>n63,CH1_FF_RX_D_5=>rxdata(5),CH0_FF_RX_D_6=>n64,CH1_FF_RX_D_6=>rxdata(6), - CH0_FF_RX_D_7=>n65,CH1_FF_RX_D_7=>rxdata(7),CH0_FF_RX_D_8=>n66,CH1_FF_RX_D_8=>rx_k(0), - CH0_FF_RX_D_9=>n67,CH1_FF_RX_D_9=>rx_disp_err(0),CH0_FF_RX_D_10=>n68, - CH1_FF_RX_D_10=>rx_cv_err(0),CH0_FF_RX_D_11=>n69,CH1_FF_RX_D_11=>n9,CH0_FF_RX_D_12=>n70, - CH1_FF_RX_D_12=>n71,CH0_FF_RX_D_13=>n72,CH1_FF_RX_D_13=>n73,CH0_FF_RX_D_14=>n74, - CH1_FF_RX_D_14=>n75,CH0_FF_RX_D_15=>n76,CH1_FF_RX_D_15=>n77,CH0_FF_RX_D_16=>n78, - CH1_FF_RX_D_16=>n79,CH0_FF_RX_D_17=>n80,CH1_FF_RX_D_17=>n81,CH0_FF_RX_D_18=>n82, - CH1_FF_RX_D_18=>n83,CH0_FF_RX_D_19=>n84,CH1_FF_RX_D_19=>n85,CH0_FF_RX_D_20=>n86, - CH1_FF_RX_D_20=>n87,CH0_FF_RX_D_21=>n88,CH1_FF_RX_D_21=>n89,CH0_FF_RX_D_22=>n90, - CH1_FF_RX_D_22=>n91,CH0_FF_RX_D_23=>n92,CH1_FF_RX_D_23=>n10,CH0_FFS_PCIE_DONE=>n93, - CH1_FFS_PCIE_DONE=>n11,CH0_FFS_PCIE_CON=>n94,CH1_FFS_PCIE_CON=>n12,CH0_FFS_RLOS=>n95, - CH1_FFS_RLOS=>rx_los_low_s_c,CH0_FFS_LS_SYNC_STATUS=>n96,CH1_FFS_LS_SYNC_STATUS=>lsm_status_s, - CH0_FFS_CC_UNDERRUN=>n97,CH1_FFS_CC_UNDERRUN=>n13,CH0_FFS_CC_OVERRUN=>n98, - CH1_FFS_CC_OVERRUN=>n14,CH0_FFS_RXFBFIFO_ERROR=>n99,CH1_FFS_RXFBFIFO_ERROR=>n15, - CH0_FFS_TXFBFIFO_ERROR=>n100,CH1_FFS_TXFBFIFO_ERROR=>n16,CH0_FFS_RLOL=>n101, - CH1_FFS_RLOL=>rx_cdr_lol_s_c,CH0_FFS_SKP_ADDED=>n102,CH1_FFS_SKP_ADDED=>n17, - CH0_FFS_SKP_DELETED=>n103,CH1_FFS_SKP_DELETED=>n18,CH0_LDR_RX2CORE=>n104, - CH1_LDR_RX2CORE=>n115,D_SCIRDATA0=>sci_rddata(0),D_SCIRDATA1=>sci_rddata(1), - D_SCIRDATA2=>sci_rddata(2),D_SCIRDATA3=>sci_rddata(3),D_SCIRDATA4=>sci_rddata(4), - D_SCIRDATA5=>sci_rddata(5),D_SCIRDATA6=>sci_rddata(6),D_SCIRDATA7=>sci_rddata(7), - D_SCIINT=>sci_int,D_SCAN_OUT_0=>n19,D_SCAN_OUT_1=>n20,D_SCAN_OUT_2=>n21, - D_SCAN_OUT_3=>n22,D_SCAN_OUT_4=>n23,D_SCAN_OUT_5=>n24,D_SCAN_OUT_6=>n25, - D_SCAN_OUT_7=>n26,D_COUT0=>n27,D_COUT1=>n28,D_COUT2=>n29,D_COUT3=>n30, - D_COUT4=>n31,D_COUT5=>n32,D_COUT6=>n33,D_COUT7=>n34,D_COUT8=>n35,D_COUT9=>n36, - D_COUT10=>n37,D_COUT11=>n38,D_COUT12=>n39,D_COUT13=>n40,D_COUT14=>n41, - D_COUT15=>n42,D_COUT16=>n43,D_COUT17=>n44,D_COUT18=>n45,D_COUT19=>n46, - D_REFCLKI=>pll_refclki,D_FFS_PLOL=>n49); - n48 <= '1' ; - n47 <= '0' ; - n1 <= 'Z' ; - n2 <= 'Z' ; - n3 <= 'Z' ; - n4 <= 'Z' ; - n5 <= 'Z' ; - n6 <= 'Z' ; - n7 <= 'Z' ; - n8 <= 'Z' ; - n9 <= 'Z' ; - n10 <= 'Z' ; - n11 <= 'Z' ; - n12 <= 'Z' ; - n13 <= 'Z' ; - n14 <= 'Z' ; - n15 <= 'Z' ; - n16 <= 'Z' ; - n17 <= 'Z' ; - n18 <= 'Z' ; - n19 <= 'Z' ; - n20 <= 'Z' ; - n21 <= 'Z' ; - n22 <= 'Z' ; - n23 <= 'Z' ; - n24 <= 'Z' ; - n25 <= 'Z' ; - n26 <= 'Z' ; - n27 <= 'Z' ; - n28 <= 'Z' ; - n29 <= 'Z' ; - n30 <= 'Z' ; - n31 <= 'Z' ; - n32 <= 'Z' ; - n33 <= 'Z' ; - n34 <= 'Z' ; - n35 <= 'Z' ; - n36 <= 'Z' ; - n37 <= 'Z' ; - n38 <= 'Z' ; - n39 <= 'Z' ; - n40 <= 'Z' ; - n41 <= 'Z' ; - n42 <= 'Z' ; - n43 <= 'Z' ; - n44 <= 'Z' ; - n45 <= 'Z' ; - n46 <= 'Z' ; - n49 <= 'Z' ; - n106 <= '0' ; - n105 <= '1' ; - n50 <= 'Z' ; - n51 <= 'Z' ; - n52 <= 'Z' ; - n53 <= 'Z' ; - n54 <= 'Z' ; - n55 <= 'Z' ; - n56 <= 'Z' ; - n57 <= 'Z' ; - n58 <= 'Z' ; - n59 <= 'Z' ; - n60 <= 'Z' ; - n61 <= 'Z' ; - n62 <= 'Z' ; - n63 <= 'Z' ; - n64 <= 'Z' ; - n65 <= 'Z' ; - n66 <= 'Z' ; - n67 <= 'Z' ; - n68 <= 'Z' ; - n69 <= 'Z' ; - n70 <= 'Z' ; - n71 <= 'Z' ; - n72 <= 'Z' ; - n73 <= 'Z' ; - n74 <= 'Z' ; - n75 <= 'Z' ; - n76 <= 'Z' ; - n77 <= 'Z' ; - n78 <= 'Z' ; - n79 <= 'Z' ; - n80 <= 'Z' ; - n81 <= 'Z' ; - n82 <= 'Z' ; - n83 <= 'Z' ; - n84 <= 'Z' ; - n85 <= 'Z' ; - n86 <= 'Z' ; - n87 <= 'Z' ; - n88 <= 'Z' ; - n89 <= 'Z' ; - n90 <= 'Z' ; - n91 <= 'Z' ; - n92 <= 'Z' ; - n93 <= 'Z' ; - n94 <= 'Z' ; - n95 <= 'Z' ; - n96 <= 'Z' ; - n97 <= 'Z' ; - n98 <= 'Z' ; - n99 <= 'Z' ; - n100 <= 'Z' ; - n101 <= 'Z' ; - n102 <= 'Z' ; - n103 <= 'Z' ; - n104 <= 'Z' ; - n115 <= 'Z' ; - rsl_inst: component serdes_sync_0rsl_core port map (rui_rst=>rsl_rst,rui_serdes_rst_dual_c=>serdes_rst_dual_c, - rui_rst_dual_c=>rst_dual_c,rui_rsl_disable=>rsl_disable,rui_tx_ref_clk=>pll_refclki, - rui_tx_serdes_rst_c=>tx_serdes_rst_c,rui_tx_pcs_rst_c(3)=>n125, - rui_tx_pcs_rst_c(2)=>n125,rui_tx_pcs_rst_c(1)=>n125,rui_tx_pcs_rst_c(0)=>tx_pcs_rst_c, - rdi_pll_lol=>pll_lol_c,rui_rx_ref_clk=>rxrefclk,rui_rx_serdes_rst_c(3)=>n125, - rui_rx_serdes_rst_c(2)=>n125,rui_rx_serdes_rst_c(1)=>n125,rui_rx_serdes_rst_c(0)=>rx_serdes_rst_c, - rui_rx_pcs_rst_c(3)=>n125,rui_rx_pcs_rst_c(2)=>n125,rui_rx_pcs_rst_c(1)=>n125, - rui_rx_pcs_rst_c(0)=>rx_pcs_rst_c,rdi_rx_los_low_s(3)=>n125,rdi_rx_los_low_s(2)=>n125, - rdi_rx_los_low_s(1)=>n125,rdi_rx_los_low_s(0)=>rx_los_low_s_c, - rdi_rx_cdr_lol_s(3)=>n125,rdi_rx_cdr_lol_s(2)=>n125,rdi_rx_cdr_lol_s(1)=>n125, - rdi_rx_cdr_lol_s(0)=>rx_cdr_lol_s_c,rdo_serdes_rst_dual_c=>rsl_serdes_rst_dual_c, - rdo_rst_dual_c=>rsl_rst_dual_c,ruo_tx_rdy=>rsl_tx_rdy,rdo_tx_serdes_rst_c=>rsl_tx_serdes_rst_c, - rdo_tx_pcs_rst_c(3)=>n116,rdo_tx_pcs_rst_c(2)=>n117,rdo_tx_pcs_rst_c(1)=>n118, - rdo_tx_pcs_rst_c(0)=>rsl_tx_pcs_rst_c,ruo_rx_rdy=>rsl_rx_rdy,rdo_rx_serdes_rst_c(3)=>n119, - rdo_rx_serdes_rst_c(2)=>n120,rdo_rx_serdes_rst_c(1)=>n121,rdo_rx_serdes_rst_c(0)=>rsl_rx_serdes_rst_c, - rdo_rx_pcs_rst_c(3)=>n122,rdo_rx_pcs_rst_c(2)=>n123,rdo_rx_pcs_rst_c(1)=>\_Z\, - rdo_rx_pcs_rst_c(0)=>rsl_rx_pcs_rst_c); - n114 <= '1' ; - n113 <= '0' ; - n125 <= '0' ; - n124 <= '1' ; - n116 <= 'Z' ; - n117 <= 'Z' ; - n118 <= 'Z' ; - n119 <= 'Z' ; - n120 <= 'Z' ; - n121 <= 'Z' ; - n122 <= 'Z' ; - n123 <= 'Z' ; - \_Z\ <= 'Z' ; - sll_inst: component serdes_sync_0sll_core port map (sli_rst=>sli_rst,sli_refclk=>pll_refclki, - sli_pclk=>tx_pclk_c,sli_div2_rate=>gnd,sli_div11_rate=>gnd,sli_gear_mode=>gnd, - sli_cpri_mode(2)=>gnd,sli_cpri_mode(1)=>gnd,sli_cpri_mode(0)=>gnd, - sli_pcie_mode=>gnd,slo_plol=>pll_lol_c); - n127 <= '1' ; - n126 <= '0' ; - gnd <= '0' ; - pwr <= '1' ; - -end architecture v1; - diff --git a/mimosis/trb5sc_mimosis.prj b/mimosis/trb5sc_mimosis.prj index 6fcd57f..930bce4 100644 --- a/mimosis/trb5sc_mimosis.prj +++ b/mimosis/trb5sc_mimosis.prj @@ -138,11 +138,22 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" #add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" #channel 1, SFP -add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" -add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" ########################################## -add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/tdc16clk/trb5sc_mdctdc.prj b/tdc16clk/trb5sc_mdctdc.prj index 5a5094b..f04d564 100644 --- a/tdc16clk/trb5sc_mdctdc.prj +++ b/tdc16clk/trb5sc_mdctdc.prj @@ -138,11 +138,23 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" #add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" #channel 1, SFP -add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" -add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" ########################################## -add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + + #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index d2e0437..a681cf6 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -11,7 +11,7 @@ lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', nodelist_file => '../nodelist_frankfurt.txt', -pinout_file => 'trb5sc_pqdc', +pinout_file => 'trb5sc_tdc', par_options => '../par.p2t', diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj index ffa8d9a..af55465 100644 --- a/template/trb5sc_template.prj +++ b/template/trb5sc_template.prj @@ -139,11 +139,22 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" #add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" #channel 1, SFP -add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" -add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" ########################################## -add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -- 2.43.0