From 731468fd2a04ed99ce8f4a8d1ae8f3b89f2c3587 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 14 Apr 2010 09:21:51 +0000 Subject: [PATCH] *** empty log message *** --- gbe_ecp2m/slv_mac_memory.vhd | 178 ++++++++++++++++++++++++++++++++++ special/handler_data.vhd | 40 +++++++- trb_net_components.vhd | 179 +++++++++++++++++++++++++++++++++++ 3 files changed, 392 insertions(+), 5 deletions(-) create mode 100644 gbe_ecp2m/slv_mac_memory.vhd diff --git a/gbe_ecp2m/slv_mac_memory.vhd b/gbe_ecp2m/slv_mac_memory.vhd new file mode 100644 index 0000000..bd74e03 --- /dev/null +++ b/gbe_ecp2m/slv_mac_memory.vhd @@ -0,0 +1,178 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +library work; + +entity slv_mac_memory is +port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG +); +end entity; + +architecture Behavioral of slv_mac_memory is + +component ip_mem is +port( + DataInA : in std_logic_vector(31 downto 0); + DataInB : in std_logic_vector(31 downto 0); + AddressA : in std_logic_vector(7 downto 0); + AddressB : in std_logic_vector(7 downto 0); + ClockA : in std_logic; + ClockB : in std_logic; + ClockEnA : in std_logic; + ClockEnB : in std_logic; + WrA : in std_logic; + WrB : in std_logic; + ResetA : in std_logic; + ResetB : in std_logic; + QA : out std_logic_vector(31 downto 0); + QB : out std_logic_vector(31 downto 0) +); +end component ip_mem; + +-- Signals +type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); +signal CURRENT_STATE, NEXT_STATE: STATES; + +-- slave bus signals +signal slv_busy_x : std_logic; +signal slv_busy : std_logic; +signal slv_ack_x : std_logic; +signal slv_ack : std_logic; +signal store_wr_x : std_logic; +signal store_wr : std_logic; +signal store_rd_x : std_logic; +signal store_rd : std_logic; + +signal reg_busy : std_logic; + +begin + +-- Fake +reg_busy <= busy_in; +stat <= (others => '0'); + +--------------------------------------------------------- +-- Statemachine -- +--------------------------------------------------------- +-- State memory process +STATE_MEM: process( clk ) +begin + if( rising_edge(clk) ) then + if( reset = '1' ) then + CURRENT_STATE <= SLEEP; + slv_busy <= '0'; + slv_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + slv_busy <= slv_busy_x; + slv_ack <= slv_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; + end if; +end process STATE_MEM; + +-- Transition matrix +TRANSFORM: process(CURRENT_STATE, slv_read_in, slv_write_in, reg_busy ) +begin + NEXT_STATE <= SLEEP; + slv_busy_x <= '0'; + slv_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => if ( (reg_busy = '0') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (reg_busy = '0') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + elsif( (reg_busy = '1') and (slv_read_in = '1') ) then + NEXT_STATE <= RD_BSY; + elsif( (reg_busy = '1') and (slv_write_in = '1') ) then + NEXT_STATE <= WR_BSY; + else + NEXT_STATE <= SLEEP; + end if; + when RD_RDY => NEXT_STATE <= RD_ACK; + when WR_RDY => NEXT_STATE <= WR_ACK; + when RD_ACK => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + slv_ack_x <= '1'; + end if; + when WR_ACK => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + slv_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + slv_ack_x <= '1'; + end if; + when RD_BSY => if( slv_read_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= RD_BSY; + slv_busy_x <= '1'; + end if; + when WR_BSY => if( slv_write_in = '0' ) then + NEXT_STATE <= DONE; + else + NEXT_STATE <= WR_BSY; + slv_busy_x <= '1'; + end if; + when DONE => NEXT_STATE <= SLEEP; + + when others => NEXT_STATE <= SLEEP; + end case; +end process TRANSFORM; + +--------------------------------------------------------- +-- data handling -- +--------------------------------------------------------- + +THE_MAC_MEM: ip_mem +port map( + DataInA => slv_data_in, + AddressA => slv_addr_in, + ClockA => clk, + ClockEnA => '1', + QA => slv_data_out, + WrA => store_wr, + ResetA => reset, + DataInB => x"0000_0000", + AddressB => mem_addr_in, + ClockB => mem_clk_in, + ClockEnB => '1', + WrB => '0', -- never write + ResetB => reset, + QB => mem_data_out +); + +-- output signals +slv_ack_out <= slv_ack; +slv_busy_out <= slv_busy; + +end Behavioral; diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 1807848..65515c4 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -7,8 +7,6 @@ use work.trb_net_std.all; use work.trb_net_components.all; use work.lattice_ecp2m_fifo.all; - - entity handler_data is generic( DATA_INTERFACE_NUMBER : integer range 1 to 16 := 1; @@ -93,6 +91,8 @@ end entity; architecture handler_data_arch of handler_data is + constant buffer_half_threshold : integer := 2** (DATA_BUFFER_DEPTH-1); + constant buffer_end_threshold : integer := 2**DATA_BUFFER_DEPTH - 2*(2**DATA_BUFFER_DEPTH-DATA_BUFFER_FULL_THRESH); constant data_width : integer := DATA_BUFFER_WIDTH + 4; type buffer_state_t is (IDLE, BUSY, WAITING); type lvl1_state_t is (IDLE, WAIT_BUSY, BUSY_RELEASE); @@ -134,12 +134,17 @@ architecture handler_data_arch of handler_data is signal length_buffer_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); signal length_buffer_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal flag_almost_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal flag_half_full : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0); + signal flag_almost_full_combined : std_logic; + signal flag_half_full_combined : std_logic; + begin assert DATA_BUFFER_FULL_THRESH < 2**DATA_BUFFER_DEPTH-2 report "Data buffer threshold too high" severity error; assert HEADER_BUFFER_FULL_THRESH < 2**HEADER_BUFFER_DEPTH-2 report "Header buffer threshold too high" severity error; - + --------------------------------------------------------------------------- -- FEE & IPU I/O --------------------------------------------------------------------------- @@ -347,12 +352,37 @@ begin end if; end process; +--------------------------------------------------------------------------- +-- Filllevel flags +--------------------------------------------------------------------------- + gen_filllevel_flags : for i in 0 to DATA_INTERFACE_NUMBER-1 generate + proc_filllevel_flag : process(CLOCK) + begin + if rising_edge(CLOCK) then + if data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)) >= buffer_half_threshold then + flag_half_full(i) <= '1'; + else + flag_half_full(i) <= '0'; + end if; + if data_buffer_filllevel(i*(DATA_BUFFER_DEPTH+1)+DATA_BUFFER_DEPTH downto i*(DATA_BUFFER_DEPTH+1)) >= buffer_end_threshold then + flag_almost_full(i) <= '1'; + else + flag_almost_full(i) <= '0'; + end if; + end if; + end process; + end generate; - + flag_half_full_combined <= or_all(flag_half_full); + flag_almost_full_combined <= or_alll(flag_almost_full); + --------------------------------------------------------------------------- -- Generate Statusbits --------------------------------------------------------------------------- - LVL1_STATUSBITS_OUT <= (others => '0'); + LVL1_STATUSBITS_OUT(31 downto 22) <= (others => '0'); + LVL1_STATUSBITS_OUT(21) <= flag_almost_full_combined; + LVL1_STATUSBITS_OUT(20) <= flag_half_full_combined; + LVL1_STATUSBITS_OUT(19 downto 0) <= (others => '0'); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 6f41457..3f7f82e 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -7,6 +7,8 @@ use work.trb_net_std.all; package trb_net_components is + + --This list of components is sorted alphabetically, ignoring the trb_net or trb_net16 prefix of some component names @@ -747,6 +749,159 @@ package trb_net_components is + component trb_net16_gbe_buf is + generic( + DO_SIMULATION : integer range 0 to 1 := 0 + ); + port( + CLK : in std_logic; + TEST_CLK : in std_logic; -- only for simulation! + RESET : in std_logic; + GSR_N : in std_logic; + -- Debug + STAGE_STAT_REGS_OUT : out std_logic_vector(31 downto 0); + STAGE_CTRL_REGS_IN : in std_logic_vector(31 downto 0); + -- configuration interface + IP_CFG_START_IN : in std_logic; + IP_CFG_BANK_SEL_IN : in std_logic_vector(3 downto 0); + IP_CFG_DONE_OUT : out std_logic; + IP_CFG_MEM_ADDR_OUT : out std_logic_vector(7 downto 0); + IP_CFG_MEM_DATA_IN : in std_logic_vector(31 downto 0); + IP_CFG_MEM_CLK_OUT : out std_logic; + MR_RESET_IN : in std_logic; + MR_MODE_IN : in std_logic; + MR_RESTART_IN : in std_logic; + -- gk 29.03.10 + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- CTS interface + CTS_NUMBER_IN : in std_logic_vector(15 downto 0); + CTS_CODE_IN : in std_logic_vector(7 downto 0); + CTS_INFORMATION_IN : in std_logic_vector(7 downto 0); + CTS_READOUT_TYPE_IN : in std_logic_vector(3 downto 0); + CTS_START_READOUT_IN : in std_logic; + CTS_DATA_OUT : out std_logic_vector(31 downto 0); + CTS_DATAREADY_OUT : out std_logic; + CTS_READOUT_FINISHED_OUT : out std_logic; + CTS_READ_IN : in std_logic; + CTS_LENGTH_OUT : out std_logic_vector(15 downto 0); + CTS_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0); + -- Data payload interface + FEE_DATA_IN : in std_logic_vector(15 downto 0); + FEE_DATAREADY_IN : in std_logic; + FEE_READ_OUT : out std_logic; + FEE_STATUS_BITS_IN : in std_logic_vector(31 downto 0); + FEE_BUSY_IN : in std_logic; + --SFP Connection + SFP_RXD_P_IN : in std_logic; + SFP_RXD_N_IN : in std_logic; + SFP_TXD_P_OUT : out std_logic; + SFP_TXD_N_OUT : out std_logic; + SFP_REFCLK_P_IN : in std_logic; + SFP_REFCLK_N_IN : in std_logic; + SFP_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SFP_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SFP_TXDIS_OUT : out std_logic; -- SFP disable + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- PacketConstructor interface + IG_CTS_CTR_TST : out std_logic_vector(2 downto 0); + IG_REM_CTR_TST : out std_logic_vector(3 downto 0); + IG_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + IG_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + IG_DATA_TST : out std_logic_vector(15 downto 0); + IG_WCNT_TST : out std_logic_vector(15 downto 0); + IG_RCNT_TST : out std_logic_vector(16 downto 0); + IG_RD_EN_TST : out std_logic; + IG_WR_EN_TST : out std_logic; + IG_EMPTY_TST : out std_logic; + IG_AEMPTY_TST : out std_logic; + IG_FULL_TST : out std_logic; + IG_AFULL_TST : out std_logic; + PC_WR_EN_TST : out std_logic; + PC_DATA_TST : out std_logic_vector (7 downto 0); + PC_READY_TST : out std_logic; + PC_START_OF_SUB_TST : out std_logic; + PC_END_OF_DATA_TST : out std_logic; + PC_SUB_SIZE_TST : out std_logic_vector(31 downto 0); + PC_TRIG_NR_TST : out std_logic_vector(31 downto 0); + PC_PADDING_TST : out std_logic; + PC_DECODING_TST : out std_logic_vector(31 downto 0); + PC_EVENT_ID_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_DEC_TST : out std_logic_vector(31 downto 0); + PC_BSM_CONSTR_TST : out std_logic_vector(3 downto 0); + PC_BSM_LOAD_TST : out std_logic_vector(3 downto 0); + PC_BSM_SAVE_TST : out std_logic_vector(3 downto 0); + PC_SHF_EMPTY_TST : out std_logic; + PC_SHF_FULL_TST : out std_logic; + PC_DF_EMPTY_TST : out std_logic; + PC_DF_FULL_TST : out std_logic; + PC_ALL_CTR_TST : out std_logic_vector(4 downto 0); + PC_SUB_CTR_TST : out std_logic_vector(4 downto 0); + PC_BYTES_LOADED_TST : out std_logic_vector(15 downto 0); + PC_SIZE_LEFT_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_TO_SAVE_TST : out std_logic_vector(31 downto 0); + PC_SUB_SIZE_LOADED_TST : out std_logic_vector(31 downto 0); + PC_SUB_BYTES_LOADED_TST : out std_logic_vector(31 downto 0); + PC_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + PC_ACT_QUEUE_SIZE_TST : out std_logic_vector(31 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameConstructor interface + FC_WR_EN_TST : out std_logic; + FC_DATA_TST : out std_logic_vector(7 downto 0); + FC_H_READY_TST : out std_logic; + FC_READY_TST : out std_logic; + FC_IP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_TST : out std_logic_vector(15 downto 0); + FC_IDENT_TST : out std_logic_vector(15 downto 0); + FC_FLAGS_OFFSET_TST : out std_logic_vector(15 downto 0); + FC_SOD_TST : out std_logic; + FC_EOD_TST : out std_logic; + FC_BSM_CONSTR_TST : out std_logic_vector(7 downto 0); + FC_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- FrameTransmitter interface + FT_DATA_TST : out std_logic_vector(8 downto 0); + FT_TX_EMPTY_TST : out std_logic; + FT_START_OF_PACKET_TST : out std_logic; + FT_BSM_INIT_TST : out std_logic_vector(3 downto 0); + FT_BSM_MAC_TST : out std_logic_vector(3 downto 0); + FT_BSM_TRANS_TST : out std_logic_vector(3 downto 0); + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- MAC interface + MAC_HADDR_TST : out std_logic_vector(7 downto 0); + MAC_HDATA_TST : out std_logic_vector(7 downto 0); + MAC_HCS_TST : out std_logic; + MAC_HWRITE_TST : out std_logic; + MAC_HREAD_TST : out std_logic; + MAC_HREADY_TST : out std_logic; + MAC_HDATA_EN_TST : out std_logic; + MAC_FIFOAVAIL_TST : out std_logic; + MAC_FIFOEOF_TST : out std_logic; + MAC_FIFOEMPTY_TST : out std_logic; + MAC_TX_READ_TST : out std_logic; + MAC_TX_DONE_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- pcs and serdes + PCS_AN_LP_ABILITY_TST : out std_logic_vector(15 downto 0); + PCS_AN_COMPLETE_TST : out std_logic; + PCS_AN_PAGE_RX_TST : out std_logic; + ------------------------------------------------------------------------------------------- + ------------------------------------------------------------------------------------------- + -- debug ports + ANALYZER_DEBUG_OUT : out std_logic_vector(63 downto 0) + ); + end component; + @@ -2143,6 +2298,30 @@ package trb_net_components is + component slv_mac_memory is + port( + CLK : in std_logic; + RESET : in std_logic; + BUSY_IN : in std_logic; + -- Slave bus + SLV_ADDR_IN : in std_logic_vector(7 downto 0); + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_BUSY_OUT : out std_logic; + SLV_ACK_OUT : out std_logic; + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + -- I/O to the backend + MEM_CLK_IN : in std_logic; + MEM_ADDR_IN : in std_logic_vector(7 downto 0); + MEM_DATA_OUT : out std_logic_vector(31 downto 0); + -- Status lines + STAT : out std_logic_vector(31 downto 0) -- DEBUG + ); + end component; + + + component slv_register is generic( RESET_VALUE : std_logic_vector(31 downto 0) := x"0000_0000" -- 2.43.0