From 736b5114bd1a8383608b8921db46f85e90487d37 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Fri, 15 Aug 2014 01:00:38 +0200 Subject: [PATCH] nxyter, new working adc handler 2 --- nxyter/checkerror.sh | 7 + nxyter/compile_munich32.pl | 163 ++++++ nxyter/compile_munich32.sh | 12 + nxyter/cores/dynamic_shift_register33x64.ipx | 10 + nxyter/cores/dynamic_shift_register33x64.lpc | 44 ++ nxyter/cores/dynamic_shift_register33x64.vhd | 291 ++++++++++ nxyter/cores/fifo_nxyter_32to32_dc.ipx | 9 + nxyter/cores/fifo_nxyter_32to32_dc.lpc | 50 ++ nxyter/cores/fifo_nxyter_32to32_dc.vhd | 568 +++++++++++++++++++ nxyter/source/adc_ad9228_data_handler.vhd | 326 +++++++++++ nxyter/trb3_periph_constraints.lpf | 9 +- 11 files changed, 1484 insertions(+), 5 deletions(-) create mode 100755 nxyter/checkerror.sh create mode 100755 nxyter/compile_munich32.pl create mode 100755 nxyter/compile_munich32.sh create mode 100644 nxyter/cores/dynamic_shift_register33x64.ipx create mode 100644 nxyter/cores/dynamic_shift_register33x64.lpc create mode 100644 nxyter/cores/dynamic_shift_register33x64.vhd create mode 100644 nxyter/cores/fifo_nxyter_32to32_dc.ipx create mode 100644 nxyter/cores/fifo_nxyter_32to32_dc.lpc create mode 100644 nxyter/cores/fifo_nxyter_32to32_dc.vhd create mode 100644 nxyter/source/adc_ad9228_data_handler.vhd diff --git a/nxyter/checkerror.sh b/nxyter/checkerror.sh new file mode 100755 index 0000000..bdf78db --- /dev/null +++ b/nxyter/checkerror.sh @@ -0,0 +1,7 @@ +#!/bin/sh + +echo "trb3_periph.twr.setup" +grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup +echo "trb3_periph.twr.hold" +grep 'Error:' ./workdir/trb3_periph.twr.hold +grep 'potential circuit loops' ./workdir/* diff --git a/nxyter/compile_munich32.pl b/nxyter/compile_munich32.pl new file mode 100755 index 0000000..2ad7c9e --- /dev/null +++ b/nxyter/compile_munich32.pl @@ -0,0 +1,163 @@ +#!/usr/bin/perl +use Data::Dumper; +use warnings; +use strict; + + + + +################################################################################### +#Settings for this project +my $TOPNAME = "trb3_periph"; #Name of top-level entity +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/3.2'; +my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; +my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; +my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; +################################################################################### + + +use FileHandle; + +$ENV{'SYNPLIFY'}=$synplify_path; +$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; + +my $FAMILYNAME="LatticeECP3"; +my $DEVICENAME="LFE3-150EA"; +my $PACKAGE="FPBGA672"; +my $SPEEDGRADE="8"; + + +#create full lpf file +system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); +system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); + +#set -e +#set -o errexit + +#generate timestamp +my $t=time; +my $fh = new FileHandle(">version.vhd"); +die "could not open file" if (! defined $fh); +print $fh <close; + +system("env| grep LM_"); +my $r = ""; +my $c = ""; + +$c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; +$r=execute($c, "do_not_exit" ); + + +chdir "workdir"; +$fh = new FileHandle("<$TOPNAME".".srr"); +my @a = <$fh>; +$fh -> close; + +foreach (@a) +{ + if(/\@E:/) + { + print STDERR "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; + system($c); + print STDERR "\n\n"; + exit 129; + } +} + + +$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; + +$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; +execute($c); + +my $tpmap = $TOPNAME . "_map" ; + +$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +execute($c); + +system("rm -vf $TOPNAME.ncd"); +system("rm -vf $TOPNAME.dir/*"); + +$c=qq|$lattice_path/ispfpga/bin/lin64/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; +execute($c, "do_not_exit"); + +print STDERR "Do 0\n"; + +system("cp -va ${TOPNAME}.dir/*.ncd ./${TOPNAME}.ncd"); + +print STDERR "Do 1\n"; + + +# IOR IO Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 2\n"; + +# TWR Timing Report +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 3\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +print STDERR "Do 4\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + +print STDERR "Do 5\n"; + +$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; +# $c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; + +print STDERR "Do 6\n"; + +execute($c); + +chdir ".."; + +exit; + +sub execute { + my ($c, $op) = @_; + #print STDERR "option: $op \n"; + $op = "" if(!$op); + print STDERR "\n\ncommand to execute: $c \n"; + $r=system($c); + if($r) { + print STDERR "$!"; + if($op ne "do_not_exit") { + print STDERR "------- EXIT by function execute --------\n"; + exit; + } + } + + return $r; + +} diff --git a/nxyter/compile_munich32.sh b/nxyter/compile_munich32.sh new file mode 100755 index 0000000..746f1ee --- /dev/null +++ b/nxyter/compile_munich32.sh @@ -0,0 +1,12 @@ +#!/bin/sh + +. /usr/local/opt/lattice_diamond/diamond/3.2/bin/lin64/diamond_env + +./compile_munich32.pl + +#grep -q 'Error:' ./workdir/trb3_periph.twr.setup && echo "Timing Errors found in trb3_periph.twr.setup" +grep 'Error: The following path exceeds requirements by' ./workdir/trb3_periph.twr.setup +grep 'Error:' ./workdir/trb3_periph.twr.hold +grep 'potential circuit loops' ./workdir/* + +echo "Script DONE!" diff --git a/nxyter/cores/dynamic_shift_register33x64.ipx b/nxyter/cores/dynamic_shift_register33x64.ipx new file mode 100644 index 0000000..ed7fb9a --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.ipx @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/nxyter/cores/dynamic_shift_register33x64.lpc b/nxyter/cores/dynamic_shift_register33x64.lpc new file mode 100644 index 0000000..9edcd22 --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.lpc @@ -0,0 +1,44 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=RAM_Based_Shift_Register +CoreRevision=5.1 +ModuleName=dynamic_shift_register33x64 +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/09/2014 +Time=14:16:23 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +DataWidth=33 +Type=VarLossless +NoOfShifts=16 +MaxLossyShifts=16 +MaxLosslessShifts=64 +EOR=1 +MemFile= +MemFormat=orca +RamType=bram + +[FilesGenerated] +=mem + +[Command] +cmd_line= -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output diff --git a/nxyter/cores/dynamic_shift_register33x64.vhd b/nxyter/cores/dynamic_shift_register33x64.vhd new file mode 100644 index 0000000..911426a --- /dev/null +++ b/nxyter/cores/dynamic_shift_register33x64.vhd @@ -0,0 +1,291 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.1 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n dynamic_shift_register33x64 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type shiftreg -width 33 -depth 64 -mode 10 -pipe_final_output + +-- Sat Aug 9 14:16:23 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity dynamic_shift_register33x64 is + port ( + Din: in std_logic_vector(32 downto 0); + Addr: in std_logic_vector(5 downto 0); + Clock: in std_logic; + ClockEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(32 downto 0)); +end dynamic_shift_register33x64; + +architecture Structure of dynamic_shift_register33x64 is + + -- internal signal declarations + signal Reset_inv: std_logic; + signal ishreg_addr_w0: std_logic; + signal ishreg_addr_w1: std_logic; + signal sreg_0_ctr_1_ci: std_logic; + signal ishreg_addr_w2: std_logic; + signal ishreg_addr_w3: std_logic; + signal co0: std_logic; + signal ishreg_addr_w4: std_logic; + signal ishreg_addr_w5: std_logic; + signal co2: std_logic; + signal co1: std_logic; + signal shreg_addr_r0: std_logic; + signal precin: std_logic; + signal high_inv: std_logic; + signal scuba_vhi: std_logic; + signal shreg_addr_w0: std_logic; + signal shreg_addr_r1: std_logic; + signal shreg_addr_r2: std_logic; + signal co0_1: std_logic; + signal shreg_addr_w1: std_logic; + signal shreg_addr_w2: std_logic; + signal shreg_addr_r3: std_logic; + signal shreg_addr_r4: std_logic; + signal co1_1: std_logic; + signal shreg_addr_w3: std_logic; + signal shreg_addr_w4: std_logic; + signal shreg_addr_r5: std_logic; + signal co2_1: std_logic; + signal shreg_addr_w5: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of sram_1_0_0_0 : label is "dynamic_shift_register33x64.lpc"; + attribute MEM_INIT_FILE of sram_1_0_0_0 : label is ""; + attribute RESETMODE of sram_1_0_0_0 : label is "SYNC"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_1: INV + port map (A=>Reset, Z=>Reset_inv); + + INV_0: INV + port map (A=>scuba_vhi, Z=>high_inv); + + sram_1_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Din(0), DI1=>Din(1), DI2=>Din(2), DI3=>Din(3), + DI4=>Din(4), DI5=>Din(5), DI6=>Din(6), DI7=>Din(7), + DI8=>Din(8), DI9=>Din(9), DI10=>Din(10), DI11=>Din(11), + DI12=>Din(12), DI13=>Din(13), DI14=>Din(14), DI15=>Din(15), + DI16=>Din(16), DI17=>Din(17), DI18=>Din(18), DI19=>Din(19), + DI20=>Din(20), DI21=>Din(21), DI22=>Din(22), DI23=>Din(23), + DI24=>Din(24), DI25=>Din(25), DI26=>Din(26), DI27=>Din(27), + DI28=>Din(28), DI29=>Din(29), DI30=>Din(30), DI31=>Din(31), + DI32=>Din(32), DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>shreg_addr_w0, ADW1=>shreg_addr_w1, + ADW2=>shreg_addr_w2, ADW3=>shreg_addr_w3, + ADW4=>shreg_addr_w4, ADW5=>shreg_addr_w5, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>ClockEn, + CLKW=>Clock, CSW0=>Reset_inv, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>shreg_addr_r0, ADR6=>shreg_addr_r1, + ADR7=>shreg_addr_r2, ADR8=>shreg_addr_r3, + ADR9=>shreg_addr_r4, ADR10=>shreg_addr_r5, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>ClockEn, + CLKR=>Clock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>open, + DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); + + FF_5: FD1P3DX + port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w0); + + FF_4: FD1P3DX + port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w1); + + FF_3: FD1P3DX + port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w2); + + FF_2: FD1P3DX + port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w3); + + FF_1: FD1P3DX + port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w4); + + FF_0: FD1P3DX + port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock, CD=>Reset, + Q=>shreg_addr_w5); + + sreg_0_ctr_1_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci, + S0=>open, S1=>open); + + sreg_0_ctr_1_0: CU2 + port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0, + PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0, + NC1=>ishreg_addr_w1); + + sreg_0_ctr_1_1: CU2 + port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3, + CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3); + + sreg_0_ctr_1_2: CU2 + port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5, + CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5); + + precin_inst101: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>scuba_vlo, COUT=>precin, S0=>open, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + raddr_sub_1_0: FSUB2B + port map (A0=>scuba_vhi, A1=>shreg_addr_w0, B0=>high_inv, + B1=>Addr(0), BI=>precin, BOUT=>co0_1, S0=>open, + S1=>shreg_addr_r0); + + raddr_sub_1_1: FSUB2B + port map (A0=>shreg_addr_w1, A1=>shreg_addr_w2, B0=>Addr(1), + B1=>Addr(2), BI=>co0_1, BOUT=>co1_1, S0=>shreg_addr_r1, + S1=>shreg_addr_r2); + + raddr_sub_1_2: FSUB2B + port map (A0=>shreg_addr_w3, A1=>shreg_addr_w4, B0=>Addr(3), + B1=>Addr(4), BI=>co1_1, BOUT=>co2_1, S0=>shreg_addr_r3, + S1=>shreg_addr_r4); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + raddr_sub_1_3: FSUB2B + port map (A0=>shreg_addr_w5, A1=>scuba_vlo, B0=>Addr(5), + B1=>scuba_vlo, BI=>co2_1, BOUT=>open, S0=>shreg_addr_r5, + S1=>open); + +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of dynamic_shift_register33x64 is + for Structure + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/fifo_nxyter_32to32_dc.ipx b/nxyter/cores/fifo_nxyter_32to32_dc.ipx new file mode 100644 index 0000000..fcef20d --- /dev/null +++ b/nxyter/cores/fifo_nxyter_32to32_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_nxyter_32to32_dc.lpc b/nxyter/cores/fifo_nxyter_32to32_dc.lpc new file mode 100644 index 0000000..72a1d68 --- /dev/null +++ b/nxyter/cores/fifo_nxyter_32to32_dc.lpc @@ -0,0 +1,50 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.7 +ModuleName=fifo_nxyter_32to32_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/08/2014 +Time=15:52:47 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=32 +RDepth=4 +RWidth=32 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 + +[Command] +cmd_line= -w -n fifo_nxyter_32to32_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 2 -data_width 32 -num_words 4 -rdata_width 32 -outdata REGISTERED -no_enable -pe -1 -pf -1 diff --git a/nxyter/cores/fifo_nxyter_32to32_dc.vhd b/nxyter/cores/fifo_nxyter_32to32_dc.vhd new file mode 100644 index 0000000..494de8c --- /dev/null +++ b/nxyter/cores/fifo_nxyter_32to32_dc.vhd @@ -0,0 +1,568 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134 +-- Module Version: 5.7 +--/usr/local/opt/lattice_diamond/diamond/3.2/ispfpga/bin/lin64/scuba -w -n fifo_nxyter_32to32_dc -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 32 -depth 4 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 + +-- Fri Aug 8 15:52:47 2014 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_nxyter_32to32_dc is + port ( + Data: in std_logic_vector(31 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(31 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_nxyter_32to32_dc; + +architecture Structure of fifo_nxyter_32to32_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal co0: std_logic; + signal wcount_2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal co0_1: std_logic; + signal rcount_2: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_nxyter_32to32_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), + DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), + DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12), + DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16), + DO35=>Q(17)); + + FF_31: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_30: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_29: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_28: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_27: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_26: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_25: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_24: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_23: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_22: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_21: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_20: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_19: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_18: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_17: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_16: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_15: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_14: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_nxyter_32to32_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/source/adc_ad9228_data_handler.vhd b/nxyter/source/adc_ad9228_data_handler.vhd new file mode 100644 index 0000000..815a2e5 --- /dev/null +++ b/nxyter/source/adc_ad9228_data_handler.vhd @@ -0,0 +1,326 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.nxyter_components.all; + +entity adc_ad9228_data_handler is + generic ( + DEBUG_ENABLE : boolean := false + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + DDR_DATA_CLK : in std_logic; + DDR_DATA_IN : in std_logic_vector(19 downto 0); + + DATA_A_OUT : out std_logic_vector(11 downto 0); + DATA_B_OUT : out std_logic_vector(11 downto 0); + DATA_C_OUT : out std_logic_vector(11 downto 0); + DATA_D_OUT : out std_logic_vector(11 downto 0); + DATA_CLK_OUT : out std_logic; + + FRAME_LOCKED_OUT : out std_logic; + ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end adc_ad9228_data_handler; + +architecture Behavioral of adc_ad9228_data_handler is + + -- Frame Lock Handler + type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0); + type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + + type BYTE_STATUS is (B_UNDEF, + B_BITSHIFTED, + B_ALIGNED, + B_SHIFTED + ); + signal adc_data_shift : adc_data_s; + + signal adc_data_m : adc_data_t; + signal adc_data_clk_m : std_logic; + + signal adc_byte_status : BYTE_STATUS; + signal adc_byte_status_last : BYTE_STATUS; + + signal adc_frame_clk_ok : std_logic; + signal adc_frame_clk_ok_hist : std_logic_vector(15 downto 0); + signal adc_frame_locked : std_logic; + signal error_status : std_logic_vector(2 downto 0); + + -- Clock Transfer + signal adc_fifo_empty : std_logic; + signal adc_fifo_full : std_logic; + signal adc_write_enable : std_logic; + signal adc_read_enable : std_logic; + signal adc_read_enable_t : std_logic; + signal adc_read_enable_tt : std_logic; + signal adc_locked_ff : std_logic; + signal adc_locked_f : std_logic; + signal adc_locked_o : std_logic; + signal adc_error_status_ff : std_logic_vector(2 downto 0); + signal adc_error_status_f : std_logic_vector(2 downto 0); + signal adc_error_status_o : std_logic_vector(2 downto 0); + + signal adc_data : adc_data_t; + + -- Output + signal adc_data_clk_o : std_logic; + signal adc_data_o : adc_data_t; + + -- RESET Handler + signal RESET_DDR_DATA_CLK_F : std_logic; + signal RESET_DDR_DATA_CLK : std_logic; + + -- Attributes + attribute syn_keep : boolean; + attribute syn_keep of RESET_DDR_DATA_CLK_F : signal is true; + attribute syn_keep of RESET_DDR_DATA_CLK : signal is true; + + attribute syn_keep of adc_locked_ff : signal is true; + attribute syn_keep of adc_locked_f : signal is true; + + attribute syn_keep of adc_error_status_ff : signal is true; + attribute syn_keep of adc_error_status_f : signal is true; + + attribute syn_preserve : boolean; + attribute syn_preserve of RESET_DDR_DATA_CLK_F : signal is true; + attribute syn_preserve of RESET_DDR_DATA_CLK : signal is true; + + attribute syn_preserve of adc_locked_ff : signal is true; + attribute syn_preserve of adc_locked_f : signal is true; + + attribute syn_preserve of adc_error_status_ff : signal is true; + attribute syn_preserve of adc_error_status_f : signal is true; + +begin + + ----------------------------------------------------------------------------- + RESET_DDR_DATA_CLK_F <= RESET_IN when rising_edge(DDR_DATA_CLK); + RESET_DDR_DATA_CLK <= RESET_DDR_DATA_CLK_F when rising_edge(DDR_DATA_CLK); + + ----------------------------------------------------------------------------- + -- Debug Handler + ----------------------------------------------------------------------------- + + DEBUG_OUT <= (others => '0'); + --DEBUG_OUT(0) <= CLK_IN; + --DEBUG_OUT(1) <= DDR_DATA_CLK; + --DEBUG_OUT(2) <= adc_write_enable; + --DEBUG_OUT(3) <= adc_fifo_full; + --DEBUG_OUT(4) <= adc_fifo_empty; + --DEBUG_OUT(5) <= adc_data_clk_m; + --DEBUG_OUT(6) <= adc_read_enable; + --DEBUG_OUT(7) <= adc_read_enable_t; + --DEBUG_OUT(8) <= adc_read_enable_tt; + --DEBUG_OUT(9) <= adc_data_clk_o; + --DEBUG_OUT(10) <= adc_error; + --DEBUG_OUT(11) <= adc_frame_locked; + --DEBUG_OUT(12) <= adc_frame_clk_ok; + --DEBUG_OUT(14) <= RESET_CLKDIV; + --DEBUG_OUT(15) <= RESET_ADC; + + ----------------------------------------------------------------------------- + -- Lock to ADC Frame Data + ----------------------------------------------------------------------------- + + PROC_LOCK_TO_ADC_FRAME: process(DDR_DATA_CLK) + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_DDR_DATA_CLK = '1') then + for I in 0 to 4 loop + adc_data_shift(I) <= (others => '0'); + end loop; + + for I in 0 to 3 loop + adc_data_m(I) <= (others => '0'); + end loop; + adc_data_clk_m <= '0'; + + adc_byte_status <= B_UNDEF; + adc_byte_status_last <= B_UNDEF; + adc_frame_clk_ok <= '0'; + adc_frame_clk_ok_hist <= (others => '0'); + adc_frame_locked <= '0'; + error_status <= (others => '0'); + else + -- Store new incoming Data in Shift Registers + for I in 0 to 4 loop + adc_data_shift(I)(3) <= DDR_DATA_IN(I + 0); + adc_data_shift(I)(2) <= DDR_DATA_IN(I + 5); + adc_data_shift(I)(1) <= DDR_DATA_IN(I + 10); + adc_data_shift(I)(0) <= DDR_DATA_IN(I + 15); + adc_data_shift(I)(13 downto 4) <= adc_data_shift(I)(9 downto 0); + end loop; + + -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock + case adc_data_shift(4)(11 downto 0) is + when "111111000000" => + -- Input Data is correct and new Frame is available + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(11 downto 0); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED; + + when "111100000011" => + -- Input Data is correct and new Frame is available, + -- but byte shifted by one + for I in 0 to 3 loop + adc_data_m(I) <= adc_data_shift(I)(13 downto 2); + end loop; + adc_data_clk_m <= '1'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_SHIFTED; + + when "110000001111" | "000011111100" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_ALIGNED; + + when "000000111111" | "001111110000" => + -- Input Data is correct + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '1'; + adc_byte_status <= B_SHIFTED; + + when "000001111110" | + "000111111000" | + "011111100000" | + "111110000001" | + "111000000111" | + "100000011111" => + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '0'; + adc_byte_status <= B_BITSHIFTED; + + when others => + -- Input Data is invalid, Fatal Error of DDR Data, needs reset. + adc_data_clk_m <= '0'; + adc_frame_clk_ok <= '0'; + adc_byte_status <= B_UNDEF; + + end case; + + -- Determin ADC Frame Lock Status + adc_frame_clk_ok_hist(0) <= adc_frame_clk_ok; + adc_frame_clk_ok_hist(15 downto 1) <= + adc_frame_clk_ok_hist(14 downto 0); + + if (adc_frame_clk_ok_hist = x"ffff") then + adc_frame_locked <= '1'; + else + adc_frame_locked <= '0'; + end if; + + -- Error Status + adc_byte_status_last <= adc_byte_status; + if (adc_byte_status /= adc_byte_status_last) then + error_status(2) <= '1'; + else + error_status(2) <= '0'; + end if; + + if (adc_byte_status = B_BITSHIFTED) then + error_status(1) <= '1'; + else + error_status(1) <= '0'; + end if; + + if (adc_byte_status = B_UNDEF) then + error_status(0) <= '1'; + else + error_status(0) <= '0'; + end if; + + end if; + + end if; + end process PROC_LOCK_TO_ADC_FRAME; + + ----------------------------------------------------------------------------- + -- Domain Tansfer of Data to CLK_IN + ----------------------------------------------------------------------------- + + fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc + port map ( + Data(11 downto 0) => adc_data_m(0), + Data(23 downto 12) => adc_data_m(1), + Data(35 downto 24) => adc_data_m(2), + Data(47 downto 36) => adc_data_m(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc_write_enable, + RdEn => adc_read_enable, + Reset => RESET_IN, + RPReset => RESET_IN, + Q(11 downto 0) => adc_data(0), + Q(23 downto 12) => adc_data(1), + Q(35 downto 24) => adc_data(2), + Q(47 downto 36) => adc_data(3), + Empty => adc_fifo_empty, + Full => adc_fifo_full + ); + + -- Readout Handler + adc_write_enable <= adc_data_clk_m and not adc_fifo_full; + adc_read_enable <= not adc_fifo_empty; + + PROC_ADC_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + adc_read_enable_tt <= adc_read_enable; + if (RESET_IN = '1') then + adc_read_enable_t <= '0'; + for I in 0 to 3 loop + adc_data_o(I) <= (others => '0'); + end loop; + adc_data_clk_o <= '0'; + else + -- Read enable + adc_read_enable_t <= adc_read_enable_tt; + + if (adc_read_enable_t = '1') then + for I in 0 to 3 loop + adc_data_o(I) <= adc_data(I); + end loop; + adc_data_clk_o <= '1'; + else + adc_data_clk_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC_FIFO_READ; + + ----------------------------------------------------------------------------- + -- Domain Transfer of Control Signals + ----------------------------------------------------------------------------- + adc_locked_ff <= adc_frame_locked when rising_edge(CLK_IN); + adc_locked_f <= adc_locked_ff when rising_edge(CLK_IN); + adc_locked_o <= adc_locked_f when rising_edge(CLK_IN); + + adc_error_status_ff <= error_status when rising_edge(CLK_IN); + adc_error_status_f <= adc_error_status_ff when rising_edge(CLK_IN); + adc_error_status_o <= adc_error_status_f when rising_edge(CLK_IN); + + ----------------------------------------------------------------------------- + -- Output + ----------------------------------------------------------------------------- + DATA_A_OUT <= adc_data_o(0); + DATA_B_OUT <= adc_data_o(1); + DATA_C_OUT <= adc_data_o(2); + DATA_D_OUT <= adc_data_o(3); + DATA_CLK_OUT <= adc_data_clk_o; + + FRAME_LOCKED_OUT <= adc_locked_o; + ERROR_STATUS_OUT <= adc_error_status_o; + +end Behavioral; diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index fc6d3b6..5179c3b 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -1,6 +1,4 @@ - ####################################################################### - - +################################################################# BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; @@ -63,11 +61,11 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLI # Relax some of the timing constraints ################################################################# -################################################# +################################################################# # Muelleimer: # #LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R43C5" ; # -################################################# +################################################################# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 50 ns; @@ -142,3 +140,4 @@ INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN"; #UGROUP NXYTER1 BBOX 100 70 # BLKNAME nXyter_FEE_board_0 #LOCATE UGROUP NXYTER1 SITE "R2C2D"; + -- 2.43.0