From 739d34f578c92a9607a01a89964edb20195933a6 Mon Sep 17 00:00:00 2001 From: hadaq Date: Thu, 8 Nov 2012 19:13:30 +0000 Subject: [PATCH] breakpoint so far, have a nxyter now..lets see --- nxyter/source/adcmv3_components.vhd | 8 +- nxyter/source/gray_decoder.vhd | 13 +- nxyter/source/gray_encoder.vhd | 3 +- nxyter/source/i2c_gstart.vhd | 6 +- nxyter/source/i2c_master.vhd | 7 +- nxyter/source/i2c_sendb.vhd | 9 +- nxyter/source/i2c_slim.vhd | 23 +- nxyter/source/nx_i2c_master.vhd | 382 +++++++++++++++++++++++ nxyter/source/nx_i2c_master.vhd- | 381 ++++++++++++++++++++++ nxyter/source/nx_i2c_sendbyte.vhd | 236 ++++++++++++++ nxyter/source/nx_i2c_startstop.vhd | 182 +++++++++++ nxyter/source/nx_i2c_timer.vhd | 82 +++++ nxyter/source/nx_timestamp_fifo_read.vhd | 98 ++++-- nxyter/source/nx_timestamp_sim.vhd | 28 +- nxyter/source/nxyter.vhd | 257 +++++++++++---- nxyter/source/nxyter_components.vhd | 150 ++++++++- nxyter/source/nxyter_registers.vhd | 5 +- nxyter/source/slave_bus.vhd | 332 -------------------- nxyter/source/slv_ped_thr_mem.vhd | 197 ------------ 19 files changed, 1714 insertions(+), 685 deletions(-) create mode 100644 nxyter/source/nx_i2c_master.vhd create mode 100644 nxyter/source/nx_i2c_master.vhd- create mode 100644 nxyter/source/nx_i2c_sendbyte.vhd create mode 100644 nxyter/source/nx_i2c_startstop.vhd create mode 100644 nxyter/source/nx_i2c_timer.vhd delete mode 100755 nxyter/source/slave_bus.vhd delete mode 100644 nxyter/source/slv_ped_thr_mem.vhd diff --git a/nxyter/source/adcmv3_components.vhd b/nxyter/source/adcmv3_components.vhd index 8655c89..d94cb3f 100644 --- a/nxyter/source/adcmv3_components.vhd +++ b/nxyter/source/adcmv3_components.vhd @@ -83,10 +83,10 @@ component i2c_master SDA_OUT : out std_logic; SCL_IN : in std_logic; SCL_OUT : out std_logic; - STAT : out std_logic_vector(31 downto 0)); + STAT : out std_logic_vector(31 downto 0) + ); end component i2c_master; - component I2C_GSTART port ( CLK_IN : in std_logic; @@ -111,7 +111,7 @@ component i2c_sendb CLK_IN : in std_logic; RESET_IN : in std_logic; DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); + I2C_SPEED_IN : in std_logic_vector(8 downto 0); I2C_BYTE_IN : in std_logic_vector(8 downto 0); I2C_BACK_OUT : out std_logic_vector(8 downto 0); SDA_IN : in std_logic; @@ -131,7 +131,7 @@ component i2c_slim RESET_IN : in std_logic; I2C_GO_IN : in std_logic; ACTION_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(5 downto 0); + I2C_SPEED_IN : in std_logic_vector(8 downto 0); I2C_ADR_IN : in std_logic_vector(7 downto 0); I2C_CMD_IN : in std_logic_vector(7 downto 0); I2C_DW_IN : in std_logic_vector(7 downto 0); diff --git a/nxyter/source/gray_decoder.vhd b/nxyter/source/gray_decoder.vhd index cdcdcd5..cb7f6f6 100644 --- a/nxyter/source/gray_decoder.vhd +++ b/nxyter/source/gray_decoder.vhd @@ -33,22 +33,23 @@ architecture Gray_Decoder of Gray_Decoder is begin -- Gray_Decoder PROC_DECODER: process (CLK_IN) + variable b : std_logic_vector(WIDTH -1 downto 0) := (others => '0'); begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - binary_o <= (others => '0'); + b := (others => '0'); else - binary_o(WIDTH - 1) <= GRAY_IN(WIDTH - 1); + b(WIDTH - 1) := GRAY_IN(WIDTH - 1); - for I in (WIDTH - 2) to 0 loop - binary_o(I) <= binary_o(I + 1) xor GRAY_IN(I); + for I in (WIDTH - 2) downto 0 loop + b(I) := b(I + 1) xor GRAY_IN(I); end loop; end if; end if; - + binary_o <= b; end process PROC_DECODER; - -- Output +-- Output BINARY_OUT <= binary_o; end Gray_Decoder; diff --git a/nxyter/source/gray_encoder.vhd b/nxyter/source/gray_encoder.vhd index 8c642ff..7dc28a9 100644 --- a/nxyter/source/gray_encoder.vhd +++ b/nxyter/source/gray_encoder.vhd @@ -39,13 +39,12 @@ begin gray_o <= (others => '0'); else gray_o(WIDTH - 1) <= BINARY_IN(WIDTH -1); - for I in (WIDTH - 2) to 0 loop + for I in (WIDTH - 2) downto 0 loop gray_o(I) <= BINARY_IN(I + 1) xor BINARY_IN(I); end loop; end if; end if; - GRAY_O <= gray_o; end process PROC_ENCODER; -- Output diff --git a/nxyter/source/i2c_gstart.vhd b/nxyter/source/i2c_gstart.vhd index 71aa45b..54b2c41 100644 --- a/nxyter/source/i2c_gstart.vhd +++ b/nxyter/source/i2c_gstart.vhd @@ -12,7 +12,7 @@ entity I2C_GSTART is RESET_IN : in std_logic; START_IN : in std_logic; DOSTART_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector(7 downto 0); + I2C_SPEED_IN : in std_logic_vector(8 downto 0); SDONE_OUT : out std_logic; SOK_OUT : out std_logic; SDA_IN : in std_logic; @@ -42,7 +42,7 @@ architecture Behavioral of I2C_GSTART is signal CURRENT_STATE, NEXT_STATE: STATES; signal bsm : std_logic_vector(3 downto 0); - signal cctr : std_logic_vector(7 downto 0); -- counter for bit length + signal cctr : unsigned(8 downto 0); -- counter for bit length signal cycdone_x : std_logic; signal cycdone : std_logic; -- one counter period done @@ -80,7 +80,7 @@ begin end process THE_CYC_CTR_PROC; -- end of cycle recognition - cycdone_x <= '1' when (cctr = x"00") else '0'; + cycdone_x <= '1' when (cctr = 0) else '0'; -- The main state machine -- State memory process diff --git a/nxyter/source/i2c_master.vhd b/nxyter/source/i2c_master.vhd index d615674..59c9769 100644 --- a/nxyter/source/i2c_master.vhd +++ b/nxyter/source/i2c_master.vhd @@ -59,6 +59,8 @@ architecture Behavioral of i2c_master is signal status_data : std_logic_vector(31 downto 0); signal i2c_debug : std_logic_vector(31 downto 0); + signal i2c_speed_static : std_logic_vector(8 downto 0); + begin --------------------------------------------------------- @@ -72,7 +74,7 @@ begin -- I2C command / setup I2C_GO_IN => reg_slv_data_in(31), ACTION_IN => reg_slv_data_in(30), - I2C_SPEED_IN => reg_slv_data_in(29 downto 24), + I2C_SPEED_IN => i2c_speed_static, I2C_ADR_IN => reg_slv_data_in(23 downto 16), I2C_CMD_IN => reg_slv_data_in(15 downto 8), I2C_DW_IN => reg_slv_data_in(7 downto 0), @@ -91,7 +93,8 @@ begin status_data(23 downto 21) <= (others => '0'); status_data(20 downto 16) <= i2c_debug(4 downto 0); status_data(15 downto 8) <= (others => '0'); - + i2c_speed_static <= (others => '1'); + -- Fake stat <= i2c_debug; diff --git a/nxyter/source/i2c_sendb.vhd b/nxyter/source/i2c_sendb.vhd index 778878a..af29247 100644 --- a/nxyter/source/i2c_sendb.vhd +++ b/nxyter/source/i2c_sendb.vhd @@ -11,13 +11,12 @@ entity i2c_sendb is CLK_IN : in std_logic; RESET_IN : in std_logic; DOBYTE_IN : in std_logic; - I2C_SPEED_IN : in std_logic_vector( 7 downto 0 ); + I2C_SPEED_IN : in std_logic_vector( 8 downto 0 ); I2C_BYTE_IN : in std_logic_vector( 8 downto 0 ); I2C_BACK_OUT : out std_logic_vector( 8 downto 0 ); SDA_IN : in std_logic; R_SDA_OUT : out std_logic; S_SDA_OUT : out std_logic; --- SCL_IN : in std_logic; R_SCL_OUT : out std_logic; S_SCL_OUT : out std_logic; BDONE_OUT : out std_logic; @@ -62,7 +61,7 @@ architecture Behavioral of i2c_sendb is signal s_scl : std_logic; -- output for SCL signal bctr : std_logic_vector( 3 downto 0 ); -- bit counter (1...9) - signal cctr : std_logic_vector( 7 downto 0 ); -- counter for bit length + signal cctr : unsigned(8 downto 0); -- counter for bit length signal bok : std_logic; signal cycdone : std_logic; -- one counter period done signal bytedone : std_logic; -- all bits sents @@ -93,7 +92,7 @@ begin end process THE_BIT_CTR_PROC; -- end of byte recognition - bytedone <= '1' when (bctr = x"9") else '0'; + bytedone <= '1' when (bctr = x"a") else '0'; -- Countdown for one half of SCL (adjustable clock width) THE_CYC_CTR_PROC: process( clk_in ) @@ -110,7 +109,7 @@ begin end process THE_CYC_CTR_PROC; -- end of cycle recognition - cycdone <= '1' when (cctr = x"00") else '0'; + cycdone <= '1' when (cctr = 0) else '0'; -- Bit output THE_BIT_OUT_PROC: process( clk_in ) diff --git a/nxyter/source/i2c_slim.vhd b/nxyter/source/i2c_slim.vhd index 656f9c9..a219332 100644 --- a/nxyter/source/i2c_slim.vhd +++ b/nxyter/source/i2c_slim.vhd @@ -6,18 +6,15 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; use work.adcmv3_components.all; --- BUG: does alway set bit 0 of address byte to zero !!!! --- REMARK: this is not a bug, but a feature.... - entity i2c_slim is - port( + port ( CLK_IN : in std_logic; RESET_IN : in std_logic; -- I2C command / setup I2C_GO_IN : in std_logic; -- startbit to trigger I2C actions ACTION_IN : in std_logic; -- '0' -> write, '1' -> read - I2C_SPEED_IN : in std_logic_vector( 5 downto 0 ); -- speed adjustment (to be defined) + I2C_SPEED_IN : in std_logic_vector( 8 downto 0 ); -- speed adjustment I2C_ADR_IN : in std_logic_vector( 7 downto 0 ); -- I2C address byte (R/W bit is ignored) I2C_CMD_IN : in std_logic_vector( 7 downto 0 ); -- I2C command byte (sent after address byte) I2C_DW_IN : in std_logic_vector( 7 downto 0 ); -- data word for write command @@ -109,11 +106,11 @@ architecture Behavioral of i2c_slim is signal gs_debug : std_logic_vector(3 downto 0); - signal i2c_speed : std_logic_vector(7 downto 0); + signal i2c_speed : std_logic_vector(8 downto 0); begin - i2c_speed <= i2c_speed_in & "00"; + i2c_speed <= I2C_SPEED_IN & "00"; -- Read phase indicator THE_PHASE_PROC: process( clk_in ) @@ -202,10 +199,10 @@ begin NEXT_STATE <= LOADC; -- I2C write load_c_x <= '1'; elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '0') ) then - NEXT_STATE <= LOADC; -- I2C read, send register address + NEXT_STATE <= LOADC; -- I2C read, send register address load_c_x <= '1'; elsif( (bdone = '1') and (bok = '1') and (action_in = '1') and (phase = '1') ) then - NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte + NEXT_STATE <= LOADD; -- I2C read, send 0xff dummy byte load_d_x <= '1'; elsif( (bdone = '1') and (bok = '0') and (phase = '0') ) then NEXT_STATE <= E_ADDR; -- first address phase failed @@ -310,7 +307,6 @@ begin end process DECODE; -- We need to load different data sets ---LOAD_DATA_PROC: process( clk_in, reset_in, CURRENT_STATE, action_in, phase) LOAD_DATA_PROC: process( clk_in ) begin if( rising_edge(clk_in) ) then @@ -321,9 +317,9 @@ begin elsif( (CURRENT_STATE = LOADA) and (phase = '1') ) then i2c_byte <= i2c_adr_in(6 downto 0) & '1' & '1'; -- send read address, receive ACK elsif( (CURRENT_STATE = LOADC) and (action_in = '0') ) then - i2c_byte <= i2c_cmd_in(7 downto 1) & '0' & '1'; -- send command byte (WRITE), receive ACK + i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK elsif( (CURRENT_STATE = LOADC) and (action_in = '1') ) then - i2c_byte <= i2c_cmd_in(7 downto 1) & '1' & '1'; -- send command byte (READ), receive ACK + i2c_byte <= i2c_cmd_in(7 downto 0) & '1'; -- send command byte, receive ACK elsif( (CURRENT_STATE = LOADD) and (action_in = '0') ) then i2c_byte <= i2c_dw_in & '1'; -- send data byte, receive ACK elsif( (CURRENT_STATE = LOADD) and (action_in = '1') ) then @@ -343,8 +339,7 @@ begin I2C_BACK_OUT => i2c_dr, SDA_IN => sda_in, R_SDA_OUT => r_sda_sb, - S_SDA_OUT => s_sda_sb, --- SCL_IN => scl_in, + S_SDA_OUT => s_sda_sb, R_SCL_OUT => r_scl_sb, S_SCL_OUT => s_scl_sb, BDONE_OUT => bdone, diff --git a/nxyter/source/nx_i2c_master.vhd b/nxyter/source/nx_i2c_master.vhd new file mode 100644 index 0000000..d092a06 --- /dev/null +++ b/nxyter/source/nx_i2c_master.vhd @@ -0,0 +1,382 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_i2c_master is + generic ( + i2c_speed : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- I2C connections + SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_i2c_master is + + signal sda_i : std_logic; + signal sda_x : std_logic; + signal sda : std_logic; + + signal scl_i : std_logic; + signal scl_x : std_logic; + signal scl : std_logic; + + -- I2C Master + signal sda_o : std_logic; + signal scl_o : std_logic; + signal i2c_start : std_logic; + + signal startstop_select : std_logic; + signal startstop_seq_start : std_logic; + signal sendbyte_seq_start : std_logic; + signal sendbyte_byte : std_logic_vector(7 downto 0); + + signal startstop_select_x : std_logic; + signal startstop_seq_start_x : std_logic; + signal wait_timer_init_x : std_logic_vector(11 downto 0); + signal sendbyte_seq_start_x : std_logic; + signal sendbyte_byte_x : std_logic_vector(7 downto 0); + signal i2c_ack_x : std_logic; + + signal sda_startstop : std_logic; + signal scl_startstop : std_logic; + signal sda_sendbyte : std_logic; + signal scl_sendbyte : std_logic; + signal startstop_done : std_logic; + + signal sendbyte_done : std_logic; + signal sendbyte_ack : std_logic; + signal i2c_ack : std_logic; + signal i2c_notready : std_logic; + signal i2c_error : std_logic_vector(3 downto 0); + + type STATES is (S_IDLE, + S_START, + S_START_WAIT, + + S_SEND_CHIP_ID, + S_SEND_CHIP_ID_WAIT, + S_SEND_REGISTER, + S_SEND_REGISTER_WAIT, + + S_STOP, + S_STOP_WAIT + ); + signal STATE, NEXT_STATE : STATES; + + + -- I2C Timer + signal wait_timer_init : unsigned(11 downto 0); + signal wait_timer_done : std_logic; + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal reg_data : std_logic_vector(31 downto 0); + signal i2c_chipid : std_logic_vector(6 downto 0); + signal i2c_rw_bit : std_logic; + signal i2c_registerid : std_logic_vector(7 downto 0); + signal i2c_register_data : std_logic_vector(7 downto 0); + signal i2c_register_value_read : std_logic_vector(7 downto 0); + +begin + + -- Timer + nx_i2c_timer_1: nx_i2c_timer + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + -- Start / Stop Sequence + nx_i2c_startstop_1: nx_i2c_startstop + generic map ( + i2c_speed => i2c_speed + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => startstop_seq_start, + SELECT_IN => startstop_select, + SEQUENCE_DONE_OUT => startstop_done, + SDA_OUT => sda_startstop, + SCL_OUT => scl_startstop, + NREADY_OUT => i2c_notready + ); + + nx_i2c_sendbyte_1: nx_i2c_sendbyte + generic map ( + i2c_speed => i2c_speed + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => sendbyte_seq_start, + BYTE_IN => sendbyte_byte, + SEQUENCE_DONE_OUT => sendbyte_done, + SDA_OUT => sda_sendbyte, + SCL_OUT => scl_sendbyte, + SDA_IN => sda, + ACK_OUT => sendbyte_ack + ); + + -- Debug Line + DEBUG_OUT(0) <= sda_o; + DEBUG_OUT(1) <= scl_o; + DEBUG_OUT(2) <= i2c_start; + DEBUG_OUT(3) <= startstop_done; + DEBUG_OUT(4) <= sda_startstop; + DEBUG_OUT(5) <= scl_startstop; + DEBUG_OUT(6) <= sda_sendbyte; + DEBUG_OUT(7) <= scl_sendbyte; + +-- DEBUG_OUT(11 downto 8) <= i2c_error; + + DEBUG_OUT(15 downto 8) <= (others => '0'); + + i2c_error(0) <= i2c_notready; + i2c_error(1) <= not sendbyte_ack; + i2c_error(3 downto 2) <= (others => '0'); + + -- Sync I2C Lines + sda_i <= SDA_INOUT; + scl_i <= SCL_INOUT; + + PROC_I2C_LINES_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sda_x <= '1'; + sda <= '1'; + + scl_x <= '1'; + scl <= '1'; + else + sda_x <= sda_i; + sda <= sda_x; + + scl_x <= scl_i; + scl <= scl_x; + end if; + end if; + end process PROC_I2C_LINES_SYNC; + + PROC_I2C_MASTER_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + i2c_ack <= '0'; + startstop_select <= '0'; + startstop_seq_start <= '0'; + sendbyte_seq_start <= '0'; + sendbyte_byte <= (others => '0'); + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + i2c_ack <= i2c_ack_x; + startstop_select <= startstop_select_x; + startstop_seq_start <= startstop_seq_start_x; + sendbyte_seq_start <= sendbyte_seq_start_x; + sendbyte_byte <= sendbyte_byte_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_I2C_MASTER_TRANSFER; + + + PROC_I2C_MASTER: process(STATE) + begin + -- Defaults + sda_o <= '1'; + scl_o <= '1'; + i2c_ack_x <= '0'; + startstop_select_x <= '0'; + startstop_seq_start_x <= '0'; + sendbyte_seq_start_x <= '0'; + sendbyte_byte_x <= (others => '0'); + wait_timer_init_x <= (others => '0'); + + case STATE is + + when S_IDLE => + if (i2c_start = '1') then + NEXT_STATE <= S_START; + else + NEXT_STATE <= S_IDLE; + end if; + + -- I2C START Sequence + when S_START => + startstop_select_x <= '1'; + startstop_seq_start_x <= '1'; + NEXT_STATE <= S_START_WAIT; + + when S_START_WAIT => + if (startstop_done = '0') then + NEXT_STATE <= S_START_WAIT; + else + sda_o <= '0'; + scl_o <= '0'; + NEXT_STATE <= S_SEND_CHIP_ID; + end if; + + -- I2C SEND ChipId Sequence + when S_SEND_CHIP_ID => + sda_o <= '0'; + scl_o <= '0'; + sendbyte_byte_x(7 downto 1) <= i2c_chipid; + sendbyte_byte_x(0) <= i2c_rw_bit; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_CHIP_ID_WAIT; + + when S_SEND_CHIP_ID_WAIT => + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_CHIP_ID_WAIT; + else + sda_o <= '0'; + scl_o <= '0'; + NEXT_STATE <= S_SEND_REGISTER; + end if; + + -- I2C SEND RegisterId Sequence + + when S_SEND_REGISTER => + sda_o <= '0'; + scl_o <= '0'; + sendbyte_byte_x <= i2c_registerid; + sendbyte_seq_start_x <= '1'; + NEXT_STATE <= S_SEND_REGISTER_WAIT; + + when S_SEND_REGISTER_WAIT => + if (sendbyte_done = '0') then + NEXT_STATE <= S_SEND_REGISTER_WAIT; + else + sda_o <= '0'; + scl_o <= '0'; + NEXT_STATE <= S_STOP; + end if; + + -- I2C STOP Sequence + when S_STOP => + sda_o <= '0'; + scl_o <= '0'; + startstop_select_x <= '0'; + startstop_seq_start_x <= '1'; + NEXT_STATE <= S_STOP_WAIT; + + when S_STOP_WAIT => + if (startstop_done = '0') then + NEXT_STATE <= S_STOP_WAIT; + else + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_I2C_MASTER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + reg_data <= x"affeaffe"; + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + i2c_start <= '0'; + + i2c_chipid <= (others => '0'); + i2c_rw_bit <= '0'; + i2c_registerid <= (others => '0'); + i2c_register_data <= (others => '0'); + i2c_register_value_read <= (others => '0'); + + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + i2c_start <= '0'; + + if (SLV_WRITE_IN = '1') then + i2c_chipid <= SLV_DATA_IN(30 downto 24); + i2c_registerid <= SLV_DATA_IN(23 downto 16); + i2c_rw_bit <= SLV_DATA_IN(8); + i2c_register_data <= SLV_DATA_IN(7 downto 0); + i2c_start <= '1'; + elsif (SLV_READ_IN = '1') then + slv_data_out_o <= reg_data; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + + +-- Write bit definition OLD boehmer +-- ==================== +-- +-- +-- D[31] I2C_GO 0 => don't do anything on I2C, 1 => start I2C access +-- D[30] I2C_ACTION 0 => write byte, 1 => read byte +-- D[29:24] I2C_SPEED set to all '1' +-- D[23:16] I2C_ADDRESS address of I2C chip +-- D[15:8] I2C_CMD command byte for access +-- D[7:0] I2C_DATA data to be written +-- +-- + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- I2c Outputs + SDA_INOUT <= '0' when (sda_o = '0' or + sda_startstop = '0' or + sda_sendbyte = '0') + else 'Z'; + + SCL_INOUT <= '0' when (scl_o = '0' or + scl_startstop = '0' or + scl_sendbyte = '0') + else 'Z'; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_master.vhd- b/nxyter/source/nx_i2c_master.vhd- new file mode 100644 index 0000000..18eba6a --- /dev/null +++ b/nxyter/source/nx_i2c_master.vhd- @@ -0,0 +1,381 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_i2c_master is + generic ( + i2c_speed : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + -- I2C connections + SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + + -- Slave bus + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end entity; + +architecture Behavioral of nx_i2c_master is + + signal sda_i : std_logic; + signal sda_x : std_logic; + signal sda : std_logic; + + signal scl_i : std_logic; + signal scl_x : std_logic; + signal scl : std_logic; + + -- I2C Master + signal sda_o : std_logic; + signal scl_o : std_logic; + signal i2c_start : std_logic; + + signal sda_startstop : std_logic; + signal scl_startstop : std_logic; + signal startstop_select : std_logic; + signal startstop_seq_start : std_logic; + signal startstop_done : std_logic; + + signal sda_sendbyte : std_logic; + signal scl_sendbyte : std_logic; + signal sendbyte_seq_start : std_logic; + signal sendbyte_byte : std_logic_vector(7 downto 0); + signal sendbyte_done : std_logic; + signal sendbyte_ack : std_logic; + + signal i2c_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal i2c_ack : std_logic; + signal i2c_error : std_logic_vector(3 downto 0); + + type STATES is (S_IDLE, + S_START, + S_START_WAIT, + + S_SEND_BYTE, + S_SET_SDA, + S_SET_SCL, + S_UNSET_SCL, + S_NEXT_BIT, + + S_GET_ACK, + S_ACK_SET_SCL, + S_STORE_ACK, + S_ACK_UNSET_SCL, + S_VERIFY_ACK, + S_ACK_ERROR, + + S_STOP, + S_STOP_WAIT + ); + signal STATE : STATES; + + + -- I2C Timer + signal wait_timer_init : unsigned(11 downto 0); + signal wait_timer_done : std_logic; + + -- TRBNet Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + signal reg_data : std_logic_vector(31 downto 0); + signal i2c_chipid : std_logic_vector(6 downto 0); + signal i2c_rw_bit : std_logic; + + +begin + + -- Timer + nx_i2c_timer_1: nx_i2c_timer + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + -- Start / Stop Sequence + nx_i2c_startstop_1: nx_i2c_startstop + generic map ( + i2c_speed => i2c_speed + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => startstop_seq_start, + SELECT_IN => startstop_select, + SEQUENCE_DONE_OUT => startstop_done, + SDA_OUT => sda_startstop, + SCL_OUT => scl_startstop + ); + + nx_i2c_sendbyte_1: nx_i2c_sendbyte + generic map ( + i2c_speed => i2c_speed + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + START_IN => sendbyte_seq_start, + BYTE_IN => sendbyte_byte, + SEQUENCE_DONE_OUT => sendbyte_done, + SDA_OUT => sda_sendbyte, + SCL_OUT => scl_sendbyte, + SDA_IN => sda, + ACK_OUT => sendbyte_ack + ); + + -- Debug Line + DEBUG_OUT(0) <= sda_o; + DEBUG_OUT(1) <= scl_o; + DEBUG_OUT(2) <= i2c_start; + DEBUG_OUT(3) <= wait_timer_done; + DEBUG_OUT(7 downto 4) <= i2c_error; + + DEBUG_OUT(15 downto 8) <= (others => '0'); + + -- Sync I2C Lines + sda_i <= SDA_INOUT; + scl_i <= SCL_INOUT; + + PROC_I2C_LINES_SYNC: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sda_x <= '1'; + sda <= '1'; + + scl_x <= '1'; + scl <= '1'; + else + sda_x <= sda_i; + sda <= sda_x; + + scl_x <= scl_i; + scl <= scl_x; + end if; + end if; + end process PROC_I2C_LINES_SYNC; + + PROC_I2C_MASTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sda_o <= '1'; + scl_o <= '1'; + wait_timer_init <= (others => '0'); + bit_ctr <= (others => '0'); + i2c_ack <= '0'; + i2c_error <= (others => '0'); + startstop_select <= '0'; + startstop_seq_start <= '0'; + STATE <= S_IDLE; + else + sda_o <= '1'; + scl_o <= '1'; + wait_timer_init <= (others => '0'); + startstop_select <= '0'; + startstop_seq_start <= '0'; + case STATE is + when S_IDLE => + if (i2c_start = '1') then + STATE <= S_START; + else + STATE <= S_IDLE; + end if; + + -- I2C START Sequence + when S_START => + i2c_ack <= '0'; + startstop_select <= '1'; + startstop_seq_start <= '1'; + STATE <= S_START_WAIT; + + when S_START_WAIT => + if (startstop_done = '0') then + STATE <= S_START_WAIT; + else + STATE <= S_SEND_BYTE; + end if; + + -- I2C Send byte + when S_SEND_BYTE => + bit_ctr <= x"7"; + sda_o <= '0'; + scl_o <= '0'; + i2c_byte(7 downto 1) <= i2c_chipid; + i2c_byte(0) <= i2c_rw_bit; + wait_timer_init <= i2c_speed srl 2; + STATE <= S_SET_SDA; + + when S_SET_SDA => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + STATE <= S_SET_SDA; + else + wait_timer_init <= i2c_speed srl 1; + STATE <= S_SET_SCL; + end if; + + when S_SET_SCL => + sda_o <= i2c_byte(7); + if (wait_timer_done = '0') then + STATE <= S_SET_SCL; + else + wait_timer_init <= i2c_speed srl 2; + STATE <= S_UNSET_SCL; + end if; + + when S_UNSET_SCL => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + STATE <= S_UNSET_SCL; + else + STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (bit_ctr > 0) then + bit_ctr <= bit_ctr - 1; + i2c_byte <= i2c_byte sll 1; + wait_timer_init <= i2c_speed srl 2; + STATE <= S_SET_SDA; + else + wait_timer_init <= i2c_speed srl 2; + STATE <= S_GET_ACK; + end if; + + -- I2C Check ACK Sequence + when S_GET_ACK => + scl_o <= '0'; + if (wait_timer_done = '0') then + STATE <= S_GET_ACK; + else + wait_timer_init <= i2c_speed srl 2; + STATE <= S_ACK_SET_SCL; + end if; + + when S_ACK_SET_SCL => + if (wait_timer_done = '0') then + STATE <= S_ACK_SET_SCL; + else + STATE <= S_STORE_ACK; + end if; + + when S_STORE_ACK => + i2c_ack <= sda; + wait_timer_init <= i2c_speed srl 2; + STATE <= S_ACK_UNSET_SCL; + + when S_ACK_UNSET_SCL => + scl_o <= '0'; + if (wait_timer_done = '0') then + STATE <= S_ACK_UNSET_SCL; + else + STATE <= S_VERIFY_ACK; + end if; + + when S_VERIFY_ACK => + scl_o <= '0'; + if (i2c_ack = '0') then + STATE <= S_STOP; + else + STATE <= S_ACK_ERROR; + end if; + + when S_ACK_ERROR => + scl_o <= '0'; + i2c_error(1) <= '1'; + STATE <= S_STOP; + + -- I2C STOP Sequence + when S_STOP => + startstop_select <= '0'; + startstop_seq_start <= '1'; + STATE <= S_STOP_WAIT; + + when S_STOP_WAIT => + if (startstop_done = '0') then + STATE <= S_STOP_WAIT; + else + STATE <= S_IDLE; + end if; + + end case; + + end if; + end if; + end process PROC_I2C_MASTER; + + ----------------------------------------------------------------------------- + -- TRBNet Slave Bus + ----------------------------------------------------------------------------- + + PROC_SLAVE_BUS: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + reg_data <= x"affeaffe"; + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + i2c_start <= '0'; + else + slv_ack_o <= '1'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + slv_data_out_o <= (others => '0'); + i2c_start <= '0'; + + if (SLV_WRITE_IN = '1') then + i2c_chipid <= SLV_DATA_IN(6 downto 0); + i2c_rw_bit <= SLV_DATA_IN(7); + i2c_start <= '1'; + elsif (SLV_READ_IN = '1') then + slv_data_out_o <= reg_data; + + else + slv_ack_o <= '0'; + end if; + end if; + end if; + end process PROC_SLAVE_BUS; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + -- I2c Outputs + SDA_INOUT <= '0' when (sda_o = '0' or sda_startstop = '0') else 'Z'; + SCL_INOUT <= '0' when (scl_o = '0' or scl_startstop = '0') else 'Z'; + + -- Slave Bus + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_sendbyte.vhd b/nxyter/source/nx_i2c_sendbyte.vhd new file mode 100644 index 0000000..2044e31 --- /dev/null +++ b/nxyter/source/nx_i2c_sendbyte.vhd @@ -0,0 +1,236 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + + +entity nx_i2c_sendbyte is + generic ( + i2c_speed : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + + -- I2C connections + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic; + ACK_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_sendbyte is + + -- Send Byte + signal sda_o : std_logic; + signal scl_o : std_logic; + signal i2c_start : std_logic; + + signal sequence_done_o : std_logic; + signal i2c_byte : unsigned(7 downto 0); + signal bit_ctr : unsigned(3 downto 0); + signal i2c_ack_o : std_logic; + signal wait_timer_init : unsigned(11 downto 0); + + signal sequence_done_o_x : std_logic; + signal i2c_byte_x : unsigned(7 downto 0); + signal bit_ctr_x : unsigned(3 downto 0); + signal i2c_ack_o_x : std_logic; + signal wait_timer_init_x : unsigned(11 downto 0); + + type STATES is (S_IDLE, + S_INIT, + S_INIT_WAIT, + + S_SEND_BYTE, + S_SET_SDA, + S_SET_SCL, + S_UNSET_SCL, + S_NEXT_BIT, + + S_GET_ACK, + S_ACK_SET_SCL, + S_STORE_ACK, + S_ACK_UNSET_SCL + ); + signal STATE, NEXT_STATE : STATES; + + -- Wait Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_i2c_timer_1: nx_i2c_timer + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + + PROC_SEND_BYTE_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + bit_ctr <= (others => '0'); + i2c_ack_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + i2c_byte <= i2c_byte_x; + bit_ctr <= bit_ctr_x; + i2c_ack_o <= i2c_ack_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_SEND_BYTE_TRANSFER; + + PROC_SEND_BYTE: process(STATE) + begin + sda_o <= '1'; + scl_o <= '1'; + sequence_done_o_x <= '0'; + i2c_byte_x <= i2c_byte; + bit_ctr_x <= bit_ctr; + i2c_ack_o_x <= i2c_ack_o; + wait_timer_init_x <= (others => '0'); + + case STATE is + when S_IDLE => + if (START_IN = '1') then + sda_o <= '0'; + scl_o <= '0'; + i2c_byte_x <= BYTE_IN; + NEXT_STATE <= S_INIT; + else + NEXT_STATE <= S_IDLE; + end if; + + -- INIT + when S_INIT => + sda_o <= '0'; + scl_o <= '0'; + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_INIT_WAIT; + + when S_INIT_WAIT => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_INIT_WAIT; + else + NEXT_STATE <= S_SEND_BYTE; + end if; + + -- I2C Send byte + when S_SEND_BYTE => + sda_o <= '0'; + scl_o <= '0'; + bit_ctr_x <= x"7"; + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_SET_SDA; + + when S_SET_SDA => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SDA; + else + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_SET_SCL; + end if; + + when S_SET_SCL => + sda_o <= i2c_byte(7); + if (wait_timer_done = '0') then + NEXT_STATE <= S_SET_SCL; + else + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_UNSET_SCL; + end if; + + when S_UNSET_SCL => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_UNSET_SCL; + else + NEXT_STATE <= S_NEXT_BIT; + end if; + + when S_NEXT_BIT => + sda_o <= i2c_byte(7); + scl_o <= '0'; + if (bit_ctr > 0) then + bit_ctr_x <= bit_ctr - 1; + i2c_byte_x <= i2c_byte sll 1; + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_SET_SDA; + else + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_GET_ACK; + end if; + + -- I2C Check ACK Sequence + when S_GET_ACK => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_GET_ACK; + else + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_ACK_SET_SCL; + end if; + + when S_ACK_SET_SCL => + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_SET_SCL; + else + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_STORE_ACK; + end if; + + when S_STORE_ACK => + if (wait_timer_done = '0') then + NEXT_STATE <= S_STORE_ACK; + else + i2c_ack_o_x <= not SDA_IN; + wait_timer_init_x <= i2c_speed srl 2; + NEXT_STATE <= S_ACK_UNSET_SCL; + end if; + + when S_ACK_UNSET_SCL => + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_ACK_UNSET_SCL; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_SEND_BYTE; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + ACK_OUT <= i2c_ack_o; + + -- I2c Outputs + SDA_OUT <= sda_o; + SCL_OUT <= scl_o; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_startstop.vhd b/nxyter/source/nx_i2c_startstop.vhd new file mode 100644 index 0000000..daba5fd --- /dev/null +++ b/nxyter/source/nx_i2c_startstop.vhd @@ -0,0 +1,182 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.nxyter_components.all; + +entity nx_i2c_startstop is + generic ( + i2c_speed : unsigned(11 downto 0) := x"3e8" + ); + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + START_IN : in std_logic; -- Start Sequence + SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop + SEQUENCE_DONE_OUT : out std_logic; + + -- I2C connections + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + NREADY_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_startstop is + + -- I2C Bus + signal sda_o : std_logic; + signal scl_o : std_logic; + signal sequence_done_o : std_logic; + signal wait_timer_init : unsigned(11 downto 0); + + signal sequence_done_o_x : std_logic; + signal wait_timer_init_x : unsigned(11 downto 0); + + type STATES is (S_IDLE, + S_START, + S_WAIT_START_1, + S_WAIT_START_2, + S_WAIT_START_3, + + S_STOP, + S_WAIT_STOP_1, + S_WAIT_STOP_2, + S_WAIT_STOP_3 + ); + signal STATE, NEXT_STATE : STATES; + + -- I2C Timer + signal wait_timer_done : std_logic; + +begin + + -- Timer + nx_i2c_timer_1: nx_i2c_timer + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + PROC_START_STOP_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + sequence_done_o <= '0'; + wait_timer_init <= (others => '0'); + STATE <= S_IDLE; + else + sequence_done_o <= sequence_done_o_x; + wait_timer_init <= wait_timer_init_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_START_STOP_TRANSFER; + + PROC_START_STOP: process(STATE) + begin + + sda_o <= '1'; + scl_o <= '1'; + wait_timer_init_x <= (others => '0'); + sequence_done_o_x <= '0'; + + case STATE is + when S_IDLE => + if (START_IN = '1') then + if (SELECT_IN = '1') then + NEXT_STATE <= S_START; + else + sda_o <= '0'; + scl_o <= '0'; + NEXT_STATE <= S_STOP; + end if; + else + NEXT_STATE <= S_IDLE; + end if; + + -- I2C START Sequence + when S_START => + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_START_1; + + when S_WAIT_START_1 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_1; + else + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_START_2; + end if; + + when S_WAIT_START_2 => + sda_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_2; + else + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_START_3; + end if; + + when S_WAIT_START_3 => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_START_3; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + -- I2C STOP Sequence + when S_STOP => + sda_o <= '0'; + scl_o <= '0'; + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_STOP_1; + + when S_WAIT_STOP_1 => + sda_o <= '0'; + scl_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_1; + else + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_STOP_2; + end if; + + when S_WAIT_STOP_2 => + sda_o <= '0'; + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_2; + else + wait_timer_init_x <= i2c_speed srl 1; + NEXT_STATE <= S_WAIT_STOP_3; + end if; + + when S_WAIT_STOP_3 => + if (wait_timer_done = '0') then + NEXT_STATE <= S_WAIT_STOP_3; + else + sequence_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + end if; + + end case; + end process PROC_START_STOP; + + + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + SEQUENCE_DONE_OUT <= sequence_done_o; + SDA_OUT <= sda_o; + SCL_OUT <= scl_o; + NREADY_OUT <= '0'; + +end Behavioral; diff --git a/nxyter/source/nx_i2c_timer.vhd b/nxyter/source/nx_i2c_timer.vhd new file mode 100644 index 0000000..15d5ab9 --- /dev/null +++ b/nxyter/source/nx_i2c_timer.vhd @@ -0,0 +1,82 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity nx_i2c_timer is + port( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + + TIMER_START_IN : in unsigned(11 downto 0); + TIMER_DONE_OUT : out std_logic + ); +end entity; + +architecture Behavioral of nx_i2c_timer is + + -- Timer + signal timer_ctr : unsigned(11 downto 0); + signal timer_done_o : std_logic; + + signal timer_ctr_x : unsigned(11 downto 0); + signal timer_done_o_x : std_logic; + + type STATES is (S_IDLE, + S_COUNT, + S_DONE + ); + signal STATE, NEXT_STATE : STATES; + +begin + + PROC_TIMER_TRANSFER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + timer_ctr <= (others => '0'); + timer_done_o <= '0'; + STATE <= S_IDLE; + else + timer_ctr <= timer_ctr_x; + timer_done_o <= timer_done_o_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_TIMER_TRANSFER; + + PROC_TIMER: process(STATE) + begin + + timer_done_o_x <= '0'; + + case STATE is + when S_IDLE => + if (TIMER_START_IN = 0) then + NEXT_STATE <= S_IDLE; + else + timer_ctr_x <= TIMER_START_IN; + NEXT_STATE <= S_COUNT; + end if; + + when S_COUNT => + if (timer_ctr > 0) then + timer_ctr_x <= timer_ctr - 1; + NEXT_STATE <= S_COUNT; + else + NEXT_STATE <= S_DONE; + end if; + + when S_DONE => + timer_done_o_x <= '1'; + NEXT_STATE <= S_IDLE; + + end case; + end process PROC_TIMER; + + ----------------------------------------------------------------------------- + -- Output Signals + ----------------------------------------------------------------------------- + + TIMER_DONE_OUT <= timer_done_o; + +end Behavioral; diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index 6c27eb2..250b819 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -4,7 +4,6 @@ use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library work; -use work.adcmv3_components.all; use work.nxyter_components.all; entity nx_timestamp_fifo_read is @@ -17,6 +16,7 @@ entity nx_timestamp_fifo_read is NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_FRAME_CLOCK_OUT : out std_logic; NX_FRAME_SYNC_OUT : out std_logic; + NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); -- Slave bus SLV_READ_IN : in std_logic; @@ -26,7 +26,9 @@ entity nx_timestamp_fifo_read is SLV_ADDR_IN : in std_logic_vector(15 downto 0); SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(7 downto 0) ); end entity; @@ -34,6 +36,7 @@ architecture Behavioral of nx_timestamp_fifo_read is -- FIFO Input Handler + signal nx_timestamp_n : std_logic_vector(7 downto 0); signal fifo_skip_write_x : std_logic; signal fifo_skip_write_l : std_logic; signal fifo_skip_write : std_logic; @@ -56,8 +59,14 @@ architecture Behavioral of nx_timestamp_fifo_read is signal fifo_skip_write_s : std_logic; -- SYNC NX Frame Process - signal nx_frame_resync_ctr : unsigned(7 downto 0); + + -- RS Sync FlipFlop signal nx_frame_synced_o : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + + -- Sync Process + signal nx_frame_resync_ctr : unsigned(7 downto 0); signal frame_sync_wait_ctr : unsigned (7 downto 0); -- Slave Bus @@ -87,13 +96,37 @@ architecture Behavioral of nx_timestamp_fifo_read is begin + DEBUG_OUT(0) <= fifo_write_enable_o; + DEBUG_OUT(1) <= fifo_full; + DEBUG_OUT(2) <= fifo_read_enable_o; + DEBUG_OUT(3) <= fifo_empty; + + DEBUG_OUT(4) <= nx_frame_synced_o; + DEBUG_OUT(5) <= fifo_skip_write_o; + DEBUG_OUT(6) <= nx_frame_clock_o; + DEBUG_OUT(7) <= CLK_IN; + ----------------------------------------------------------------------------- -- Dual Clock FIFO 8bit to 32bit ----------------------------------------------------------------------------- + -- First Decode + -- Gray_Decoder_1: Gray_Decoder + -- generic map ( + -- WIDTH => 8) + -- port map ( + -- CLK_IN => NX_TIMESTAMP_CLK_IN, + -- RESET_IN => RESET_IN, + -- GRAY_IN => NX_TIMESTAMP_IN, + -- BINARY_OUT => nx_timestamp_n + -- ); + nx_timestamp_n <= NX_TIMESTAMP_IN; + + + -- Second send data to FIFO fifo_dc_8to32_1: fifo_dc_8to32 port map ( - Data => NX_TIMESTAMP_IN, + Data => nx_timestamp_n, WrClock => NX_TIMESTAMP_CLK_IN, RdClock => CLK_IN, WrEn => fifo_write_enable_o, @@ -105,10 +138,11 @@ begin Full => fifo_full_i ); + ----------------------------------------------------------------------------- -- FIFO Input Handler ----------------------------------------------------------------------------- - + -- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal -- fifo_skip_write PROC_FIFO_IN_HANDLER_SYNC: process(NX_TIMESTAMP_CLK_IN) @@ -125,13 +159,13 @@ begin end process PROC_FIFO_IN_HANDLER_SYNC; -- Signal fifo_skip_write might 2 clocks long --> I need 1 - level_to_pulse_1: level_to_pulse - port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, - RESET_IN => RESET_IN, - LEVEL_IN => fifo_skip_write_l, - PULSE_OUT => fifo_skip_write - ); + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => NX_TIMESTAMP_CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => fifo_skip_write_l, + PULSE_OUT => fifo_skip_write + ); -- Write only in case FIFO is not full, skip one write cycle in case -- fifo_skip_write is true (needed by the synchronization process @@ -171,7 +205,6 @@ begin NX_FRAME_CLOCK_OUT <= nx_frame_clock_o; - ----------------------------------------------------------------------------- -- FIFO Output Handler and Sync FIFO ----------------------------------------------------------------------------- @@ -204,48 +237,60 @@ begin end if; end if; end process PROC_FIFO_READ; + + -- RS FlipFlop to hold Sync Status + PROC_RS_FRAME_SYNCED: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or rs_sync_reset = '1') then + nx_frame_synced_o <= '0'; + elsif (rs_sync_set = '1') then + nx_frame_synced_o <= '1'; + end if; + end if; + end process PROC_RS_FRAME_SYNCED; - -- Sync to NX NO_DATA FRAME + -- Sync to NX NO_DATA FRAME PROC_SYNC_TO_NO_DATA: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - nx_frame_synced_o <= '0'; + rs_sync_set <= '0'; + rs_sync_reset <= '1'; nx_frame_resync_ctr <= (others => '0'); frame_sync_wait_ctr <= (others => '0'); - fifo_skip_write_s <= '0'; - STATE_SYNC <= SYNC_CHECK; + fifo_skip_write_s <= '0'; + STATE_SYNC <= SYNC_CHECK; else + rs_sync_set <= '0'; + rs_sync_reset <= '0'; fifo_skip_write_s <= '0'; - + case STATE_SYNC is when SYNC_CHECK => case fifo_out is when x"7f7f7f06" => - nx_frame_synced_o <= '1'; - STATE_SYNC <= SYNC_CHECK; + rs_sync_set <= '1'; + STATE_SYNC <= SYNC_CHECK; when x"067f7f7f" => - nx_frame_synced_o <= '0'; STATE_SYNC <= SYNC_RESYNC; when x"7f067f7f" => - nx_frame_synced_o <= '0'; STATE_SYNC <= SYNC_RESYNC; when x"7f7f067f" => - nx_frame_synced_o <= '0'; STATE_SYNC <= SYNC_RESYNC; when others => - nx_frame_synced_o <= nx_frame_synced_o; STATE_SYNC <= SYNC_CHECK; - + end case; when SYNC_RESYNC => + rs_sync_reset <= '1'; fifo_skip_write_s <= '1'; nx_frame_resync_ctr <= nx_frame_resync_ctr + 1; frame_sync_wait_ctr <= x"ff"; @@ -266,7 +311,8 @@ begin end process PROC_SYNC_TO_NO_DATA; NX_FRAME_SYNC_OUT <= nx_frame_synced_o; - + NX_TIMESTAMP_OUT <= register_fifo_data; + ------------------------------------------------------------------------------- -- TRBNet Slave Bus ------------------------------------------------------------------------------- diff --git a/nxyter/source/nx_timestamp_sim.vhd b/nxyter/source/nx_timestamp_sim.vhd index 30588eb..47ce26f 100644 --- a/nxyter/source/nx_timestamp_sim.vhd +++ b/nxyter/source/nx_timestamp_sim.vhd @@ -54,22 +54,22 @@ begin end if; end process PROC_NX_TIMESTAMP; - - --- Gray_Encoder_1: Gray_Encoder --- generic map ( --- WIDTH => 8 --- ) --- port map ( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- BINARY_IN => timestamp_n, --- GRAY_OUT => timestamp_g --- ); +-- Gray_Encoder_1: Gray_Encoder +-- generic map ( +-- WIDTH => 8 +-- ) +-- port map ( +-- CLK_IN => CLK_IN, +-- RESET_IN => RESET_IN, +-- BINARY_IN => timestamp_n, +-- GRAY_OUT => timestamp_g +-- ); -- - + timestamp_g <= timestamp_n; + + -- Output Signals - TIMESTAMP_OUT <= timestamp_n; + TIMESTAMP_OUT <= timestamp_g; CLK128_OUT <= CLK_IN; end Behavioral; diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index e09a6da..69b9fa6 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -1,6 +1,6 @@ ----------------------------------------------------------------------------- -- ---One nXyter FEB +-- One nXyter FEB -- ----------------------------------------------------------------------------- library ieee; @@ -10,8 +10,8 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.adcmv3_components.all; use work.nxyter_components.all; +-- ADCM use work.adcmv3_components.all; entity nXyter_FEE_board is @@ -21,13 +21,13 @@ entity nXyter_FEE_board is -- I2C Ports I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line - I2C_SCL_OUT : out std_logic; -- nXyter I2C Clock line + I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C StateMachine I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers to default -- ADC SPI SPI_SCLK_OUT : out std_logic; - SPI_SDIO_INOUT : in std_logic; + SPI_SDIO_INOUT : inout std_logic; SPI_CSB_OUT : out std_logic; -- nXyter Timestamp Ports @@ -56,7 +56,11 @@ entity nXyter_FEE_board is REGIO_DATAREADY_OUT : out std_logic; REGIO_WRITE_ACK_OUT : out std_logic; REGIO_NO_MORE_DATA_OUT : out std_logic; - REGIO_UNKNOWN_ADDR_OUT : out std_logic + REGIO_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Signals + CLK_128_IN : in std_logic; + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) ); end nXyter_FEE_board; @@ -67,11 +71,13 @@ architecture Behavioral of nXyter_FEE_board is ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- + -- Clock 256 + signal clk_256_o : std_logic; -- Bus Handler signal slv_read : std_logic_vector(8-1 downto 0); signal slv_write : std_logic_vector(8-1 downto 0); - signal slv_busy : std_logic_vector(8-1 downto 0); + signal slv_no_more_data : std_logic_vector(8-1 downto 0); signal slv_ack : std_logic_vector(8-1 downto 0); signal slv_addr : std_logic_vector(8*16-1 downto 0); signal slv_data_rd : std_logic_vector(8*32-1 downto 0); @@ -79,34 +85,90 @@ architecture Behavioral of nXyter_FEE_board is signal slv_unknown_addr : std_logic_vector(8-1 downto 0); -- I2C Master - signal i2c_sda_o : std_logic; -- I2C SDA - signal i2c_sda_i : std_logic; - signal i2c_scl_o : std_logic; -- I2C SCL - signal i2c_scl_i : std_logic; - +-- ADCM signal i2c_sda_o : std_logic; +-- ADCM signal i2c_sda_i : std_logic; +-- ADCM signal i2c_scl_o : std_logic; +-- ADCM signal i2c_scl_i : std_logic; + signal i2c_sm_reset_o : std_logic; + signal i2c_reg_reset_o : std_logic; + -- SPI Interface ADC signal spi_sdi : std_logic; signal spi_sdo : std_logic; + -- FIFO Read + signal nx_frame_clock_o : std_logic; + signal nx_frame_sync_o : std_logic; + + + -- Timestamp Handlers + signal nx_timestamp_o : std_logic_vector(31 downto 0); + + begin +------------------------------------------------------------------------------- +-- DEBUG +------------------------------------------------------------------------------- +-- DEBUG_LINE_OUT(0) <= CLK_IN; +-- DEBUG_LINE_OUT(1) <= clk_256_o; +-- DEBUG_LINE_OUT(2) <= NX_CLK128_IN; +-- DEBUG_LINE_OUT(3) <= nx_frame_clock_o; +-- DEBUG_LINE_OUT(4) <= nx_frame_sync_o; +-- DEBUG_LINE_OUT(7 downto 5) <= (others => '0'); +-- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; +-- DEBUG_LINE_OUT(8) <= i2c_sda_o; +-- DEBUG_LINE_OUT(9) <= i2c_sda_i; +-- DEBUG_LINE_OUT(10) <= i2c_scl_o; +-- DEBUG_LINE_OUT(11) <= i2c_scl_i; +-- DEBUG_LINE_OUT(15 downto 12) <= (others => '0'); + + DEBUG_LINE_OUT(0) <= CLK_IN; + DEBUG_LINE_OUT(1) <= I2C_SDA_INOUT; + DEBUG_LINE_OUT(2) <= I2C_SCL_INOUT; + + DEBUG_LINE_OUT(7 downto 3) <= (others => '0'); + ------------------------------------------------------------------------------- -- Port Maps ------------------------------------------------------------------------------- + + + -- pll_nx_clk256_1: pll_nx_clk256 + -- port map ( + -- CLK => CLK_IN, + -- CLKOP => clk_256_o, + -- LOCK => open + -- ); + + -- pll_25_1: pll_25 + -- port map ( + -- CLK => CLK_IN, + -- CLKOP => clk_256_o, + -- LOCK => open + -- ); + clk_256_o <= CLK_128_IN; + + NX_RESET_OUT <= '0'; + NX_CLK256A_OUT <= clk_256_o; + NX_TESTPULSE_OUT <= '0'; + -- TRBNet Bus Handler THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler - 1 => x"0040", -- I2C master - 2 => x"0100", -- Timestamp Fifo - -- 3 => x"d100", -- SPI data memory + PORT_NUMBER => 4, + PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler + 1 => x"0040", -- I2C master + 2 => x"0100", -- Timestamp Fifo + 3 => x"0200", -- Data Buffer + -- 3 => x"d100", -- SPI data memory others => x"0000"), - PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler - 1 => 0, -- I2C master - 2 => 1, -- Timestamp Fifo - -- 3 => 6, -- SPI data memory + PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler + 1 => 0, -- I2C master + 2 => 1, -- Timestamp Fifo + 3 => 1, -- Data Buffer + -- 3 => 6, -- SPI data memory others => 0) ) port map( @@ -133,7 +195,7 @@ begin BUS_TIMEOUT_OUT(0) => open, BUS_DATAREADY_IN(0) => slv_ack(0), BUS_WRITE_ACK_IN(0) => slv_ack(0), - BUS_NO_MORE_DATA_IN(0) => slv_busy(0), + BUS_NO_MORE_DATA_IN(0) => slv_no_more_data(0), BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0), -- I2C master @@ -145,8 +207,8 @@ begin BUS_TIMEOUT_OUT(1) => open, BUS_DATAREADY_IN(1) => slv_ack(1), BUS_WRITE_ACK_IN(1) => slv_ack(1), - BUS_NO_MORE_DATA_IN(1) => slv_busy(1), - BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_NO_MORE_DATA_IN(1) => slv_no_more_data(1), + BUS_UNKNOWN_ADDR_IN(1) => slv_unknown_addr(1), -- Timestamp Fifo BUS_READ_ENABLE_OUT(2) => slv_read(2), @@ -159,9 +221,23 @@ begin BUS_TIMEOUT_OUT(2) => open, BUS_DATAREADY_IN(2) => slv_ack(2), BUS_WRITE_ACK_IN(2) => slv_ack(2), - BUS_NO_MORE_DATA_IN(2) => slv_busy(2), + BUS_NO_MORE_DATA_IN(2) => slv_no_more_data(2), BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2), + -- DataBuffer + BUS_READ_ENABLE_OUT(3) => slv_read(3), + BUS_WRITE_ENABLE_OUT(3) => slv_write(3), + BUS_DATA_OUT(3*32+31 downto 3*32) => slv_data_wr(3*32+31 downto 3*32), + BUS_DATA_IN(3*32+31 downto 3*32) => slv_data_rd(3*32+31 downto 3*32), +-- BUS_ADDR_OUT(3*16+0 downto 2*16) => slv_addr(3*16+0 downto 0*16), + BUS_ADDR_OUT(3*16+0) => slv_addr(3*16+0), + BUS_ADDR_OUT(3*16+15 downto 3*16+1) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATAREADY_IN(3) => slv_ack(3), + BUS_WRITE_ACK_IN(3) => slv_ack(3), + BUS_NO_MORE_DATA_IN(3) => slv_no_more_data(3), + BUS_UNKNOWN_ADDR_IN(3) => slv_unknown_addr(3), + ---- SPI control registers --BUS_READ_ENABLE_OUT(4) => slv_read(4), --BUS_WRITE_ENABLE_OUT(4) => slv_write(4), @@ -171,7 +247,7 @@ begin --BUS_TIMEOUT_OUT(4) => open, --BUS_DATAREADY_IN(4) => slv_ack(4), --BUS_WRITE_ACK_IN(4) => slv_ack(4), - --BUS_NO_MORE_DATA_IN(4) => slv_busy(4), + --BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4), --BUS_UNKNOWN_ADDR_IN(4) => '0', ---- SPI data memory @@ -183,11 +259,10 @@ begin --BUS_TIMEOUT_OUT(5) => open, --BUS_DATAREADY_IN(5) => slv_ack(5), --BUS_WRITE_ACK_IN(5) => slv_ack(5), - --BUS_NO_MORE_DATA_IN(5) => slv_busy(5), + --BUS_NO_MORE_DATA_IN(5) => slv_no_more_data(5), --BUS_UNKNOWN_ADDR_IN(5) => '0', ---- debug - --STAT_DEBUG => stat STAT_DEBUG => open ); @@ -206,35 +281,61 @@ begin SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16), SLV_ACK_OUT => slv_ack(0), - SLV_NO_MORE_DATA_OUT => slv_busy(0), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) + SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0), + + DEBUG_OUT => open ); ------------------------------------------------------------------------------- -- I2C master block for accessing the nXyter ------------------------------------------------------------------------------- - THE_I2C_MASTER: i2c_master - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - -- Slave bus - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_BUSY_OUT => slv_busy(1), - SLV_ACK_OUT => slv_ack(1), - SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), - SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), - - -- I2C connections - SDA_IN => open, - SDA_OUT => open, - SCL_IN => open, - SCL_OUT => open, - - -- Status lines - STAT => open + nx_i2c_master_1: nx_i2c_master + generic map ( + i2c_speed => x"3e8" + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SDA_INOUT => I2C_SDA_INOUT, + SCL_INOUT => I2C_SCL_INOUT, + SLV_READ_IN => slv_read(1), + SLV_WRITE_IN => slv_write(1), + SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), + SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), + SLV_ACK_OUT => slv_ack(1), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(1), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1), + DEBUG_OUT(7 downto 0) => DEBUG_LINE_OUT(15 downto 8) ); + +-- ADCM i2c_master_1: i2c_master +-- ADCM port map ( +-- ADCM CLK_IN => CLK_IN, +-- ADCM RESET_IN => RESET_IN, +-- ADCM SLV_READ_IN => slv_read(1), +-- ADCM SLV_WRITE_IN => slv_write(1), +-- ADCM SLV_BUSY_OUT => open, +-- ADCM SLV_ACK_OUT => slv_ack(1), +-- ADCM SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), +-- ADCM SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), +-- ADCM SDA_IN => i2c_sda_i, +-- ADCM SDA_OUT => i2c_sda_o, +-- ADCM SCL_IN => i2c_scl_i, +-- ADCM SCL_OUT => i2c_scl_o, +-- ADCM STAT => open +-- ADCM ); +-- ADCM +-- ADCM -- I2c Outputs +-- ADCM I2C_SDA_INOUT <= '0' when (i2c_sda_o = '0') else 'Z'; +-- ADCM i2c_sda_i <= I2C_SDA_INOUT; +-- ADCM I2C_SCL_INOUT <= '0' when (i2c_scl_o = '0') else 'Z'; +-- ADCM i2c_scl_i <= I2C_SCL_INOUT; + + i2c_sm_reset_o <= not '0'; + i2c_reg_reset_o <= not '0'; + ------------------------------------------------------------------------------- -- nXyter TimeStamp Read ------------------------------------------------------------------------------- @@ -243,39 +344,59 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, + NX_TIMESTAMP_CLK_IN => NX_CLK128_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_FRAME_CLOCK_OUT => open, - + NX_FRAME_CLOCK_OUT => nx_frame_clock_o, + NX_FRAME_SYNC_OUT => nx_frame_sync_o, + NX_TIMESTAMP_OUT => nx_timestamp_o, + SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_busy(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) + SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), + +-- DEBUG_OUT => DEBUG_LINE_OUT(7 downto 0) + DEBUG_OUT => open ); - ----------------------------------------------------------------------------- - -- nXyter Signals - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- I2C Signals - ----------------------------------------------------------------------------- +------------------------------------------------------------------------------- +-- Data Buffer FIFO +------------------------------------------------------------------------------- + nx_data_buffer_1: nx_data_buffer + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, - -- SDA line output - I2C_SDA_INOUT <= '0' when (i2c_sda_o = '0') else 'Z'; + FIFO_DATA_IN => nx_timestamp_o, + FIFO_WRITE_ENABLE_IN => '1', + FIFO_READ_ENABLE_IN => '1', + + SLV_READ_IN => slv_read(3), + SLV_WRITE_IN => slv_write(3), + SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32), + SLV_DATA_IN => slv_data_wr(3*32+31 downto 3*32), + SLV_ADDR_IN => slv_addr(3*16+15 downto 3*16), + SLV_ACK_OUT => slv_ack(3), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3) + ); - -- SDA line input (wired OR negative logic) - -- i2c_sda_i <= i2c_sda; - -- SCL line output - I2C_SCL_OUT <= '0' when (i2c_scl_o = '0') else 'Z'; +------------------------------------------------------------------------------- +-- nXyter Signals +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- I2C Signals +------------------------------------------------------------------------------- - -- SCL line input (wired OR negative logic) - -- i2c_scl_i <= i2c_scl; + I2C_SM_RESET_OUT <= i2c_sm_reset_o; + I2C_REG_RESET_OUT <= i2c_reg_reset_o; ------------------------------------------------------------------------------- -- END diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index e2ef4ae..cdb9ab5 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -3,7 +3,6 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; - package nxyter_components is ------------------------------------------------------------------------------- @@ -16,12 +15,12 @@ component nXyter_FEE_board RESET_IN : in std_logic; I2C_SDA_INOUT : inout std_logic; - I2C_SCL_OUT : out std_logic; + I2C_SCL_INOUT : inout std_logic; I2C_SM_RESET_OUT : out std_logic; I2C_REG_RESET_OUT : out std_logic; SPI_SCLK_OUT : out std_logic; - SPI_SDIO_INOUT : in std_logic; + SPI_SDIO_INOUT : inout std_logic; SPI_CSB_OUT : out std_logic; NX_CLK128_IN : in std_logic; @@ -47,10 +46,84 @@ component nXyter_FEE_board REGIO_DATAREADY_OUT : out std_logic; REGIO_WRITE_ACK_OUT : out std_logic; REGIO_NO_MORE_DATA_OUT : out std_logic; - REGIO_UNKNOWN_ADDR_OUT : out std_logic + REGIO_UNKNOWN_ADDR_OUT : out std_logic; + + CLK_128_IN : in std_logic; + DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) ); end component; +------------------------------------------------------------------------------- +-- nXyter I2C Interface +------------------------------------------------------------------------------- + + +component nx_i2c_master + generic ( + i2c_speed : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + SDA_INOUT : inout std_logic; + SCL_INOUT : inout std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + +component nx_i2c_timer + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + TIMER_START_IN : in unsigned(11 downto 0); + TIMER_DONE_OUT : out std_logic + ); +end component; + +component nx_i2c_startstop + generic ( + i2c_speed : unsigned(11 downto 0)); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; -- Start Sequence + SELECT_IN : in std_logic; -- '1' -> Start, '0'-> Stop + SEQUENCE_DONE_OUT : out std_logic; + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + NREADY_OUT : out std_logic + ); +end component; + +component nx_i2c_sendbyte + generic ( + i2c_speed : unsigned(11 downto 0) + ); + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + START_IN : in std_logic; + BYTE_IN : in std_logic_vector(7 downto 0); + SEQUENCE_DONE_OUT : out std_logic; + SDA_OUT : out std_logic; + SCL_OUT : out std_logic; + SDA_IN : in std_logic; + ACK_OUT : out std_logic + ); +end component; + +------------------------------------------------------------------------------- +-- TRBNet Registers +------------------------------------------------------------------------------- + + component nxyter_registers port ( CLK_IN : in std_logic; @@ -62,7 +135,8 @@ component nxyter_registers SLV_ADDR_IN : in std_logic_vector(15 downto 0); SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -84,9 +158,13 @@ component nx_timestamp_fifo_read port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_TIMESTAMP_CLK_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_FRAME_CLOCK_OUT : out std_logic; + NX_TIMESTAMP_CLK_IN : in std_logic; + + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + NX_FRAME_CLOCK_OUT : out std_logic; + NX_FRAME_SYNC_OUT : out std_logic; + NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); + SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -94,7 +172,9 @@ component nx_timestamp_fifo_read SLV_ADDR_IN : in std_logic_vector(15 downto 0); SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(7 downto 0) ); end component; @@ -114,7 +194,8 @@ component Gray_Decoder CLK_IN : in std_logic; RESET_IN : in std_logic; GRAY_IN : in std_logic_vector(WIDTH - 1 downto 0); - BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0)); + BINARY_OUT : out std_logic_vector(WIDTH - 1 downto 0) + ); end component; @@ -125,7 +206,54 @@ component Gray_Encoder CLK_IN : in std_logic; RESET_IN : in std_logic; BINARY_IN : in std_logic_vector(WIDTH - 1 downto 0); - GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0)); + GRAY_OUT : out std_logic_vector(WIDTH - 1 downto 0) + ); +end component; + +component fifo_32_data + port ( + Data : in std_logic_vector(31 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end component; + +component nx_data_buffer + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + FIFO_DATA_IN : std_logic_vector(31 downto 0); + FIFO_WRITE_ENABLE_IN : std_logic; + FIFO_READ_ENABLE_IN : std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic + ); +end component; + + +component pll_nx_clk256 + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); +end component; + +component pll_25 + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); end component; ------------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd index 7937a18..fc5290e 100644 --- a/nxyter/source/nxyter_registers.vhd +++ b/nxyter/source/nxyter_registers.vhd @@ -18,7 +18,8 @@ entity nxyter_registers is SLV_ADDR_IN : in std_logic_vector(15 downto 0); SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity; @@ -34,6 +35,8 @@ architecture Behavioral of nxyter_registers is begin + DEBUG_OUT <= reg_data(0)(15 downto 0); + PROC_NX_REGISTERS: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then diff --git a/nxyter/source/slave_bus.vhd b/nxyter/source/slave_bus.vhd deleted file mode 100755 index cea38f9..0000000 --- a/nxyter/source/slave_bus.vhd +++ /dev/null @@ -1,332 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.adcmv3_components.all; -use work.nxyter_components.all; - -entity slave_bus is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- RegIO signals - REGIO_ADDR_IN : in std_logic_vector(15 downto 0); -- address bus - REGIO_DATA_IN : in std_logic_vector(31 downto 0); -- data from TRB endpoint - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); -- data to TRB endpoint - REGIO_READ_ENABLE_IN : in std_logic; -- read pulse - REGIO_WRITE_ENABLE_IN : in std_logic; -- write pulse - REGIO_TIMEOUT_IN : in std_logic; -- access timed out - REGIO_DATAREADY_OUT : out std_logic; -- your data, master, as requested - REGIO_WRITE_ACK_OUT : out std_logic; -- data accepted - REGIO_NO_MORE_DATA_OUT : out std_logic; -- don't disturb me now - REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- noone here to answer your request - - -- I2C connections - SDA_IN : in std_logic; - SDA_OUT : out std_logic; - SCL_IN : in std_logic; - SCL_OUT : out std_logic; - - -- SPI connections - SPI_CS_OUT : out std_logic; - SPI_SCK_OUT : out std_logic; - SPI_SDI_IN : in std_logic; - SPI_SDO_OUT : out std_logic; - - -- Timestamp Read - NX_CLK128_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector(7 downto 0) - ); -end entity; - -architecture Behavioral of slave_bus is - --- Signals - signal slv_read : std_logic_vector(8-1 downto 0); - signal slv_write : std_logic_vector(8-1 downto 0); - signal slv_busy : std_logic_vector(8-1 downto 0); - signal slv_ack : std_logic_vector(8-1 downto 0); - signal slv_addr : std_logic_vector(8*16-1 downto 0); - signal slv_data_rd : std_logic_vector(8*32-1 downto 0); - signal slv_data_wr : std_logic_vector(8*32-1 downto 0); - signal slv_unknown_addr : std_logic_vector(8-1 downto 0); - --- SPI controller BRAM lines - signal spi_bram_addr : std_logic_vector(7 downto 0); - signal spi_bram_wr_d : std_logic_vector(7 downto 0); - signal spi_bram_rd_d : std_logic_vector(7 downto 0); - signal spi_bram_we : std_logic; - - signal spi_cs : std_logic; - signal spi_sck : std_logic; - signal spi_sdi : std_logic; - signal spi_sdo : std_logic; - signal spi_debug : std_logic_vector(31 downto 0); - - signal ctrl_lvl : std_logic_vector(31 downto 0); - signal ctrl_trg : std_logic_vector(31 downto 0); - signal ctrl_pll : std_logic_vector(15 downto 0); - - signal debug : std_logic_vector(63 downto 0); - - -- Register Stuff - -- type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); - - signal reg_data : std_logic_vector(31 downto 0); - - -begin - --- Bus handler: acts as bridge between RegIO and the FPGA internal slave bus - THE_BUS_HANDLER: trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler - 1 => x"0040", -- I2C master - 2 => x"0100", -- Timestamp Fifo - -- 3 => x"d100", -- SPI data memory - others => x"0000"), - PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler - 1 => 0, -- I2C master - 2 => 2, -- Timestamp Fifo - -- 3 => 6, -- SPI data memory - others => 0) - ) - port map( - CLK => CLK_IN, - RESET => RESET_IN, - DAT_ADDR_IN => REGIO_ADDR_IN, - DAT_DATA_IN => REGIO_DATA_IN, - DAT_DATA_OUT => REGIO_DATA_OUT, - DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_IN, - DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN, - DAT_TIMEOUT_IN => REGIO_TIMEOUT_IN, - DAT_DATAREADY_OUT => REGIO_DATAREADY_OUT, - DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, - DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, - DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, - - -- Control Registers - BUS_READ_ENABLE_OUT(0) => slv_read(0), - BUS_WRITE_ENABLE_OUT(0) => slv_write(0), - BUS_DATA_OUT(0*32+31 downto 0*32) => slv_data_wr(0*32+31 downto 0*32), - BUS_DATA_IN(0*32+31 downto 0*32) => slv_data_rd(0*32+31 downto 0*32), - BUS_ADDR_OUT(0*16+2 downto 0*16) => slv_addr(0*16+2 downto 0*16), - BUS_ADDR_OUT(0*16+15 downto 0*16+3) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_DATAREADY_IN(0) => slv_ack(0), - BUS_WRITE_ACK_IN(0) => slv_ack(0), - BUS_NO_MORE_DATA_IN(0) => slv_busy(0), - BUS_UNKNOWN_ADDR_IN(0) => slv_unknown_addr(0), - - -- I2C master - BUS_READ_ENABLE_OUT(1) => slv_read(1), - BUS_WRITE_ENABLE_OUT(1) => slv_write(1), - BUS_DATA_OUT(1*32+31 downto 1*32) => slv_data_wr(1*32+31 downto 1*32), - BUS_DATA_IN(1*32+31 downto 1*32) => slv_data_rd(1*32+31 downto 1*32), - BUS_ADDR_OUT(1*16+15 downto 1*16) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATAREADY_IN(1) => slv_ack(1), - BUS_WRITE_ACK_IN(1) => slv_ack(1), - BUS_NO_MORE_DATA_IN(1) => slv_busy(1), - BUS_UNKNOWN_ADDR_IN(1) => '0', - - -- Timestamp Fifo - BUS_READ_ENABLE_OUT(2) => slv_read(2), - BUS_WRITE_ENABLE_OUT(2) => slv_write(2), - BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), - BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+1 downto 2*16) => slv_addr(2*16+1 downto 2*16), - BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open, - BUS_TIMEOUT_OUT(2) => open, - BUS_DATAREADY_IN(2) => slv_ack(2), - BUS_WRITE_ACK_IN(2) => slv_ack(2), - BUS_NO_MORE_DATA_IN(2) => slv_busy(2), - BUS_UNKNOWN_ADDR_IN(2) => slv_unknown_addr(2), - - ---- SPI control registers - --BUS_READ_ENABLE_OUT(4) => slv_read(4), - --BUS_WRITE_ENABLE_OUT(4) => slv_write(4), - --BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32), - --BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32), - --BUS_ADDR_OUT(4*16+15 downto 4*16) => slv_addr(4*16+15 downto 4*16), - --BUS_TIMEOUT_OUT(4) => open, - --BUS_DATAREADY_IN(4) => slv_ack(4), - --BUS_WRITE_ACK_IN(4) => slv_ack(4), - --BUS_NO_MORE_DATA_IN(4) => slv_busy(4), - --BUS_UNKNOWN_ADDR_IN(4) => '0', - ---- SPI data memory - --BUS_READ_ENABLE_OUT(5) => slv_read(5), - --BUS_WRITE_ENABLE_OUT(5) => slv_write(5), - --BUS_DATA_OUT(5*32+31 downto 5*32) => slv_data_wr(5*32+31 downto 5*32), - --BUS_DATA_IN(5*32+31 downto 5*32) => slv_data_rd(5*32+31 downto 5*32), - --BUS_ADDR_OUT(5*16+15 downto 5*16) => slv_addr(5*16+15 downto 5*16), - --BUS_TIMEOUT_OUT(5) => open, - --BUS_DATAREADY_IN(5) => slv_ack(5), - --BUS_WRITE_ACK_IN(5) => slv_ack(5), - --BUS_NO_MORE_DATA_IN(5) => slv_busy(5), - --BUS_UNKNOWN_ADDR_IN(5) => '0', - - ---- debug - --STAT_DEBUG => stat - STAT_DEBUG => open - ); - -------------------------------------------------------------------------------- --- Registers -------------------------------------------------------------------------------- - nxyter_registers_1: nxyter_registers - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - - SLV_READ_IN => slv_read(0), - SLV_WRITE_IN => slv_write(0), - SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), - SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), - SLV_ADDR_IN => slv_addr(0*16+15 downto 0*16), - SLV_ACK_OUT => slv_ack(0), - SLV_NO_MORE_DATA_OUT => slv_busy(0), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) - ); - -------------------------------------------------------------------------------- --- I2C master block for accessing APVs -------------------------------------------------------------------------------- - THE_I2C_MASTER: i2c_master - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - -- Slave bus - SLV_READ_IN => slv_read(1), - SLV_WRITE_IN => slv_write(1), - SLV_BUSY_OUT => slv_busy(1), - SLV_ACK_OUT => slv_ack(1), - SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32), - SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32), - -- I2C connections - SDA_IN => SDA_IN, - SDA_OUT => SDA_OUT, - SCL_IN => SCL_IN, - SCL_OUT => SCL_OUT, - -- Status lines - STAT => open - ); -------------------------------------------------------------------------------- --- TimeStamp Read -------------------------------------------------------------------------------- - nx_timestamp_read_1: nx_timestamp_read - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - NX_CLK128_IN => NX_CLK128_IN, - NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - - SLV_READ_IN => slv_read(2), - SLV_WRITE_IN => slv_write(2), - SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), - SLV_DATA_IN => slv_data_wr(2*32+31 downto 2*32), - SLV_ADDR_IN => slv_addr(2*16+15 downto 2*16), - SLV_ACK_OUT => slv_ack(2), - SLV_NO_MORE_DATA_OUT => slv_busy(2), - SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2) - ); - ------------------------------------------------------------------------------ --- Test Register ------------------------------------------------------------------------------ --- slv_register_1: slv_register --- generic map ( --- RESET_VALUE => x"dead_beef" --- ) --- port map ( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- BUSY_IN => '0', --- --- SLV_READ_IN => slv_read(0), --- SLV_WRITE_IN => slv_write(0), --- SLV_BUSY_OUT => slv_busy(0), --- SLV_ACK_OUT => slv_ack(0), --- SLV_DATA_IN => slv_data_wr(0*32+31 downto 0*32), --- SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), --- --- REG_DATA_IN => reg_data_in, --- REG_DATA_OUT => reg_data_out, --- STAT => open --- ); --- slv_busy(0) <= '0'; - --- ------------------------------------------------------------------------------------ --- -- SPI master --- ------------------------------------------------------------------------------------ --- THE_SPI_MASTER: spi_master --- port map( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- -- Slave bus --- BUS_READ_IN => slv_read(4), --- BUS_WRITE_IN => slv_write(4), --- BUS_BUSY_OUT => slv_busy(4), --- BUS_ACK_OUT => slv_ack(4), --- BUS_ADDR_IN => slv_addr(4*16+0 downto 4*16), --- BUS_DATA_IN => slv_data_wr(4*32+31 downto 4*32), --- BUS_DATA_OUT => slv_data_rd(4*32+31 downto 4*32), --- -- SPI connections --- SPI_CS_OUT => spi_cs, --- SPI_SDI_IN => spi_sdi, --- SPI_SDO_OUT => spi_sdo, --- SPI_SCK_OUT => spi_sck, --- -- BRAM for read/write data --- BRAM_A_OUT => spi_bram_addr, --- BRAM_WR_D_IN => spi_bram_wr_d, --- BRAM_RD_D_OUT => spi_bram_rd_d, --- BRAM_WE_OUT => spi_bram_we, --- -- Status lines --- STAT => spi_debug --open --- ); --- --- ------------------------------------------------------------------------------------ --- -- data memory for SPI accesses --- ------------------------------------------------------------------------------------ --- THE_SPI_MEMORY: spi_databus_memory --- port map( --- CLK_IN => CLK_IN, --- RESET_IN => RESET_IN, --- -- Slave bus --- BUS_ADDR_IN => slv_addr(5*16+5 downto 5*16), --- BUS_READ_IN => slv_read(5), --- BUS_WRITE_IN => slv_write(5), --- BUS_ACK_OUT => slv_ack(5), --- BUS_DATA_IN => slv_data_wr(5*32+31 downto 5*32), --- BUS_DATA_OUT => slv_data_rd(5*32+31 downto 5*32), --- -- state machine connections --- BRAM_ADDR_IN => spi_bram_addr, --- BRAM_WR_D_OUT => spi_bram_wr_d, --- BRAM_RD_D_IN => spi_bram_rd_d, --- BRAM_WE_IN => spi_bram_we, --- -- Status lines --- STAT => open --- ); --- slv_busy(5) <= '0'; --- - --- unusable pins - debug(63 downto 43) <= (others => '0'); --- connected pins - debug(42 downto 0) <= (others => '0'); - --- input signals - spi_sdi <= SPI_SDI_IN; - --- Output signals - SPI_CS_OUT <= spi_cs; - SPI_SCK_OUT <= spi_sck; - SPI_SDO_OUT <= spi_sdo; - -end Behavioral; diff --git a/nxyter/source/slv_ped_thr_mem.vhd b/nxyter/source/slv_ped_thr_mem.vhd deleted file mode 100644 index 05e46e1..0000000 --- a/nxyter/source/slv_ped_thr_mem.vhd +++ /dev/null @@ -1,197 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - -library work; -use work.adcmv3_components.all; - -entity slv_ped_thr_mem is - port( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - - -- Slave bus - SLV_ADDR_IN : in std_logic_vector(10 downto 0); - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_ACK_OUT : out std_logic; - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - - -- I/O to the backend - MEM_CLK_IN : in std_logic; - MEM_ADDR_IN : in std_logic_vector(6 downto 0); - MEM_0_D_OUT : out std_logic_vector(17 downto 0); - - -- Status lines - STAT : out std_logic_vector(31 downto 0) -- DEBUG - ); -end entity; - -architecture Behavioral of slv_ped_thr_mem is - --- Signals - type STATES is (SLEEP, - RD_RDY, - RD_DEL0, - RD_DEL1, - WR_DEL0, - WR_DEL1, - WR_RDY, - RD_ACK, - WR_ACK, - DONE); - signal CURRENT_STATE, NEXT_STATE: STATES; - --- statemachine signals - signal slv_ack_x : std_logic; - signal slv_ack : std_logic; - signal store_wr_x : std_logic; - signal store_wr : std_logic; - signal store_rd_x : std_logic; - signal store_rd : std_logic; - - signal block_addr : std_logic_vector(3 downto 0); - - signal ped_data : std_logic_vector(17 downto 0); - signal mem_data : std_logic_vector(17 downto 0); - - signal mem_wr_x : std_logic; - signal mem_wr : std_logic; - signal mem_sel : std_logic; - - signal rdback_data : std_logic_vector(17 downto 0); - -begin - ---------------------------------------------------------- --- Mapping of backplanes -- ---------------------------------------------------------- --- THE_APV_ADC_MAP_MEM: apv_adc_map_mem --- port map ( --- ADDRESS(6 downto 4) => backplane_in, --- ADDRESS(3 downto 0) => slv_addr_in(10 downto 7), --- Q => block_addr --- ); --- - THE_MEM_SEL_PROC: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - mem_sel <= '1'; - rdback_data <= mem_data; - end if; - end process THE_MEM_SEL_PROC; - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- --- State memory process - STATE_MEM: process( clk_in ) - begin - if( rising_edge(clk_in) ) then - if( reset_in = '1' ) then - CURRENT_STATE <= SLEEP; - slv_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - slv_ack <= slv_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; - end process STATE_MEM; - --- Transition matrix - TRANSFORM: process( CURRENT_STATE, slv_read_in, slv_write_in ) - begin - NEXT_STATE <= SLEEP; - slv_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => if ( slv_read_in = '1' ) then - NEXT_STATE <= RD_DEL0; - store_rd_x <= '1'; - elsif( slv_write_in = '1' ) then - NEXT_STATE <= WR_DEL0; - store_wr_x <= '1'; - else - NEXT_STATE <= SLEEP; - end if; - when RD_DEL0 => NEXT_STATE <= RD_DEL1; - when RD_DEL1 => NEXT_STATE <= RD_RDY; - when RD_RDY => NEXT_STATE <= RD_ACK; - when RD_ACK => if( slv_read_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= RD_ACK; - slv_ack_x <= '1'; - end if; - when WR_DEL0 => NEXT_STATE <= WR_DEL1; - when WR_DEL1 => NEXT_STATE <= WR_RDY; - when WR_RDY => NEXT_STATE <= WR_ACK; - when WR_ACK => if( slv_write_in = '0' ) then - NEXT_STATE <= DONE; - slv_ack_x <= '1'; - else - NEXT_STATE <= WR_ACK; - slv_ack_x <= '1'; - end if; - when DONE => NEXT_STATE <= SLEEP; - - when others => NEXT_STATE <= SLEEP; - end case; - end process TRANSFORM; - ---------------------------------------------------------- --- block memories -- ---------------------------------------------------------- - -- Port A: SLV_BUS - -- Port B: state machine - THE_PED_MEM: ped_thr_true - port map( - DATAINA => slv_data_in(17 downto 0), - DATAINB => b"00_0000_0000_0000_0000", - ADDRESSA => slv_addr_in(6 downto 0), - ADDRESSB => mem_addr_in, - CLOCKA => clk_in, - CLOCKB => mem_clk_in, - CLOCKENA => '1', - CLOCKENB => '1', - WRA => mem_wr, -- BUGBUGBUG - WRB => '0', -- state machine never writes! - RESETA => reset_in, - RESETB => reset_in, - QA => mem_data, - QB => ped_data - ); --- Write signals - mem_wr_x <= '1' when ( (mem_sel = '1') and (store_wr = '1') ) else '0'; - - --- Synchronize - THE_SYNC_PROC: process(clk_in) - begin - if( rising_edge(clk_in) ) then - mem_wr <= mem_wr_x; - end if; - end process THE_SYNC_PROC; - ---------------------------------------------------------- --- output signals -- ---------------------------------------------------------- - slv_ack_out <= slv_ack; - slv_data_out <= b"0000_0000_0000_00" & rdback_data; - - mem_0_d_out <= ped_data; - - stat(31 downto 20) <= (others => '0'); - stat(19 downto 16) <= block_addr; - stat(15 downto 1) <= (others => '0'); - stat(0) <= mem_sel; - -end Behavioral; -- 2.43.0