From 73aa012633a9fa98921b1c431a319dda5cded233 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Wed, 2 Oct 2013 17:39:19 +0200
Subject: [PATCH] added better fifo handling to padiwa

---
 wasa/panda_dirc_wasa.vhd |  5 +++--
 wasa/source/ffarray.vhd  | 29 ++++++++++++++++-------------
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index 344840a..6d45c97 100644
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -16,7 +16,7 @@ entity panda_dirc_wasa is
   generic(
     PADIWA_FLAVOUR : integer := 3;
     TEMP_CORRECTION: integer := c_YES;
-    TDCTEST        : integer := c_NO
+    TDCTEST        : integer := c_YES
     );
   port(
     CON        : out std_logic_vector(16 downto 1);
@@ -485,7 +485,8 @@ end process;
 gen_ffarr : if TDCTEST = 1 generate
  THE_FFARR : entity work.ffarray
    port map(
-    CLK        => clk_osc,
+    CLK        => clk_i,
+    RESET_IN   => onewire_reset,
     SIGNAL_IN  => SPI_IN,
     
     DATA_OUT   => ffarr_data(7 downto 0),
diff --git a/wasa/source/ffarray.vhd b/wasa/source/ffarray.vhd
index e87ef08..46aaebb 100644
--- a/wasa/source/ffarray.vhd
+++ b/wasa/source/ffarray.vhd
@@ -9,6 +9,7 @@ use work.trb_net_std.all;
 entity ffarray is
   port(
     CLK        : in std_logic;
+    RESET_IN   : in std_logic;    
     SIGNAL_IN  : in std_logic;
     
     DATA_OUT   : out std_logic_vector(7 downto 0);
@@ -22,7 +23,7 @@ architecture ffarray_arch of ffarray is
 signal CLKt  : std_logic_vector(3 downto 0);
 signal CLKa  : std_logic_vector(7 downto 0);
 
-signal final     : std_logic_vector(7 downto 0);
+signal final, final1, final2     : std_logic_vector(7 downto 0);
 signal final_t   : std_logic_vector(7 downto 0);
 
 type ffarr_t is array(0 to 3) of std_logic_vector(7 downto 0);
@@ -63,20 +64,22 @@ gen_ffarr_first : for i in 0 to 7 generate
   ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0));
 end generate;
 
-
--- gen_ffarr_j : for j in 1 to 3 generate
---   gen_ffarr_i : for i in 0 to 7 generate
---     ffarr(j)(i) <= ffarr(j-1)(i) when rising_edge(CLKa(maximum(i-j*2-1,0)));
---   end generate;
--- end generate;
+process begin
+  wait until falling_edge(CLK);
+  final_t <= ffarr(2);
+end process;
 
 
 process begin
   wait until rising_edge(CLK);
-  final_t <= ffarr(2);
-  if ((not and_all(final_t) and or_all(final_t)) = '1') then
+  final1 <= final_t;
+  final2 <= ffarr(2);
+  if (final1(7) xor final1(0)) = '1' then
+    fifo_write <= '1';
+    final <= final1;
+  elsif (final2(7) xor final2(0)) = '1' then
     fifo_write <= '1';
-    final <= final_t;
+    final <= final2;
   else
     fifo_write <= '0';
   end if;
@@ -86,12 +89,12 @@ end process;
 THE_FIFO : entity work.fifo_1kx8
   port map(
     Data        => final,
-    WrClock     => CLK,    --wrong!
+    WrClock     => CLK,
     RdClock     => CLK, 
     WrEn        => fifo_write, 
     RdEn        => READ_IN,
-    Reset       => '0',
-    RPReset     => '0', 
+    Reset       => RESET_IN,
+    RPReset     => RESET_IN, 
     Q           => DATA_OUT,
     Empty       => EMPTY_OUT,
     Full        => open,
-- 
2.43.0