From 73bfea94ccc8ffb714043b67078a3b115e3419d0 Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 5 Aug 2020 20:25:48 +0200 Subject: [PATCH] endpoint_hades_full_gbe: Add Xilinx DNA interface --- trb_net16_endpoint_hades_full_gbe.vhd | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/trb_net16_endpoint_hades_full_gbe.vhd b/trb_net16_endpoint_hades_full_gbe.vhd index a43519b..1bc5223 100644 --- a/trb_net16_endpoint_hades_full_gbe.vhd +++ b/trb_net16_endpoint_hades_full_gbe.vhd @@ -45,7 +45,7 @@ entity trb_net16_endpoint_hades_full_gbe is REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; - REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR + REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR,c_I2C,c_XDNA REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; CLOCK_FREQUENCY : integer range 1 to 200 := 100; USE_GBE : integer range 0 to 1 := c_YES @@ -900,6 +900,25 @@ begin REGIO_ONEWIRE_MONITOR_OUT <= '0'; end generate; + gen_XilinxDNA : if REGIO_USE_1WIRE_INTERFACE = c_XDNA generate + + REGIO_IDRAM_DATA_OUT <= (others => '0'); + STAT_ONEWIRE <= (others => '0'); + REGIO_ONEWIRE_MONITOR_OUT <= '0'; + REGIO_ONEWIRE_INOUT <= '0'; + + XilinxDNA : entity work.trb_net_xdna + port map( + CLK => CLK, + RESET => RESET, + DATA_OUT => ONEWIRE_DATA, + ADDR_OUT => ONEWIRE_ADDR, + WRITE_OUT=> ONEWIRE_WRITE, + TEMP_OUT => temperature, + ID_OUT => unique_id_out_i + ); + end generate; + gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate -- 2.43.0