From 74679c05ac2cb2c6340a05fcc5dd168fc24a3c74 Mon Sep 17 00:00:00 2001
From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 27 Feb 2015 16:03:04 +0100
Subject: [PATCH] DEBUG should be in clk_rd aka ADC clock domain

---
 ADC/source/adc_ad9219.vhd | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 26e41f6..488f7ea 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -321,7 +321,7 @@ begin
 
     proc_debug : process
     begin
-      wait until rising_edge(CLK);
+      wait until rising_edge(clk_rd);
       state_q(i)                           <= state(i);
       counter_q(i)                         <= counter(i);
       DEBUG(i * 32 + 31 downto i * 32 + 4) <= std_logic_vector(counter_q(i));
-- 
2.43.0