From 7476ce3118822d67e740ea5392f897a1f7220e76 Mon Sep 17 00:00:00 2001 From: Tobias Weber Date: Mon, 23 Feb 2015 10:19:16 +0100 Subject: [PATCH] Include time walk measurement into existing design --- base/trb3_periph_mupix.lpf | 40 ++++++++++++------------- mupix/sources/MuPix3_board.vhd | 32 ++++++++++++++++---- mupix/sources/MuPix3_boardinterface.vhd | 23 ++++++++++---- mupix/sources/mupix_components.vhd | 40 ++++++++++++++++++++++--- mupix/trb3_periph.prj | 3 ++ mupix/trb3_periph.vhd | 10 ++++--- 6 files changed, 109 insertions(+), 39 deletions(-) diff --git a/base/trb3_periph_mupix.lpf b/base/trb3_periph_mupix.lpf index 5b651e2..735f5e1 100644 --- a/base/trb3_periph_mupix.lpf +++ b/base/trb3_periph_mupix.lpf @@ -134,16 +134,16 @@ LOCATE COMP "fpga_led_to_board0_3" SITE "Y7"; DEFINE PORT GROUP "fpga_led0_group" "fpga_led_to_board0*"; IOBUF GROUP "fpga_led0_group" IO_TYPE=LVCMOS25; -LOCATE COMP "fpga_aux_to_board0_0" SITE "T7"; -LOCATE COMP "fpga_aux_to_board0_1" SITE "R6"; -LOCATE COMP "fpga_aux_to_board0_2" SITE "K2"; -LOCATE COMP "fpga_aux_to_board0_3" SITE "T8"; -LOCATE COMP "fpga_aux_to_board0_4" SITE "K4"; -LOCATE COMP "fpga_aux_to_board0_5" SITE "K1"; -LOCATE COMP "fpga_aux_to_board0_6" SITE "E1"; -LOCATE COMP "fpga_aux_to_board0_7" SITE "K5"; -LOCATE COMP "fpga_aux_to_board0_8" SITE "B2"; -LOCATE COMP "fpga_aux_to_board0_9" SITE "B3"; +LOCATE COMP "fpga_aux_from_board0_0" SITE "T7"; +LOCATE COMP "fpga_aux_from_board0_1" SITE "R6"; +LOCATE COMP "fpga_aux_from_board0_2" SITE "K2"; +LOCATE COMP "fpga_aux_from_board0_3" SITE "T8"; +LOCATE COMP "fpga_aux_from_board0_4" SITE "K4"; +LOCATE COMP "fpga_aux_from_board0_5" SITE "K1"; +LOCATE COMP "fpga_aux_to_board0_0" SITE "E1"; +LOCATE COMP "fpga_aux_to_board0_1" SITE "K5"; +LOCATE COMP "fpga_aux_to_board0_2" SITE "B2"; +LOCATE COMP "fpga_aux_to_board0_3" SITE "B3"; DEFINE PORT GROUP "fpga_aux0_group" "fpga_aux_to_board0*"; IOBUF GROUP "fpga_aux0_group" IO_TYPE=LVCMOS25; @@ -239,16 +239,16 @@ LOCATE COMP "fpga_led_to_board1_3" SITE "H25"; DEFINE PORT GROUP "fpga_led1_group" "fpga_led_to_board1*"; IOBUF GROUP "fpga_led1_group" IO_TYPE=LVCMOS25; -LOCATE COMP "fpga_aux_to_board1_0" SITE "AE25"; -LOCATE COMP "fpga_aux_to_board1_1" SITE "AE24"; -LOCATE COMP "fpga_aux_to_board1_2" SITE "W23"; -LOCATE COMP "fpga_aux_to_board1_3" SITE "AF24"; -LOCATE COMP "fpga_aux_to_board1_4" SITE "AA25"; -LOCATE COMP "fpga_aux_to_board1_5" SITE "W22"; -LOCATE COMP "fpga_aux_to_board1_6" SITE "AA26"; -LOCATE COMP "fpga_aux_to_board1_7" SITE "Y24"; -LOCATE COMP "fpga_aux_to_board1_8" SITE "W21"; -LOCATE COMP "fpga_aux_to_board1_9" SITE "W20"; +LOCATE COMP "fpga_aux_from_board1_0" SITE "AE25"; +LOCATE COMP "fpga_aux_from_board1_1" SITE "AE24"; +LOCATE COMP "fpga_aux_from_board1_2" SITE "W23"; +LOCATE COMP "fpga_aux_from_board1_3" SITE "AF24"; +LOCATE COMP "fpga_aux_from_board1_4" SITE "AA25"; +LOCATE COMP "fpga_aux_from_board1_5" SITE "W22"; +LOCATE COMP "fpga_aux_to_board1_0" SITE "AA26"; +LOCATE COMP "fpga_aux_to_board1_1" SITE "Y24"; +LOCATE COMP "fpga_aux_to_board1_2" SITE "W21"; +LOCATE COMP "fpga_aux_to_board1_3" SITE "W20"; DEFINE PORT GROUP "fpga_aux1_group" "fpga_aux_to_board1*"; IOBUF GROUP "fpga_aux01_group" IO_TYPE=LVCMOS25; diff --git a/mupix/sources/MuPix3_board.vhd b/mupix/sources/MuPix3_board.vhd index 1e8bdbd..fdeca4c 100644 --- a/mupix/sources/MuPix3_board.vhd +++ b/mupix/sources/MuPix3_board.vhd @@ -16,6 +16,7 @@ entity MuPix3_Board is port( --Clock signal clk : in std_logic; + fast_clk : in std_logic; reset : in std_logic; --signals to and from MuPix 3 chip/board DACS timestamp_from_mupix : in std_logic_vector(7 downto 0); @@ -25,7 +26,7 @@ entity MuPix3_Board is sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; hbus_from_mupix : in std_logic; - fpga_aux_from_board : in std_logic_vector(9 downto 0); + fpga_aux_from_board : in std_logic_vector(5 downto 0); ldpix_to_mupix : out std_logic; ldcol_to_mupix : out std_logic; timestamp_to_mupix : out std_logic_vector(7 downto 0); @@ -41,7 +42,7 @@ entity MuPix3_Board is spi_clk_to_board : out std_logic; spi_ld_to_board : out std_logic; fpga_led_to_board : out std_logic_vector(3 downto 0); - fpga_aux_to_board : out std_logic_vector(9 downto 0); + fpga_aux_to_board : out std_logic_vector(3 downto 0); --resets timestampreset_in : in std_logic; @@ -84,7 +85,7 @@ architecture Behavioral of MuPix3_Board is --signal declarations -- Bus Handler - constant NUM_PORTS : integer := 8; + constant NUM_PORTS : integer := 9; signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); @@ -120,7 +121,8 @@ architecture Behavioral of MuPix3_Board is signal sout_c_from_mupix_sync : std_logic; signal sout_d_from_mupix_sync : std_logic; signal hbus_from_mupix_sync : std_logic; - signal fpga_aux_from_board_sync : std_logic_vector(9 downto 0); + signal fpga_aux_from_board_sync : std_logic_vector(5 downto 0); + signal szintilator_sync : std_logic; @@ -143,6 +145,7 @@ begin -- Behavioral 5 => x"0300", -- Event Buffer 6 => x"0100", -- Trigger Handler 7 => x"0200", -- Board Interface + 8 => x"0400", -- TimeWalk Measurement others => x"0000"), PORT_ADDR_MASK @@ -153,7 +156,8 @@ begin -- Behavioral 4 => 8, -- HitBus Histograms 5 => 8, -- Event Buffer 6 => 8, -- Trigger Handler - 7 => 8, -- Board Interface + 7 => 8, -- Board Interface + 8 => 8, -- TimeWalk Measurement others => 0) --PORT_MASK_ENABLE => 1 @@ -193,6 +197,7 @@ begin -- Behavioral board_interface_1: entity work.board_interface port map ( clk_in => clk, + fast_clk_in => fast_clk, timestamp_from_mupix => timestamp_from_mupix, rowaddr_from_mupix => rowaddr_from_mupix, coladdr_from_mupix => coladdr_from_mupix, @@ -209,6 +214,7 @@ begin -- Behavioral sout_d_from_mupix_sync => sout_d_from_mupix_sync, hbus_from_mupix_sync => hbus_from_mupix_sync, fpga_aux_from_board_sync => fpga_aux_from_board_sync, + szintilator_sync => szintilator_sync, SLV_READ_IN => slv_read(7), SLV_WRITE_IN => slv_write(7), @@ -379,5 +385,21 @@ begin -- Behavioral SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6)); + TimeWalkWithFiFo_1: entity work.TimeWalkWithFiFo + port map ( + trb_slv_clock => clk, + fast_clk => fast_clk, + reset => reset, + hitbus => hbus_from_mupix_sync, + szintillator_trigger => szintilator_sync, + SLV_READ_IN => slv_read(8), + SLV_WRITE_IN => slv_write(8), + SLV_DATA_OUT => slv_data_rd(8*32+31 downto 8*32), + SLV_DATA_IN => slv_data_wr(8*32+31 downto 8*32), + SLV_ADDR_IN => slv_addr(8*16+15 downto 8*16), + SLV_ACK_OUT => slv_ack(8), + SLV_NO_MORE_DATA_OUT => slv_no_more_data(8), + SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8)); + end Behavioral; diff --git a/mupix/sources/MuPix3_boardinterface.vhd b/mupix/sources/MuPix3_boardinterface.vhd index b6bdb40..07ec510 100644 --- a/mupix/sources/MuPix3_boardinterface.vhd +++ b/mupix/sources/MuPix3_boardinterface.vhd @@ -14,6 +14,7 @@ use work.mupix_components.all; entity board_interface is port( clk_in : in std_logic; + fast_clk_in : in std_logic; -- signals from mupix timestamp_from_mupix : in std_logic_vector(7 downto 0); rowaddr_from_mupix : in std_logic_vector(5 downto 0); @@ -22,7 +23,7 @@ entity board_interface is sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; hbus_from_mupix : in std_logic; - fpga_aux_from_board : in std_logic_vector(9 downto 0); + fpga_aux_from_board : in std_logic_vector(5 downto 0); --synced (and inverted) signals timestamp_from_mupix_sync : out std_logic_vector(7 downto 0); rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0); @@ -31,7 +32,8 @@ entity board_interface is sout_c_from_mupix_sync : out std_logic; sout_d_from_mupix_sync : out std_logic; hbus_from_mupix_sync : out std_logic; - fpga_aux_from_board_sync : out std_logic_vector(9 downto 0); + fpga_aux_from_board_sync : out std_logic_vector(5 downto 0); + szintilator_sync : out std_logic; --Trb Slv-Bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -51,11 +53,24 @@ architecture rtl of board_interface is begin +-- fast synchronize for hitbus and szintilator + fast_sync: process (fast_clk_in) is + begin -- process fast_sync + if rising_edge(fast_clk_in) then + szintilator_sync <= fpga_aux_from_board(0); + if invert_signals_int = '1' then + hbus_from_mupix_sync <= hbus_from_mupix; + else + hbus_from_mupix_sync <= not hbus_from_mupix; + end if; + end if; + end process fast_sync; -- Synchronize input signals process begin wait until rising_edge(clk_in); + fpga_aux_from_board_sync <= fpga_aux_from_board; if invert_signals_int = '1' then timestamp_from_mupix_sync <= not timestamp_from_mupix; rowaddr_from_mupix_sync <= not rowaddr_from_mupix; @@ -63,8 +78,6 @@ begin sout_c_from_mupix_sync <= not sout_c_from_mupix; sout_d_from_mupix_sync <= not sout_d_from_mupix; priout_from_mupix_sync <= priout_from_mupix; --is inverted on the chip - hbus_from_mupix_sync <= hbus_from_mupix; - fpga_aux_from_board_sync <= fpga_aux_from_board; else timestamp_from_mupix_sync <= timestamp_from_mupix; rowaddr_from_mupix_sync <= rowaddr_from_mupix; @@ -72,8 +85,6 @@ begin sout_c_from_mupix_sync <= sout_c_from_mupix; sout_d_from_mupix_sync <= sout_d_from_mupix; priout_from_mupix_sync <= not priout_from_mupix; --is inverted on the chip - hbus_from_mupix_sync <= not hbus_from_mupix; - fpga_aux_from_board_sync <= not fpga_aux_from_board; end if; end process; diff --git a/mupix/sources/mupix_components.vhd b/mupix/sources/mupix_components.vhd index ea5e4e2..1d6a81a 100644 --- a/mupix/sources/mupix_components.vhd +++ b/mupix/sources/mupix_components.vhd @@ -9,6 +9,7 @@ package mupix_components is component MuPix3_Board port ( clk : in std_logic; + fast_clk : in std_logic; reset : in std_logic; timestamp_from_mupix : in std_logic_vector(7 downto 0); rowaddr_from_mupix : in std_logic_vector(5 downto 0); @@ -17,7 +18,7 @@ package mupix_components is sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; hbus_from_mupix : in std_logic; - fpga_aux_from_board : in std_logic_vector(9 downto 0); + fpga_aux_from_board : in std_logic_vector(5 downto 0); ldpix_to_mupix : out std_logic; ldcol_to_mupix : out std_logic; timestamp_to_mupix : out std_logic_vector(7 downto 0); @@ -33,7 +34,7 @@ package mupix_components is spi_clk_to_board : out std_logic; spi_ld_to_board : out std_logic; fpga_led_to_board : out std_logic_vector(3 downto 0); - fpga_aux_to_board : out std_logic_vector(9 downto 0); + fpga_aux_to_board : out std_logic_vector(3 downto 0); timestampreset_in : in std_logic; eventcounterreset_in : in std_logic; TIMING_TRG_IN : in std_logic; @@ -262,6 +263,7 @@ package mupix_components is component board_interface is port ( clk_in : in std_logic; + fast_clk_in : in std_logic; timestamp_from_mupix : in std_logic_vector(7 downto 0); rowaddr_from_mupix : in std_logic_vector(5 downto 0); coladdr_from_mupix : in std_logic_vector(5 downto 0); @@ -269,7 +271,7 @@ package mupix_components is sout_c_from_mupix : in std_logic; sout_d_from_mupix : in std_logic; hbus_from_mupix : in std_logic; - fpga_aux_from_board : in std_logic_vector(9 downto 0); + fpga_aux_from_board : in std_logic_vector(5 downto 0); timestamp_from_mupix_sync : out std_logic_vector(7 downto 0); rowaddr_from_mupix_sync : out std_logic_vector(5 downto 0); coladdr_from_mupix_sync : out std_logic_vector(5 downto 0); @@ -277,7 +279,8 @@ package mupix_components is sout_c_from_mupix_sync : out std_logic; sout_d_from_mupix_sync : out std_logic; hbus_form_mupix_sync : out std_logic; - fpga_aux_from_board_sync : out std_logic_vector(9 downto 0); + fpga_aux_from_board_sync : out std_logic_vector(5 downto 0); + szintilator_sync : out std_logic; SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -303,5 +306,34 @@ package mupix_components is SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic); end component resethandler; + + component TimeWalkWithFiFo is + port ( + trb_slv_clock : in std_logic; + fast_clk : in std_logic; + reset : in std_logic; + hitbus : in std_logic; + szintillator_trigger : in std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic); + end component TimeWalkWithFiFo; + + component TimeWalk is + port ( + clk : in std_logic; + reset : in std_logic; + hitbus : in std_logic; + hitbus_timeout : in std_logic_vector(31 downto 0); + szintillator_trigger : in std_logic; + readyToWrite : in std_logic; + measurementFinished : out std_logic; + measurementData : out std_logic_vector(31 downto 0)); + end component TimeWalk; end mupix_components; diff --git a/mupix/trb3_periph.prj b/mupix/trb3_periph.prj index 1833d12..71067e9 100644 --- a/mupix/trb3_periph.prj +++ b/mupix/trb3_periph.prj @@ -157,3 +157,6 @@ add_file -vhdl -lib "work" "sources/MuPix3_boardinterface.vhd" add_file -vhdl -lib "work" "sources/TriggerHandler.vhd" add_file -vhdl -lib "work" "cores/fifo_32x2k.vhd" add_file -vhdl -lib "work" "sources/ResetHandler.vhd" +add_file -vhdl -lib "work" "cores/fifo_4k32_async.vhd" +add_file -vhdl -lib "work" "sources/TimeWalk.vhd" +add_file -vhdl -lib "work" "sources/TimeWalkWithFiFo.vhd" \ No newline at end of file diff --git a/mupix/trb3_periph.vhd b/mupix/trb3_periph.vhd index 0c99709..6558228 100644 --- a/mupix/trb3_periph.vhd +++ b/mupix/trb3_periph.vhd @@ -52,7 +52,7 @@ entity trb3_periph is sout_c_from_mupix0 : in std_logic; sout_d_from_mupix0 : in std_logic; hbus_from_mupix0 : in std_logic; - fpga_aux_from_board0 : in std_logic_vector(9 downto 0); + fpga_aux_from_board0 : in std_logic_vector(5 downto 0); ldpix_to_mupix0 : out std_logic; ldcol_to_mupix0 : out std_logic; timestamp_to_mupix0 : out std_logic_vector(7 downto 0); @@ -68,7 +68,7 @@ entity trb3_periph is spi_clk_to_board0 : out std_logic; spi_ld_to_board0 : out std_logic; fpga_led_to_board0 : out std_logic_vector(3 downto 0); - fpga_aux_to_board0 : out std_logic_vector(9 downto 0); + fpga_aux_to_board0 : out std_logic_vector(3 downto 0); --Connections to Sensorboard 1 timestamp_from_mupix1 : in std_logic_vector(7 downto 0); @@ -78,7 +78,7 @@ entity trb3_periph is sout_c_from_mupix1 : in std_logic; sout_d_from_mupix1 : in std_logic; hbus_from_mupix1 : in std_logic; - fpga_aux_from_board1 : in std_logic_vector(9 downto 0); + fpga_aux_from_board1 : in std_logic_vector(5 downto 0); ldpix_to_mupix1 : out std_logic; ldcol_to_mupix1 : out std_logic; timestamp_to_mupix1 : out std_logic_vector(7 downto 0); @@ -94,7 +94,7 @@ entity trb3_periph is spi_clk_to_board1 : out std_logic; spi_ld_to_board1 : out std_logic; fpga_led_to_board1 : out std_logic_vector(3 downto 0); - fpga_aux_to_board1 : out std_logic_vector(9 downto 0); + fpga_aux_to_board1 : out std_logic_vector(3 downto 0); --------------------------------------------------------------------------- @@ -696,6 +696,7 @@ begin MuPix3_Board_0 : MuPix3_Board port map ( clk => clk_100_i, + fast_clk => clk_200_i, reset => reset_i, timestamp_from_mupix => timestamp_from_mupix0, rowaddr_from_mupix => rowaddr_from_mupix0, @@ -757,6 +758,7 @@ begin MuPix3_Board_1 : MuPix3_Board port map ( clk => clk_100_i, + fast_clk => clk_200_i, reset => reset_i, timestamp_from_mupix => timestamp_from_mupix1, rowaddr_from_mupix => rowaddr_from_mupix1, -- 2.43.0