From 748e7acbf9c2632f5ddb8116b22ca884bc70a5ad Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 26 Sep 2017 10:31:35 +0200 Subject: [PATCH] Design for new SFP-AddOn-v2 --- hub/config.vhd | 8 +- hub/config_compile_frankfurt.pl | 2 +- hub/trb3sc_hub.lpf | 97 ++++++--- hub/trb3sc_hub.prj | 120 ++++++----- hub/trb3sc_hub.vhd | 332 ++++++++++++++++++++++--------- pinout/basic_constraints.lpf | 2 +- pinout/trb3sc_hub.lpf | 339 ++++++++++++++++++++++++++++++++ 7 files changed, 712 insertions(+), 188 deletions(-) create mode 100644 pinout/trb3sc_hub.lpf diff --git a/hub/config.vhd b/hub/config.vhd index 06da8ff..4df0e1f 100644 --- a/hub/config.vhd +++ b/hub/config.vhd @@ -13,7 +13,7 @@ package config is --design options: backplane or front SFP, with or without GBE constant USE_BACKPLANE : integer := c_NO; - constant INCLUDE_GBE : integer := c_NO; + constant INCLUDE_GBE : integer := c_YES; --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; @@ -71,6 +71,7 @@ package config is type hub_ct is array(0 to 16) of integer; type hub_cfg_t is array(0 to 3) of hub_ct; type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); + type intlist_t is array(0 to 7) of integer; --order: no backplane, no GBE 8x AddOn, SFP downlink, SFP uplink @@ -93,7 +94,6 @@ package config is (0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0), (0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0)); - constant INTERNAL_NUM : integer; constant INTERFACE_NUM : integer; constant IS_UPLINK : hub_ct; constant IS_DOWNLINK : hub_ct; @@ -102,8 +102,7 @@ package config is ------------------------------------------------------------------------------ --Select settings by configuration ------------------------------------------------------------------------------ - type intlist_t is array(0 to 7) of integer; - type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000"; constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); @@ -128,7 +127,6 @@ package body config is constant CFG_MODE : integer := INCLUDE_GBE*2 + USE_BACKPLANE; - constant HARDWARE_INFO : std_logic_vector (31 downto 0) := HARDWARE_INFO_ARR(INCLUDE_TDC); constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); diff --git a/hub/config_compile_frankfurt.pl b/hub/config_compile_frankfurt.pl index e9fa960..57ac2c7 100644 --- a/hub/config_compile_frankfurt.pl +++ b/hub/config_compile_frankfurt.pl @@ -1,4 +1,4 @@ -TOPNAME => "trb3sc_hubaddon", +TOPNAME => "trb3sc_hub", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05.gsi.de", lattice_path => '/d/jspc29/lattice/diamond/3.9_x64', diff --git a/hub/trb3sc_hub.lpf b/hub/trb3sc_hub.lpf index c70d9c3..bd9dbe5 100644 --- a/hub/trb3sc_hub.lpf +++ b/hub/trb3sc_hub.lpf @@ -1,36 +1,77 @@ -LOCATE COMP "THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST" SITE "PCSC" ; -REGION "MEDIA_DOWN1" "R102C40D" 13 100; -LOCATE UGROUP "THE_MEDIA_4_DOWN/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; -MULTICYCLE TO CELL "THE_MEDIA_4_DOWN/sci*" 20 ns; -MULTICYCLE FROM CELL "THE_MEDIA_4_DOWN/sci*" 20 ns; -MULTICYCLE TO CELL "THE_MEDIA_4_DOWN/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "THE_MEDIA_4_DOWN/sci_write_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_write_i"; -BLOCK PATH TO CLKNET "THE_MEDIA_4_DOWN/sci_read_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOWN/sci_read_i"; -MULTICYCLE TO CLKNET "THE_MEDIA_4_DOWN/sci_read_i" 15 ns; -MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOWN/sci_read_i" 15 ns; -MULTICYCLE TO CLKNET "THE_MEDIA_4_DOWN/sci_write_i" 15 ns; -MULTICYCLE FROM CLKNET "THE_MEDIA_4_DOWN/sci_write_i" 15 ns; +REGION "MEDIA_DOWN1" "R102C40D" 13 100; +LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; +FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz; -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; -MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i"; -BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i"; -MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; -MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; -MULTICYCLE TO CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; -MULTICYCLE FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; +MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; + +MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; + + +MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -MULTICYCLE TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; -MAXDELAY TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; # PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; @@ -52,4 +93,4 @@ MAXDELAY TO ASIC THE_MEDIA_4_DOWN/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; # PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; # PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; # FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps -# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps \ No newline at end of file +# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps diff --git a/hub/trb3sc_hub.prj b/hub/trb3sc_hub.prj index bea4539..b39d4f2 100644 --- a/hub/trb3sc_hub.prj +++ b/hub/trb3sc_hub.prj @@ -12,7 +12,7 @@ set_option -part_companion "" # compilation/mapping options set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 -set_option -top_module "trb3sc_hubaddon" +set_option -top_module "trb3sc_hub" set_option -resource_sharing false # map options @@ -40,7 +40,7 @@ set_option -write_apr_constraint 0 # set result format/file last project -result_format "edif" -project -result_file "workdir/trb3sc_hubaddon.edf" +project -result_file "workdir/trb3sc_hub.edf" #implementation attributes @@ -59,8 +59,8 @@ add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" @@ -138,8 +138,10 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -188,64 +190,56 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" #GbE -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd" -#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" -#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v" -#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v" -#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v" -#add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" @@ -258,7 +252,7 @@ add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" -add_file -vhdl -lib work "./trb3sc_hubaddon.vhd" +add_file -vhdl -lib work "./trb3sc_hub.vhd" #add_file -fpga_constraint "./synplify.fdc" diff --git a/hub/trb3sc_hub.vhd b/hub/trb3sc_hub.vhd index e913bcb..7fb6ec7 100644 --- a/hub/trb3sc_hub.vhd +++ b/hub/trb3sc_hub.vhd @@ -22,8 +22,8 @@ entity trb3sc_hub is --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); BACK_LVDS : inout std_logic_vector( 1 downto 0); - BACK_GPIO : inout std_logic_vector(15 downto 0); - + BACK_GPIO : inout std_logic_vector( 3 downto 0); + --LED LED_GREEN : out std_logic; LED_YELLOW : out std_logic; @@ -102,13 +102,13 @@ architecture trb3sc_arch of trb3sc_hub is signal debug_clock_reset : std_logic_vector(31 downto 0); --Media Interface - signal med2int : med2int_array_t(0 to INTERFACE_NUM-1); - signal int2med : int2med_array_t(0 to INTERFACE_NUM-1); + signal med2int : med2int_array_t(0 to 10); + signal int2med : int2med_array_t(0 to 10); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); - signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bustools_rx, + signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx, bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx : CTRLBUS_RX; - signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bustools_tx, + signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; @@ -149,19 +149,21 @@ architecture trb3sc_arch of trb3sc_hub is signal mc_unique_id : std_logic_vector(63 downto 0); signal reset_via_gbe : std_logic := '0'; - signal med_dataready_out : std_logic_vector (mii-1 downto 0); - signal med_data_out : std_logic_vector (mii*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_out : std_logic_vector (mii*c_NUM_WIDTH-1 downto 0); - signal med_read_in : std_logic_vector (mii-1 downto 0); - signal med_dataready_in : std_logic_vector (mii-1 downto 0); - signal med_data_in : std_logic_vector (mii*c_DATA_WIDTH-1 downto 0); - signal med_packet_num_in : std_logic_vector (mii*c_NUM_WIDTH-1 downto 0); - signal med_read_out : std_logic_vector (mii-1 downto 0); - signal med_stat_op : std_logic_vector (mii*16+15 downto 0); - signal med_ctrl_op : std_logic_vector (mii*16-1 downto 0); + signal med_dataready_out : std_logic_vector (11-1 downto 0); + signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (11-1 downto 0); + signal med_dataready_in : std_logic_vector (11-1 downto 0); + signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (11-1 downto 0); + signal med_stat_op : std_logic_vector (11*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); signal rdack, wrack : std_logic; - + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(17 downto 0); + attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; @@ -208,7 +210,7 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- PCSA Uplink when backplane is used --------------------------------------------------------------------------- gen_PCSA : if USE_BACKPLANE = c_YES generate - THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync + THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync generic map( SERDES_NUM => 0, IS_SYNC_SLAVE => c_YES @@ -244,16 +246,182 @@ end generate; --------------------------------------------------------------------------- -- PCSB Uplink without backplane and 3/4 downlinks ---------------------------------------------------------------------------- - +--------------------------------------------------------------------------- +gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + + +gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4_slave3 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; --------------------------------------------------------------------------- -- PCSC 4 downlinks --------------------------------------------------------------------------- - THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4 + THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(2), + MEDIA_MED2INT(1) => med2int(3), + MEDIA_MED2INT(2) => med2int(0), + MEDIA_MED2INT(3) => med2int(1), + MEDIA_INT2MED(0) => int2med(2), + MEDIA_INT2MED(1) => int2med(3), + MEDIA_INT2MED(2) => int2med(0), + MEDIA_INT2MED(3) => int2med(1), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + + --Control Interface + BUS_RX => bussci3_rx, + BUS_TX => bussci3_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- PCSD GBE or 2 downlinks +--------------------------------------------------------------------------- +gen_PCSD : if INCLUDE_GBE = c_NO generate + THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_4 generic map( IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), - IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + IS_USED => (c_YES,c_YES ,c_NO ,c_NO) ) port map( CLK_REF_FULL => clk_full_osc, @@ -263,14 +431,10 @@ end generate; CLEAR => clear_i, --Internal Connection - MEDIA_MED2INT(0) => med2int(2), - MEDIA_MED2INT(1) => med2int(3), - MEDIA_MED2INT(2) => med2int(0), - MEDIA_MED2INT(3) => med2int(1), - MEDIA_INT2MED(0) => int2med(2), - MEDIA_INT2MED(1) => int2med(3), - MEDIA_INT2MED(2) => int2med(0), - MEDIA_INT2MED(3) => int2med(1), + MEDIA_MED2INT(0) => med2int(8), + MEDIA_MED2INT(1) => med2int(7), + MEDIA_INT2MED(0) => int2med(8), + MEDIA_INT2MED(1) => int2med(7), --Sync operation RX_DLM => open, @@ -279,34 +443,24 @@ end generate; TX_DLM_WORD => open, --SFP Connection - SD_PRSNT_N_IN(0) => HUB_MOD0(3), - SD_PRSNT_N_IN(1) => HUB_MOD0(4), - SD_PRSNT_N_IN(2) => HUB_MOD0(1), - SD_PRSNT_N_IN(3) => HUB_MOD0(2), - - SD_LOS_IN(0) => HUB_LOS(3), - SD_LOS_IN(1) => HUB_LOS(4), - SD_LOS_IN(2) => HUB_LOS(1), - SD_LOS_IN(3) => HUB_LOS(2), - - SD_TXDIS_OUT(0) => HUB_TXDIS(3), - SD_TXDIS_OUT(1) => HUB_TXDIS(4), - SD_TXDIS_OUT(2) => HUB_TXDIS(1), - SD_TXDIS_OUT(3) => HUB_TXDIS(2), + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(1) => HUB_MOD0(8), + + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(1) => HUB_LOS(8), + + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + SD_TXDIS_OUT(1) => HUB_TXDIS(8), --Control Interface - BUS_RX => bussci3_rx, - BUS_TX => bussci3_tx, + BUS_RX => bussci4_rx, + BUS_TX => bussci4_tx, -- Status and control port STAT_DEBUG => open, --med_stat_debug(63 downto 0), CTRL_DEBUG => open - ); - ---------------------------------------------------------------------------- --- PCSD GBE or 2 downlinks ---------------------------------------------------------------------------- - + ); +end generate; --------------------------------------------------------------------------- -- GbE @@ -351,7 +505,7 @@ gen_GBE : if INCLUDE_GBE = 1 generate RESET => reset_i, GSR_N => GSR_N, - TRIGGER_IN => TRIG_LEFT, + TRIGGER_IN => '0', SD_PRSNT_N_IN(0) => SFP_MOD0(0), SD_LOS_IN(0) => SFP_LOS(0), @@ -412,9 +566,9 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate HUB_USED_CHANNELS => (1,1,0,1), INIT_ADDRESS => INIT_ADDRESS, MII_NUMBER => INTERFACE_NUM, - MII_IS_UPLINK => MII_IS_UPLINK, - MII_IS_DOWNLINK => MII_IS_DOWNLINK, - MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, USE_ONEWIRE => c_YES, HARDWARE_VERSION => HARDWARE_INFO, INCLUDED_FEATURES => INCLUDED_FEATURES, @@ -428,8 +582,8 @@ gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate CLK_EN => '1', --Media interfacces - MEDIA_MED2INT => med2int, - MEDIA_INT2MED => int2med, + MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1 ), + MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1), --Event information coming from CTSCTS_READOUT_TYPE_OUT CTS_NUMBER_OUT => cts_number, @@ -497,49 +651,48 @@ gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate HUB_USED_CHANNELS => (1,1,0,1), INIT_ADDRESS => INIT_ADDRESS, MII_NUMBER => INTERFACE_NUM, - MII_IS_UPLINK => MII_IS_UPLINK, - MII_IS_DOWNLINK => MII_IS_DOWNLINK, - MII_IS_UPLINK_ONLY => MII_IS_UPLINK_ONLY, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, USE_ONEWIRE => c_YES, HARDWARE_VERSION => HARDWARE_INFO, INCLUDED_FEATURES => INCLUDED_FEATURES, INIT_ENDPOINT_ID => x"0001", CLOCK_FREQUENCY => CLOCK_FREQUENCY, BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, - COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), - INIT_ADDRESS => INIT_ADDRESS + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) ) port map ( - CLK => clk_100_i, + CLK => clk_sys, RESET => reset_i, CLK_EN => '1', --Media interfacces - MED_DATAREADY_OUT(7*1-1 downto 0) => med_dataready_out, - MED_DATA_OUT(7*16-1 downto 0) => med_data_out, - MED_PACKET_NUM_OUT(7*3-1 downto 0) => med_packet_num_out, - MED_READ_IN(7*1-1 downto 0) => med_read_in, - MED_DATAREADY_IN(7*1-1 downto 0) => med_dataready_in, - MED_DATA_IN(7*16-1 downto 0) => med_data_in, - MED_PACKET_NUM_IN(7*3-1 downto 0) => med_packet_num_in, - MED_READ_OUT(7*1-1 downto 0) => med_read_out, - MED_STAT_OP(7*16-1 downto 0) => med_stat_op, - MED_CTRL_OP(7*16-1 downto 0) => med_ctrl_op, + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), COMMON_STAT_REGS => common_stat_reg, COMMON_CTRL_REGS => common_ctrl_reg, MY_ADDRESS_OUT => my_address, --REGIO INTERFACE - REGIO_ADDR_OUT => BUS_RX.addr, - REGIO_READ_ENABLE_OUT => BUS_RX.read, - REGIO_WRITE_ENABLE_OUT => BUS_RX.write, - REGIO_DATA_OUT => BUS_RX.data, - REGIO_DATA_IN => BUS_TX.data, + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, REGIO_DATAREADY_IN => rdack, - REGIO_NO_MORE_DATA_IN => BUS_TX.nack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, REGIO_WRITE_ACK_IN => wrack, - REGIO_UNKNOWN_ADDR_IN => BUS_TX.unknown, - REGIO_TIMEOUT_OUT => BUS_RX.timeout, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, ONEWIRE => TEMPSENS, ONEWIRE_MONITOR_OUT => open, @@ -562,8 +715,8 @@ gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); end generate; - rdack <= BUS_TX.ack or BUS_TX.rack; - wrack <= BUS_TX.ack or BUS_TX.wack; + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; end generate; @@ -572,7 +725,7 @@ end generate; --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 7, + PORT_NUMBER => 8, PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"8100", 7 => x"8300", others => x"0000"), PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 8, 7 => 8, others => 0), PORT_MASK_ENABLE => 1 @@ -635,10 +788,9 @@ end generate; ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS(17 downto 0) => monitor_inputs_i, - MONITOR_INPUTS(21 downto 18) => trig_gen_out_i, - TRIG_GEN_INPUTS => monitor_inputs_i, - TRIG_GEN_OUTPUTS => trig_gen_out_i, + MONITOR_INPUTS => open, + TRIG_GEN_INPUTS => open, + TRIG_GEN_OUTPUTS => open, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -658,6 +810,7 @@ gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; end generate; + --------------------------------------------------------------------------- -- Switches --------------------------------------------------------------------------- @@ -667,7 +820,6 @@ end generate; PCSSW_PE <= x"F"; PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf index 377aae9..6b11454 100644 --- a/pinout/basic_constraints.lpf +++ b/pinout/basic_constraints.lpf @@ -66,7 +66,7 @@ BLOCK PATH FROM PORT "SFP*"; BLOCK PATH TO PORT "PROGRAMN"; BLOCK PATH TO PORT "TEMPSENS"; BLOCK PATH FROM PORT "TEMPSENS"; -BLOCK PATH TO PORT "TESTLINE"; +BLOCK PATH TO PORT "TEST_LINE"; PROHIBIT PRIMARY NET "ENPIRION_CLOCK_c" ; PROHIBIT SECONDARY NET "ENPIRION_CLOCK_c" ; diff --git a/pinout/trb3sc_hub.lpf b/pinout/trb3sc_hub.lpf new file mode 100644 index 0000000..60c5641 --- /dev/null +++ b/pinout/trb3sc_hub.lpf @@ -0,0 +1,339 @@ +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_SUPPL_PCLK" SITE "V9"; #was SUPPL_CLOCK3_P +LOCATE COMP "CLK_CORE_PCLK" SITE "U9"; #was "CORE_CLOCK0_P" +LOCATE COMP "CLK_EXT_PLL_LEFT" SITE "N7"; #was "EXT_CLOCK2_P" +DEFINE PORT GROUP "CLK_group" "CLK*" ; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +################################################################# +# AddOn Connector +################################################################# + + LOCATE COMP "LED_HUB_LINKOK_1" SITE "AA2"; #was "DQLL0_0_P" 1 + LOCATE COMP "LED_HUB_RX_1" SITE "AA1"; + LOCATE COMP "LED_HUB_TX_1" SITE "AB2"; #was "DQLL0_1_P" 5 + LOCATE COMP "HUB_MOD0_1" SITE "AB1"; + LOCATE COMP "HUB_MOD1_1" SITE "AA4"; #was "DQLL0_2_P" 9 + LOCATE COMP "HUB_MOD2_1" SITE "AA3"; +# LOCATE COMP "HUB_RATESEL_1" SITE "AA10"; #was "DQSLL0_T" 13 + LOCATE COMP "HUB_TXDIS_1" SITE "AB9"; + LOCATE COMP "HUB_LOS_1" SITE "AA5"; #was "DQLL0_3_P" 17 +# LOCATE COMP "HUB_TXFAULT_1" SITE "AB5"; + + LOCATE COMP "LED_HUB_LINKOK_2" SITE "Y7"; #was "DQLL0_4_P" 21 + LOCATE COMP "LED_HUB_RX_2" SITE "AA7"; + LOCATE COMP "LED_HUB_TX_2" SITE "AC5"; #was "DQLL2_0_P" 25 + LOCATE COMP "HUB_MOD0_2" SITE "AC4"; + LOCATE COMP "HUB_MOD1_2" SITE "AC2"; #was "DQLL2_1_P" 29 + LOCATE COMP "HUB_MOD2_2" SITE "AC1"; +# LOCATE COMP "HUB_RATESEL_2" SITE "AB4"; #was "DQLL2_2_P" 33 + LOCATE COMP "HUB_TXDIS_2" SITE "AB3"; + LOCATE COMP "HUB_LOS_2" SITE "AD5"; #was "DQSLL2_T" 37 +# LOCATE COMP "HUB_TXFAULT_2" SITE "AE5"; + + LOCATE COMP "LED_HUB_LINKOK_3" SITE "AE4"; #was "DQLL3_0_P" 2 + LOCATE COMP "LED_HUB_RX_3" SITE "AE3"; + LOCATE COMP "LED_HUB_TX_3" SITE "AB10"; #was "DQLL3_1_P" 6 + LOCATE COMP "HUB_MOD0_3" SITE "AC10"; + LOCATE COMP "HUB_MOD1_3" SITE "AE2"; #was "DQLL3_2_P" 10 + LOCATE COMP "HUB_MOD2_3" SITE "AE1"; +# LOCATE COMP "HUB_RATESEL_3" SITE "AJ1"; #was "DQSLL3_T" 14 + LOCATE COMP "HUB_TXDIS_3" SITE "AK1"; + LOCATE COMP "HUB_LOS_3" SITE "AD4"; #was "DQLL3_3_P" 18 +# LOCATE COMP "HUB_TXFAULT_3" SITE "AD3"; + + LOCATE COMP "LED_HUB_LINKOK_4" SITE "AC9"; #was "DQLL3_4_P" 22 + LOCATE COMP "LED_HUB_RX_4" SITE "AC8"; + LOCATE COMP "LED_HUB_TX_4" SITE "Y2"; #was "DQLL1_0_P" 26 + LOCATE COMP "HUB_MOD0_4" SITE "Y1"; + LOCATE COMP "HUB_MOD1_4" SITE "W4"; #was "DQLL1_1_P" 30 + LOCATE COMP "HUB_MOD2_4" SITE "W3"; +# LOCATE COMP "HUB_RATESEL_4" SITE "W2"; #was "DQLL1_2_P" 34 + LOCATE COMP "HUB_TXDIS_4" SITE "W1"; + LOCATE COMP "HUB_LOS_4" SITE "W6"; #was "DQSLL1_T" 38 +# LOCATE COMP "HUB_TXFAULT_4" SITE "Y6"; + + LOCATE COMP "LED_HUB_LINKOK_5" SITE "AD31"; #was "DQLR1_0_P" 169 + LOCATE COMP "LED_HUB_RX_5" SITE "AD30"; + LOCATE COMP "LED_HUB_TX_5" SITE "AB32"; #was "DQLR1_1_P" 173 + LOCATE COMP "HUB_MOD0_5" SITE "AB31"; + LOCATE COMP "HUB_MOD1_5" SITE "AE34"; #was "DQLR1_2_P" 177 + LOCATE COMP "HUB_MOD2_5" SITE "AE33"; +# LOCATE COMP "HUB_RATESEL_5" SITE "AB26"; #was "DQSLR1_T" 181 + LOCATE COMP "HUB_TXDIS_5" SITE "AB25"; + LOCATE COMP "HUB_LOS_5" SITE "AD33"; #was "DQLR1_3_P" 185 +# LOCATE COMP "HUB_TXFAULT_5" SITE "AD34" + + LOCATE COMP "LED_HUB_LINKOK_6" SITE "W30"; #was "DQLR2_0_P" 170 + LOCATE COMP "LED_HUB_RX_6" SITE "W29"; + LOCATE COMP "LED_HUB_TX_6" SITE "W27"; #was "DQLR2_1_P" 174 + LOCATE COMP "HUB_MOD0_6" SITE "W26"; + LOCATE COMP "HUB_MOD1_6" SITE "W34"; #was "DQLR2_2_P" 178 + LOCATE COMP "HUB_MOD2_6" SITE "W33"; +# LOCATE COMP "HUB_RATESEL_6" SITE "Y30"; #was "DQSLR2_T" 182 + LOCATE COMP "HUB_TXDIS_6" SITE "AA29"; + LOCATE COMP "HUB_LOS_6" SITE "Y34"; #was "DQLR2_3_P" 186 +# LOCATE COMP "HUB_TXFAULT_6" SITE "Y33"; + + LOCATE COMP "LED_HUB_LINKOK_7" SITE "AB34"; #was "DQLR0_0_P" 129 + LOCATE COMP "LED_HUB_RX_7" SITE "AB33"; + LOCATE COMP "LED_HUB_TX_7" SITE "AA25"; #was "DQLR0_1_P" 133 + LOCATE COMP "HUB_MOD0_7" SITE "AA26"; + LOCATE COMP "HUB_MOD1_7" SITE "AC34"; #was "DQLR0_2_P" 137 + LOCATE COMP "HUB_MOD2_7" SITE "AC33"; +# LOCATE COMP "HUB_RATESEL_7" SITE "AB30"; #was "DQSLR0_T" 141 + LOCATE COMP "HUB_TXDIS_7" SITE "AC30"; + LOCATE COMP "HUB_LOS_7" SITE "AA31"; #was "DQLR0_3_P" 145 +# LOCATE COMP "HUB_TXFAULT_7" SITE "AA30" + + LOCATE COMP "LED_HUB_LINKOK_8" SITE "T32"; #was "DQUR2_0_P" 130 + LOCATE COMP "LED_HUB_RX_8" SITE "T31"; + LOCATE COMP "LED_HUB_TX_8" SITE "T26"; #was "DQUR2_1_P" 134 + LOCATE COMP "HUB_MOD0_8" SITE "T27"; + LOCATE COMP "HUB_MOD1_8" SITE "U32"; #was "DQUR2_2_P" 138 + LOCATE COMP "HUB_MOD2_8" SITE "U31"; +# LOCATE COMP "HUB_RATESEL_8" SITE "T30"; #was "DQSUR2_T" 142 + LOCATE COMP "HUB_TXDIS_8" SITE "U30"; + LOCATE COMP "HUB_LOS_8" SITE "T34"; #was "DQUR2_3_P" 146 +# LOCATE COMP "HUB_TXFAULT_8" SITE "T33"; + +DEFINE PORT GROUP "HUB_group" "HUB*" ; +IOBUF GROUP "HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; +DEFINE PORT GROUP "LED_HUB_group" "LED_HUB*" ; +IOBUF GROUP "LED_HUB_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Pin-header IO +################################################################# +#on KEL1 +LOCATE COMP "INP_64" SITE "AP5"; +LOCATE COMP "INP_65" SITE "AP2"; +LOCATE COMP "INP_66" SITE "AN1"; +LOCATE COMP "INP_67" SITE "AN3"; +LOCATE COMP "INP_68" SITE "AL5"; +LOCATE COMP "INP_69" SITE "AM6"; +LOCATE COMP "INP_70" SITE "AL4"; +LOCATE COMP "INP_71" SITE "AJ5"; +LOCATE COMP "INP_72" SITE "AJ2"; +LOCATE COMP "INP_73" SITE "AL3"; +LOCATE COMP "INP_74" SITE "AD9"; +LOCATE COMP "INP_75" SITE "AJ4"; +LOCATE COMP "INP_76" SITE "V4"; +LOCATE COMP "INP_77" SITE "V5"; +LOCATE COMP "INP_78" SITE "T9"; +LOCATE COMP "INP_79" SITE "T2"; + #on KEL2 +LOCATE COMP "INP_80" SITE "AP29"; +LOCATE COMP "INP_81" SITE "AP33"; +LOCATE COMP "INP_82" SITE "AN34"; +LOCATE COMP "INP_83" SITE "AP31"; +LOCATE COMP "INP_84" SITE "AN32"; +LOCATE COMP "INP_85" SITE "AM29"; +LOCATE COMP "INP_86" SITE "AL31"; +LOCATE COMP "INP_87" SITE "AL30"; +LOCATE COMP "INP_88" SITE "AL34"; +LOCATE COMP "INP_89" SITE "AJ31"; +LOCATE COMP "INP_90" SITE "AH33"; +LOCATE COMP "INP_91" SITE "AL32"; +LOCATE COMP "INP_92" SITE "AF32"; +LOCATE COMP "INP_93" SITE "AE32"; +LOCATE COMP "INP_94" SITE "AE30"; +LOCATE COMP "INP_95" SITE "AD26"; +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "DAC_IN_SDI_5" SITE "P7"; +LOCATE COMP "DAC_IN_SDI_6" SITE "M29"; +DEFINE PORT GROUP "IN_group" "DAC_IN*" ; +IOBUF GROUP "IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + + +LOCATE COMP "DAC_OUT_SDO_5" SITE "R8"; +LOCATE COMP "DAC_OUT_SCK_5" SITE "R2"; +LOCATE COMP "DAC_OUT_CS_5" SITE "P9"; +LOCATE COMP "DAC_OUT_SDO_6" SITE "AC28"; +LOCATE COMP "DAC_OUT_SCK_6" SITE "M34"; +LOCATE COMP "DAC_OUT_CS_6" SITE "L28"; +DEFINE PORT GROUP "OUT_group" "DAC_OUT*" ; +IOBUF GROUP "OUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF; + + + +################################################################# +# Pin-header IO +################################################################# +LOCATE COMP "HDR_IO_1" SITE "AP28"; +LOCATE COMP "HDR_IO_2" SITE "AN28"; +LOCATE COMP "HDR_IO_3" SITE "AP27"; +LOCATE COMP "HDR_IO_4" SITE "AN27"; +LOCATE COMP "HDR_IO_5" SITE "AM27"; +LOCATE COMP "HDR_IO_6" SITE "AL27"; +LOCATE COMP "HDR_IO_7" SITE "AH26"; +LOCATE COMP "HDR_IO_8" SITE "AG26"; +LOCATE COMP "HDR_IO_9" SITE "AM28"; +LOCATE COMP "HDR_IO_10" SITE "AL28"; +DEFINE PORT GROUP "HDR_group" "HDR*" ; +IOBUF GROUP "HDR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +################################################################# +# Many LED +################################################################# +LOCATE COMP "LED_RJ_GREEN_0" SITE "C25"; +LOCATE COMP "LED_RJ_RED_0" SITE "D25"; +LOCATE COMP "LED_GREEN" SITE "D24"; +LOCATE COMP "LED_ORANGE" SITE "E24"; +LOCATE COMP "LED_RED" SITE "K23"; +LOCATE COMP "LED_RJ_GREEN_1" SITE "G26"; +LOCATE COMP "LED_RJ_RED_1" SITE "G25"; +LOCATE COMP "LED_YELLOW" SITE "K24"; +IOBUF PORT "LED_RJ_GREEN_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_0" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_GREEN_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_RJ_RED_1" IO_TYPE=LVCMOS25 ; +IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "LED_SFP_GREEN_0" SITE "B4"; +LOCATE COMP "LED_SFP_GREEN_1" SITE "A6"; +LOCATE COMP "LED_SFP_RED_0" SITE "A3"; +LOCATE COMP "LED_SFP_RED_1" SITE "A8"; +DEFINE PORT GROUP "LED_SFP_group" "LED_SFP*" ; +IOBUF GROUP "LED_SFP_group" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_WHITE_0" SITE "A32"; +LOCATE COMP "LED_WHITE_1" SITE "A33"; +DEFINE PORT GROUP "LED_WHITE_group" "LED_WHITE*" ; +IOBUF GROUP "LED_WHITE_group" IO_TYPE=LVTTL33 ; + +################################################################# +# SFP Control Signals +################################################################# +LOCATE COMP "SFP_LOS_0" SITE "B6"; +LOCATE COMP "SFP_LOS_1" SITE "C9"; +LOCATE COMP "SFP_MOD0_0" SITE "A5"; +LOCATE COMP "SFP_MOD0_1" SITE "K11"; +LOCATE COMP "SFP_MOD1_0" SITE "B7"; +LOCATE COMP "SFP_MOD1_1" SITE "J11"; +LOCATE COMP "SFP_MOD2_0" SITE "A7"; +LOCATE COMP "SFP_MOD2_1" SITE "D9"; +LOCATE COMP "SFP_TX_DIS_0" SITE "D6"; +LOCATE COMP "SFP_TX_DIS_1" SITE "A9"; + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVTTL33 ; + + + +################################################################# +# Serdes Output Switch +################################################################# +LOCATE COMP "PCSSW_ENSMB" SITE "B3"; +LOCATE COMP "PCSSW_EQ_0" SITE "B1"; +LOCATE COMP "PCSSW_EQ_1" SITE "B2"; +LOCATE COMP "PCSSW_EQ_2" SITE "E4"; +LOCATE COMP "PCSSW_EQ_3" SITE "D4"; +LOCATE COMP "PCSSW_PE_0" SITE "C3"; +LOCATE COMP "PCSSW_PE_1" SITE "C4"; +LOCATE COMP "PCSSW_PE_2" SITE "D3"; +LOCATE COMP "PCSSW_PE_3" SITE "C2"; +LOCATE COMP "PCSSW_1" SITE "D5"; +LOCATE COMP "PCSSW_0" SITE "A2"; +LOCATE COMP "PCSSW_2" SITE "E13"; +LOCATE COMP "PCSSW_3" SITE "F13"; +LOCATE COMP "PCSSW_4" SITE "G13"; +LOCATE COMP "PCSSW_5" SITE "H14"; +LOCATE COMP "PCSSW_6" SITE "A13"; +LOCATE COMP "PCSSW_7" SITE "B13"; +DEFINE PORT GROUP "PCSSW_group" "PCSSW*" ; +IOBUF GROUP "PCSSW_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +################################################################# +# ADC +################################################################# +LOCATE COMP "ADC_CLK" SITE "A14"; +LOCATE COMP "ADC_CS" SITE "B14"; +LOCATE COMP "ADC_DIN" SITE "G17"; +LOCATE COMP "ADC_DOUT" SITE "G16"; +IOBUF PORT "ADC_CLK" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_CS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DIN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=4 ; +IOBUF PORT "ADC_DOUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + +################################################################# +# RJ-45 connectors +################################################################# +LOCATE COMP "RJ_IO_0" SITE "R28"; +LOCATE COMP "RJ_IO_1" SITE "R31"; +LOCATE COMP "RJ_IO_2" SITE "R26"; +LOCATE COMP "RJ_IO_3" SITE "R34"; +#LOCATE COMP "RJ_IO_1_N" SITE "R27"; +#LOCATE COMP "RJ_IO_2_N" SITE "R30"; +#LOCATE COMP "RJ_IO_3_N" SITE "R25"; +#LOCATE COMP "RJ_IO_4_N" SITE "R33"; +IOBUF PORT "RJ_IO_0" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; +IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; +IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; + + +LOCATE COMP "SPARE_IN_0" SITE "K31"; +LOCATE COMP "SPARE_IN_1" SITE "R4"; +#LOCATE COMP "SPARE_IN0_N" SITE "K32"; +#LOCATE COMP "SPARE_IN1_N" SITE "R3"; +IOBUF PORT "SPARE_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "SPARE_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + + + +################################################################# +# Flash ROM and Reboot +################################################################# +LOCATE COMP "FLASH_CLK" SITE "F34"; #was "SPI_CLK" +LOCATE COMP "FLASH_CS" SITE "D34"; #was "SPI_CS" +LOCATE COMP "FLASH_IN" SITE "F33"; #was "SPI_IN" +LOCATE COMP "FLASH_OUT" SITE "F32"; #was "SPI_OUT" +LOCATE COMP "PROGRAMN" SITE "C31"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVTTL33 PULLMODE=NONE; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "ENPIRION_CLOCK" SITE "H23"; +IOBUF PORT "ENPIRION_CLOCK" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "J13"; #was TEMP_OWB +IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Trigger I/O +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A19"; +LOCATE COMP "TEST_LINE_1" SITE "B19"; +LOCATE COMP "TEST_LINE_2" SITE "K20"; +LOCATE COMP "TEST_LINE_3" SITE "L19"; +LOCATE COMP "TEST_LINE_4" SITE "C19"; +LOCATE COMP "TEST_LINE_5" SITE "D19"; +LOCATE COMP "TEST_LINE_6" SITE "J19"; +LOCATE COMP "TEST_LINE_7" SITE "K19"; +LOCATE COMP "TEST_LINE_8" SITE "A20"; +LOCATE COMP "TEST_LINE_9" SITE "B20"; +LOCATE COMP "TEST_LINE_10" SITE "G20"; +LOCATE COMP "TEST_LINE_11" SITE "G21"; +LOCATE COMP "TEST_LINE_12" SITE "C20"; +LOCATE COMP "TEST_LINE_13" SITE "D20"; +LOCATE COMP "TEST_LINE_14" SITE "F21"; +LOCATE COMP "TEST_LINE_15" SITE "F22"; +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; -- 2.43.0