From 74c0f9df0029126ad482e4e5749cfeee94817118 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sat, 5 Feb 2022 15:43:14 +0100 Subject: [PATCH] before TDC --- cts/config_simple.vhd | 6 ++--- cts/par.p2t | 2 +- cts/trb3sc_cts.vhd | 58 +++++++++++++++++++++---------------------- 3 files changed, 33 insertions(+), 33 deletions(-) diff --git a/cts/config_simple.vhd b/cts/config_simple.vhd index c1d6527..e258855 100644 --- a/cts/config_simple.vhd +++ b/cts/config_simple.vhd @@ -39,7 +39,7 @@ package config is constant INCLUDE_DEBUG_INTERFACE : integer := c_YES; --input monitor and trigger generation logic - constant INCLUDE_TDC : integer := c_NO; + constant INCLUDE_TDC : integer := c_YES; constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; constant INCLUDE_STATISTICS : integer := c_YES; constant TRIG_GEN_INPUT_NUM : integer := 36 - USE_RJADAPT*12; @@ -48,9 +48,9 @@ package config is -- TDC stuff constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons - constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2: alternating channels, diff --git a/cts/par.p2t b/cts/par.p2t index 7d3af7c..51f613b 100644 --- a/cts/par.p2t +++ b/cts/par.p2t @@ -1,7 +1,7 @@ -w -l 5 -s 10 --t 37 # seed setting here! 3 4 13 17 37 51 +-t 3 # seed setting here! 3 4 13 17 37 51 -c 0 -e 0 -i 6 diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 54b0164..992850c 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -1063,34 +1063,34 @@ end generate; ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- --- THE_TDC : entity work.TDC_record --- generic map ( --- CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module --- STATUS_REG_NR => 21, -- Number of status regs --- DEBUG => c_YES, --- SIMULATION => c_NO --- ) --- port map ( --- RESET => reset_i, --- CLK_TDC => clk_full_osc, --- CLK_READOUT => clk_sys, -- Clock for the readout --- REFERENCE_TIME => cts_trigger_out, -- Reference time input --- HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals --- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC --- -- Trigger signals from handler --- BUSRDO_RX => cts_rdo_rx, --- BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM), --- -- Slow control bus --- BUS_RX => bustdc_rx, --- BUS_TX => bustdc_tx, --- -- Dubug signals --- INFO_IN => timer, --- LOGIC_ANALYSER_OUT => open --- ); --- --- -- For single edge measurements --- gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate --- hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0); --- end generate; + THE_TDC : entity work.TDC_record + generic map ( + CHANNEL_NUMBER => NUM_TDC_CHANNELS, -- Number of TDC channels per module + STATUS_REG_NR => 21, -- Number of status regs + DEBUG => c_YES, + SIMULATION => c_NO + ) + port map ( + RESET => reset_i, + CLK_TDC => clk_full_osc, + CLK_READOUT => clk_sys, -- Clock for the readout + REFERENCE_TIME => cts_trigger_out, -- Reference time input + HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals + HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC + -- Trigger signals from handler + BUSRDO_RX => cts_rdo_rx, + BUSRDO_TX => cts_rdo_additional(INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM), + -- Slow control bus + BUS_RX => bustdc_rx, + BUS_TX => bustdc_tx, + -- Debug signals + INFO_IN => timer, + LOGIC_ANALYSER_OUT => open + ); + + -- For single edge measurements + gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate + hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0); + end generate; end architecture; -- 2.43.0