From 75070d2e9653af2c3a2ef067246b8a0f211a1aa5 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Wed, 16 Oct 2013 02:40:33 +0200 Subject: [PATCH] nxyter updates, cleanup --- base/trb3_periph_nxyter.lpf | 22 +- nxyter/source/gray_decoder.vhd | 3 +- nxyter/source/gray_encoder.vhd | 2 +- nxyter/source/level_to_pulse.vhd | 60 ++--- nxyter/source/nx_data_receiver.vhd | 323 +++++++++++++++++--------- nxyter/source/nx_data_validate.vhd | 8 +- nxyter/source/nx_fpga_timestamp.vhd | 60 ++--- nxyter/source/nx_histograms.vhd | 266 +++++++++++---------- nxyter/source/nx_timer.vhd | 75 +++--- nxyter/source/nx_trigger_validate.vhd | 6 +- nxyter/source/nxyter_components.vhd | 123 ++++++---- nxyter/source/nxyter_fee_board.vhd | 314 +++++++++++++------------ nxyter/source/nxyter_registers.vhd | 71 +++--- nxyter/source/pulse_dtrans.vhd | 74 ++++++ nxyter/source/pulse_to_level.vhd | 89 ++++--- nxyter/source/registers.txt | 3 +- nxyter/trb3_periph.prj | 2 + nxyter/trb3_periph.vhd | 107 ++++----- nxyter/trb3_periph_constraints.lpf | 29 +-- 19 files changed, 967 insertions(+), 670 deletions(-) create mode 100644 nxyter/source/pulse_dtrans.vhd diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index 0af0430..cc8579a 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -93,10 +93,10 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; # nXyter 1 LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 -LOCATE COMP "NX1_CLK256A_OUT" SITE "AB1"; #DQLL2_2 #29 +LOCATE COMP "NX1_MAIN_CLK_OUT" SITE "AB1"; #DQLL2_2 #29 LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45 -#LOCATE COMP "NX1_CLK128_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE +#LOCATE COMP "NX1_DATA_CLK_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +LOCATE COMP "NX1_DATA_CLK_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34 LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36 @@ -146,9 +146,9 @@ IOBUF PORT "NX1_ADC_B_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; -IOBUF PORT "NX1_CLK128_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "NX1_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=LVDS25; -IOBUF PORT "NX1_CLK256A_OUT" IO_TYPE=LVDS25; +IOBUF PORT "NX1_MAIN_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX1_RESET_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; @@ -164,12 +164,12 @@ IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP; # nXyter 2 -LOCATE COMP "NX2_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133 +LOCATE COMP "NX2_ADC_SAMPLE_CLK_OUT" SITE "Y19"; #DQLR0_2 #133 LOCATE COMP "NX2_RESET_OUT" SITE "W23"; #DQLR1_0 #169 -LOCATE COMP "NX2_CLK256A_OUT" SITE "AA26"; #DQLR1_4 #177 +LOCATE COMP "NX2_MAIN_CLK_OUT" SITE "AA26"; #DQLR1_4 #177 LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185 -LOCATE COMP "NX2_CLK128_IN" SITE "M23"; #DQSUR1_T #118 -#LOCATE COMP "NX2_CLK128_IN" SITE "N23"; #DQUR2_2 #134 +LOCATE COMP "NX2_DATA_CLK_IN" SITE "M23"; #DQSUR1_T #118 +#LOCATE COMP "NX2_DATA_CLK_IN" SITE "N23"; #DQUR2_2 #134 LOCATE COMP "ADDON_TRIGGER_OUT" SITE "N23"; #DQUR2_2 #134 LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170 @@ -221,9 +221,9 @@ IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "ADDON_TRIGGER_OUT" IO_TYPE=LVDS25; -IOBUF PORT "NX2_CLK128_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "NX2_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25; -IOBUF PORT "NX2_CLK256A_OUT" IO_TYPE=LVDS25; +IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX2_RESET_OUT" IO_TYPE=LVDS25; IOBUF PORT "NX2_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; diff --git a/nxyter/source/gray_decoder.vhd b/nxyter/source/gray_decoder.vhd index fdcffd8..3cd1c8b 100644 --- a/nxyter/source/gray_decoder.vhd +++ b/nxyter/source/gray_decoder.vhd @@ -10,7 +10,8 @@ use ieee.numeric_std.all; entity Gray_Decoder is generic ( - WIDTH : integer := 12); -- Register Width + WIDTH : integer range 2 to 32 := 12 -- Register Width + ); port ( CLK_IN : in std_logic; diff --git a/nxyter/source/gray_encoder.vhd b/nxyter/source/gray_encoder.vhd index 037a4ee..559acaa 100644 --- a/nxyter/source/gray_encoder.vhd +++ b/nxyter/source/gray_encoder.vhd @@ -9,7 +9,7 @@ use ieee.numeric_std.all; entity Gray_Encoder is generic ( - WIDTH : integer := 12 -- Register Width + WIDTH : integer range 2 to 32 := 12 -- Register Width ); port ( diff --git a/nxyter/source/level_to_pulse.vhd b/nxyter/source/level_to_pulse.vhd index b77f4de..c3b3865 100644 --- a/nxyter/source/level_to_pulse.vhd +++ b/nxyter/source/level_to_pulse.vhd @@ -19,44 +19,52 @@ architecture Behavioral of level_to_pulse is type STATES is (IDLE, WAIT_LOW ); - signal STATE : STATES; + signal STATE, NEXT_STATE : STATES; signal pulse_o : std_logic; begin - PROC_CONVERT: process(CLK_IN) + PROC_CONVERT_TRANSFER:process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - pulse_o <= '0'; - STATE <= IDLE; + STATE <= IDLE; else - pulse_o <= '0'; - case STATE is - - when IDLE => - if (LEVEL_IN = '1') then - pulse_o <= '1'; - STATE <= WAIT_LOW; - else - STATE <= IDLE; - end if; - - when WAIT_LOW => - if (LEVEL_IN = '0') then - STATE <= IDLE; - else - STATE <= WAIT_LOW; - end if; - - when others => null; - - end case; + STATE <= NEXT_STATE; end if; end if; + end process PROC_CONVERT_TRANSFER; + + + PROC_CONVERT: process(STATE, + LEVEL_IN + ) + begin + + case STATE is + when IDLE => + if (LEVEL_IN = '1') then + pulse_o <= '1'; + NEXT_STATE <= WAIT_LOW; + else + pulse_o <= '0'; + NEXT_STATE <= IDLE; + end if; + + when WAIT_LOW => + pulse_o <= '0'; + if (LEVEL_IN = '0') then + NEXT_STATE <= IDLE; + else + NEXT_STATE <= WAIT_LOW; + end if; + + end case; + end process PROC_CONVERT; - PULSE_OUT <= pulse_o; + -- Output Signals + PULSE_OUT <= pulse_o; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 1c07f29..1adbea2 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -12,6 +12,7 @@ entity nx_data_receiver is port( CLK_IN : in std_logic; RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; TRIGGER_IN : in std_logic; -- nXyter Ports @@ -51,104 +52,117 @@ end entity; architecture Behavioral of nx_data_receiver is + ----------------------------------------------------------------------------- + -- NX_MAIN_CLK Domain + ----------------------------------------------------------------------------- + + -- Check Nxyter Data Clock + signal nx_data_clock_t : std_logic; + signal nx_data_clock : std_logic; + signal nx_data_clock_last : std_logic; + signal nx_data_clock_nok : std_logic; + + -- CLK_IN Domain + signal nx_data_clock_invalid : std_logic; + ----------------------------------------------------------------------------- -- NX_TIMESTAMP_CLK Domain ----------------------------------------------------------------------------- -- FIFO DC Input Handler - signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); - signal nx_timestamp_reg : std_logic_vector(7 downto 0); - signal nx_fifo_full : std_logic; - signal nx_fifo_reset : std_logic; - - -- NX_TIMESTAMP_IN Process - signal frame_byte_ctr : unsigned(1 downto 0); - signal nx_frame_word : std_logic_vector(31 downto 0); - signal nx_new_frame : std_logic; - - -- Frame Sync Process - signal frame_byte_pos : unsigned(1 downto 0); - - -- RS Sync FlipFlop - signal nx_frame_synced : std_logic; - signal rs_sync_set : std_logic; - signal rs_sync_reset : std_logic; - - -- Parity Check - signal parity_error : std_logic; - - -- Write to FIFO Handler - signal nx_fifo_data_input : std_logic_vector(31 downto 0); - signal nx_fifo_write_enable : std_logic; - - -- NX Clock Active - signal nx_clk_active_ff_0 : std_logic; - signal nx_clk_active_ff_1 : std_logic; - signal nx_clk_active_ff_2 : std_logic; - - -- ADC Ckl Generator - signal adc_clk_skip : std_logic; - signal adc_sample_clk : std_logic; - signal johnson_ff_0 : std_logic; - signal johnson_ff_1 : std_logic; - signal adc_clk_inv : std_logic; - signal adc_clk_delay : std_logic_vector(2 downto 0); - signal adc_clk_ok : std_logic; - - -- ADC RESET - signal adc_clk_ok_last : std_logic; - signal adc_reset_s : std_logic; - signal adc_reset_ctr : unsigned(11 downto 0); + signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); + signal nx_timestamp_reg : std_logic_vector(7 downto 0); + signal nx_fifo_full : std_logic; + signal nx_fifo_reset : std_logic; + + -- NX_TIMESTAMP_IN Process + signal frame_byte_ctr : unsigned(1 downto 0); + signal nx_frame_word : std_logic_vector(31 downto 0); + signal nx_new_frame : std_logic; + + -- Frame Sync Process + signal frame_byte_pos : unsigned(1 downto 0); + + -- RS Sync FlipFlop + signal nx_frame_synced : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + + -- Parity Check + signal parity_error : std_logic; + + -- Write to FIFO Handler + signal nx_fifo_data_input : std_logic_vector(31 downto 0); + signal nx_fifo_write_enable : std_logic; + + -- NX Clock Active + signal nx_clk_active_ff_0 : std_logic; + signal nx_clk_active_ff_1 : std_logic; + signal nx_clk_active_ff_2 : std_logic; + + -- ADC Ckl Generator + signal adc_clk_skip : std_logic; + signal adc_sample_clk : std_logic; + signal johnson_ff_0 : std_logic; + signal johnson_ff_1 : std_logic; + signal adc_clk_inv : std_logic; + signal adc_clk_delay : std_logic_vector(2 downto 0); + signal adc_clk_ok : std_logic; + + -- ADC RESET + signal adc_clk_ok_last : std_logic; + signal adc_reset_s : std_logic; + signal adc_reset_ctr : unsigned(11 downto 0); ----------------------------------------------------------------------------- -- CLK_IN Domain ----------------------------------------------------------------------------- -- NX FIFO READ ENABLE - signal nx_fifo_read_enable : std_logic; - signal nx_fifo_empty : std_logic; - signal nx_read_enable : std_logic; - signal nx_fifo_data_valid_t : std_logic; - signal nx_fifo_data_valid : std_logic; - - -- NX FIFO READ - signal nx_timestamp_t : std_logic_vector(31 downto 0); - signal nx_new_timestamp : std_logic; - signal nx_new_timestamp_ctr : unsigned(3 downto 0); - signal nx_fifo_data : std_logic_vector(31 downto 0); - - -- Resync Counter Process - signal resync_counter : unsigned(11 downto 0); - signal resync_ctr_inc : std_logic; - signal nx_clk_active : std_logic; - - -- Parity Error Counter Process - signal parity_error_counter : unsigned(11 downto 0); - signal parity_error_ctr_inc : std_logic; - - signal reg_nx_frame_synced_t : std_logic; - signal reg_nx_frame_synced : std_logic; + signal nx_fifo_read_enable : std_logic; + signal nx_fifo_empty : std_logic; + signal nx_read_enable : std_logic; + signal nx_fifo_data_valid_t : std_logic; + signal nx_fifo_data_valid : std_logic; + + -- NX FIFO READ + signal nx_timestamp_t : std_logic_vector(31 downto 0); + signal nx_new_timestamp : std_logic; + signal nx_new_timestamp_ctr : unsigned(3 downto 0); + signal nx_fifo_data : std_logic_vector(31 downto 0); + + -- Resync Counter Process + signal resync_counter : unsigned(11 downto 0); + signal resync_ctr_inc : std_logic; + signal nx_clk_active : std_logic; + + -- Parity Error Counter Process + signal parity_error_counter : unsigned(11 downto 0); + signal parity_error_ctr_inc : std_logic; + + signal reg_nx_frame_synced_t : std_logic; + signal reg_nx_frame_synced : std_logic; ----------------------------------------------------------------------------- -- ADC Data Handler ----------------------------------------------------------------------------- -- ADC Handler - signal adc_reset_r : std_logic; - signal adc_reset_l : std_logic; - signal adc_reset : std_logic; - - signal adc_data : std_logic_vector(11 downto 0); - signal test_adc_data : std_logic_vector(11 downto 0); - signal adc_data_valid : std_logic; - - signal adc_data_t : std_logic_vector(11 downto 0); - signal adc_new_data : std_logic; - signal adc_new_data_ctr : unsigned(3 downto 0); - - -- ADC TEST INPUT DATA - signal adc_input_error_enable : std_logic; - signal adc_input_error_ctr : unsigned(15 downto 0); + signal adc_reset_r : std_logic; + signal adc_reset_l : std_logic; + signal adc_reset : std_logic; + + signal adc_data : std_logic_vector(11 downto 0); + signal test_adc_data : std_logic_vector(11 downto 0); + signal adc_data_valid : std_logic; + + signal adc_data_t : std_logic_vector(11 downto 0); + signal adc_new_data : std_logic; + signal adc_new_data_ctr : unsigned(3 downto 0); + + -- ADC TEST INPUT DATA + signal adc_input_error_enable : std_logic; + signal adc_input_error_ctr : unsigned(15 downto 0); -- Data Output Handler @@ -157,25 +171,25 @@ architecture Behavioral of nx_data_receiver is WAIT_TIMESTAMP ); signal STATE : STATES; - signal STATE_d : std_logic_vector(1 downto 0); - - signal nx_timestamp_o : std_logic_vector(31 downto 0); - signal adc_data_o : std_logic_vector(11 downto 0); - signal new_data_o : std_logic; - - -- Slave Bus - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - signal reset_resync_ctr : std_logic; - signal reset_parity_error_ctr : std_logic; - signal fifo_reset_r : std_logic; - signal debug_adc : std_logic_vector(1 downto 0); - -begin + signal STATE_d : std_logic_vector(1 downto 0); + + signal nx_timestamp_o : std_logic_vector(31 downto 0); + signal adc_data_o : std_logic_vector(11 downto 0); + signal new_data_o : std_logic; + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + + signal reset_resync_ctr : std_logic; + signal reset_parity_error_ctr : std_logic; + signal fifo_reset_r : std_logic; + signal debug_adc : std_logic_vector(1 downto 0); +begin + PROC_DEBUG_MULT: process(debug_adc, adc_data, adc_data_valid, @@ -227,7 +241,13 @@ begin DEBUG_OUT(8) <= adc_reset_s; DEBUG_OUT(9) <= adc_reset; DEBUG_OUT(10) <= nx_new_frame; - DEBUG_OUT(15 downto 11) <= adc_reset_ctr(4 downto 0) ; + DEBUG_OUT(11) <= nx_data_clock; + DEBUG_OUT(12) <= nx_data_clock_last; + DEBUG_OUT(13) <= nx_data_clock_nok; + DEBUG_OUT(14) <= nx_data_clock_invalid; + DEBUG_OUT(15) <= '0'; + + --DEBUG_OUT(15 downto 11) <= adc_reset_ctr(4 downto 0) ; when others => DEBUG_OUT(0) <= CLK_IN; @@ -243,6 +263,7 @@ begin DEBUG_OUT(9) <= nx_new_timestamp; DEBUG_OUT(10) <= adc_new_data; + DEBUG_OUT(12 downto 11) <= STATE_d; DEBUG_OUT(13) <= new_data_o; @@ -252,6 +273,45 @@ begin end process PROC_DEBUG_MULT; + ----------------------------------------------------------------------------- + -- NX_MAIN_CLK Domain + ----------------------------------------------------------------------------- + PROC_CHECK_NX_DATA_CLOCK: process(NX_MAIN_CLK_IN) + begin + if (rising_edge(NX_MAIN_CLK_IN)) then + if( RESET_IN = '1' ) then + nx_data_clock_t <= '0'; + nx_data_clock <= '0'; + nx_data_clock_last <= '0'; + nx_data_clock_nok <= '0'; + else + if (nx_data_clock /= nx_data_clock_last) then + nx_data_clock_nok <= '0'; + else + nx_data_clock_nok <= '1'; + end if; + + nx_data_clock_t <= NX_TIMESTAMP_CLK_IN; + nx_data_clock <= nx_data_clock_t; + nx_data_clock_last <= nx_data_clock; + end if; + end if; + end process PROC_CHECK_NX_DATA_CLOCK; + + pulse_dtrans_1: pulse_dtrans + generic map ( + CLK_RATIO => 3 + ) + port map ( + CLK_A_IN => NX_MAIN_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => nx_data_clock_nok, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => nx_data_clock_invalid + ); + + ----------------------------------------------------------------------------- -- ADC CLK DOMAIN ----------------------------------------------------------------------------- @@ -296,7 +356,7 @@ begin pulse_to_level_1: pulse_to_level generic map ( - NUM_CYCLES => "10000" + NUM_CYCLES => 7 ) port map ( CLK_IN => CLK_IN, @@ -550,6 +610,18 @@ begin end if; end if; end process PROC_RESET_CTR; + + -- PROC_CAL_RATES: process (CLK_IN) + -- begin + -- if( rising_edge(CLK_IN) ) then + -- if (RESET_IN = '1') then + -- nx_trigger_ctr_t <= (others => '0'); + -- nx_hit_rate <= (others => '0'); + -- nx_frame_rate <= (others => '0'); + -- else + -- end if; + -- end if; + -- end process PROC_CAL_RATES; ----------------------------------------------------------------------------- -- NX CLK_IN Domain @@ -597,17 +669,23 @@ begin ----------------------------------------------------------------------------- -- Domain Transfers - pulse_sync_1: pulse_sync + pulse_dtrans_2: pulse_dtrans + generic map ( + CLK_RATIO => 3 + ) port map ( CLK_A_IN => NX_TIMESTAMP_CLK_IN, RESET_A_IN => RESET_IN, PULSE_A_IN => rs_sync_reset, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, - PULSE_B_OUT => resync_ctr_inc + PULSE_B_OUT => resync_ctr_inc ); - pulse_sync_2: pulse_sync + pulse_dtrans_3: pulse_dtrans + generic map ( + CLK_RATIO => 3 + ) port map ( CLK_A_IN => NX_TIMESTAMP_CLK_IN, RESET_A_IN => RESET_IN, @@ -616,7 +694,7 @@ begin RESET_B_IN => RESET_IN, PULSE_B_OUT => parity_error_ctr_inc ); - + PROC_SYNC_FRAME_SYNC: process(CLK_IN) begin if (rising_edge(CLK_IN) ) then @@ -764,7 +842,7 @@ begin end if; end if; end process PROC_OUTPUT_HANDLER; - + ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- @@ -785,6 +863,9 @@ begin adc_reset_r <= '0'; debug_adc <= (others => '0'); adc_input_error_enable <= '0'; + -- pll_adc_sample_clk_reset <= '1'; + -- pll_adc_sample_clk_dphase <= (others => '0'); + -- pll_adc_sample_clk_finedelb <= (others => '0'); else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -794,6 +875,9 @@ begin reset_parity_error_ctr <= '0'; fifo_reset_r <= '0'; adc_reset_r <= '0'; + -- pll_adc_sample_clk_reset <= '0'; + -- pll_adc_sample_clk_dphase <= (others => '0'); + -- pll_adc_sample_clk_finedelb <= (others => '0'); if (SLV_READ_IN = '1') then case SLV_ADDR_IN is @@ -863,6 +947,21 @@ begin slv_data_out_o(15 downto 0) <= adc_input_error_ctr; slv_data_out_o(31 downto 16) <= (others => '0'); slv_ack_o <= '1'; + + -- when x"000b" => + -- slv_data_out_o(0) <= pll_adc_sample_clk_lock; + -- slv_data_out_o(31 downto 1) <= (others => '0'); + -- slv_ack_o <= '1'; + -- + -- when x"000c" => + -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_dphase; + -- slv_data_out_o(31 downto 4) <= (others => '0'); + -- slv_ack_o <= '1'; + -- + -- when x"000d" => + -- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb; + -- slv_data_out_o(31 downto 4) <= (others => '0'); + -- slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; @@ -905,6 +1004,18 @@ begin adc_input_error_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; + -- when x"000b" => + -- pll_adc_sample_clk_reset <= '1'; + -- slv_ack_o <= '1'; + -- + -- when x"000c" => + -- pll_adc_sample_clk_dphase <= SLV_DATA_IN(3 downto 0); + -- slv_ack_o <= '1'; + -- + -- when x"000d" => + -- pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0); + -- slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 2130f29..9f33f97 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -87,7 +87,7 @@ architecture Behavioral of nx_data_validate is signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; signal clear_counters : std_logic; - signal nx_trigger_rate : unsigned(27 downto 0); + signal nx_hit_rate : unsigned(27 downto 0); signal nx_frame_rate : unsigned(27 downto 0); signal invalid_adc : std_logic; @@ -285,7 +285,7 @@ begin nx_trigger_ctr_t <= (others => '0'); nx_frame_ctr_t <= (others => '0'); nx_rate_timer <= (others => '0'); - nx_trigger_rate <= (others => '0'); + nx_hit_rate <= (others => '0'); nx_frame_rate <= (others => '0'); else if (nx_rate_timer < x"5f5e100") then @@ -297,7 +297,7 @@ begin end if; nx_rate_timer <= nx_rate_timer + 1; else - nx_trigger_rate <= nx_trigger_ctr_t; + nx_hit_rate <= nx_trigger_ctr_t; nx_frame_rate <= nx_frame_ctr_t; if (trigger_rate_inc = '0') then nx_trigger_ctr_t <= (others => '0'); @@ -364,7 +364,7 @@ begin when x"0004" => slv_data_out_o(27 downto 0) <= - std_logic_vector(nx_trigger_rate); + std_logic_vector(nx_hit_rate); slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index 5059218..192a053 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -7,27 +7,28 @@ use work.nxyter_components.all; entity nx_fpga_timestamp is port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NX_CLK_IN : in std_logic; - - TIMESTAMP_SYNC_IN : in std_logic; - TRIGGER_IN : in std_logic; - TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); - TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); - NX_TIMESTAMP_SYNC_OUT : out std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; + + TIMESTAMP_SYNC_IN : in std_logic; + TRIGGER_IN : in std_logic; + TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); + TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); + NX_TIMESTAMP_SYNC_OUT : out std_logic; + NX_TIMESTAMP_TRIGGER_OUT : out std_logic; -- Slave bus - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Debug Line - DEBUG_OUT : out std_logic_vector(15 downto 0) + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + + -- Debug Line + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity; @@ -72,9 +73,9 @@ begin -- NX Clock Domain -- Cross Clockdomain for TRIGGER and SYNC - PROC_SYNC: process (NX_CLK_IN) + PROC_SYNC: process (NX_MAIN_CLK_IN) begin - if( rising_edge(NX_CLK_IN) ) then + if( rising_edge(NX_MAIN_CLK_IN) ) then if (RESET_IN = '1') then trigger_x <= '0'; trigger_l <= '0'; @@ -92,7 +93,7 @@ begin -- Convert TRIGGER_IN to Pulse level_to_pulse_1: level_to_pulse port map ( - CLK_IN => NX_CLK_IN, + CLK_IN => NX_MAIN_CLK_IN, RESET_IN => RESET_IN, LEVEL_IN => trigger_l, PULSE_OUT => trigger @@ -101,7 +102,7 @@ begin -- Convert TIMESTAMP_SYNC_IN to Pulse level_to_pulse_2: level_to_pulse port map ( - CLK_IN => NX_CLK_IN, + CLK_IN => NX_MAIN_CLK_IN, RESET_IN => RESET_IN, LEVEL_IN => timestamp_sync_l, PULSE_OUT => timestamp_sync @@ -109,9 +110,9 @@ begin -- Timestamp Process + Trigger - PROC_TIMESTAMP_CTR: process (NX_CLK_IN) + PROC_TIMESTAMP_CTR: process (NX_MAIN_CLK_IN) begin - if( rising_edge(NX_CLK_IN) ) then + if( rising_edge(NX_MAIN_CLK_IN) ) then if( RESET_IN = '1' ) then timestamp_ctr <= (others => '0'); timestamp_hold <= (others => '0'); @@ -145,7 +146,7 @@ begin fifo_ts_12to12_dc_1: fifo_ts_12to12_dc port map ( Data => timestamp_hold, - WrClock => NX_CLK_IN, + WrClock => NX_MAIN_CLK_IN, RdClock => CLK_IN, WrEn => fifo_write_enable, RdEn => fifo_read_enable, @@ -180,8 +181,9 @@ begin -- Output Signals ----------------------------------------------------------------------------- - TIMESTAMP_CURRENT_OUT <= timestamp_current_o; - TIMESTAMP_HOLD_OUT <= timestamp_hold_o; - NX_TIMESTAMP_SYNC_OUT <= nx_timestamp_sync_o; + TIMESTAMP_CURRENT_OUT <= timestamp_current_o; + TIMESTAMP_HOLD_OUT <= timestamp_hold_o; + NX_TIMESTAMP_SYNC_OUT <= nx_timestamp_sync_o; + NX_TIMESTAMP_TRIGGER_OUT <= trigger; end Behavioral; diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index c2c9623..51e8bf5 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -7,13 +7,13 @@ use work.nxyter_components.all; entity nx_histograms is generic ( - BUS_WIDTH : integer := 7; - ENABLE : integer := 1 + BUS_WIDTH : integer := 7; + ENABLE : boolean := true ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - + RESET_HISTS_IN : in std_logic; CHANNEL_STAT_FILL_IN : in std_logic; @@ -32,7 +32,7 @@ entity nx_histograms is DEBUG_OUT : out std_logic_vector(15 downto 0) ); - + end entity; architecture nx_histograms of nx_histograms is @@ -58,138 +58,148 @@ architecture nx_histograms of nx_histograms is begin -hist_enable_1: if ENABLE = 1 generate - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= RESET_IN; - DEBUG_OUT(2) <= RESET_HISTS_IN; - DEBUG_OUT(3) <= reset_hists_r; - DEBUG_OUT(4) <= CHANNEL_STAT_FILL_IN; - DEBUG_OUT(5) <= slv_ack_o; - DEBUG_OUT(6) <= SLV_READ_IN; - DEBUG_OUT(7) <= SLV_WRITE_IN; - DEBUG_OUT(8) <= wait_timer_done; - DEBUG_OUT(15 downto 9) <= CHANNEL_ID_IN; - - ----------------------------------------------------------------------------- - - PROC_CHANNEL_HIST : process (CLK_IN) - variable value : unsigned(31 downto 0); - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then - for I in 0 to (2**BUS_WIDTH - 1) loop - hist_channel_stat(I) <= (others => '0'); - hist_channel_freq(I) <= (others => '0'); - hist_channel_adc(I) <= (others => '0'); - end loop; - wait_timer_init <= x"000_0001"; - else - wait_timer_init <= (others => '0'); - if (wait_timer_done = '1') then + hist_enable_1: if ENABLE = true generate + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= RESET_IN; + DEBUG_OUT(2) <= RESET_HISTS_IN; + DEBUG_OUT(3) <= reset_hists_r; + DEBUG_OUT(4) <= CHANNEL_STAT_FILL_IN; + DEBUG_OUT(5) <= slv_ack_o; + DEBUG_OUT(6) <= SLV_READ_IN; + DEBUG_OUT(7) <= SLV_WRITE_IN; + DEBUG_OUT(8) <= wait_timer_done; + DEBUG_OUT(15 downto 9) <= CHANNEL_ID_IN; + + --------------------------------------------------------------------------- + + PROC_CHANNEL_HIST : process (CLK_IN) + variable value : unsigned(31 downto 0); + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_hists_r = '1' or RESET_HISTS_IN = '1') then for I in 0 to (2**BUS_WIDTH - 1) loop hist_channel_stat(I) <= (others => '0'); - hist_channel_freq(I) <= - (hist_channel_freq(I) + hist_channel_stat(I)) / 2; + hist_channel_freq(I) <= (others => '0'); + hist_channel_adc(I) <= (others => '0'); end loop; - wait_timer_init <= x"5f5_e100"; + wait_timer_init <= x"000_0001"; else - if (CHANNEL_STAT_FILL_IN = '1') then - hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <= - hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1; - - value := (hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) - + unsigned(CHANNEL_ADC_IN)) / 2; - hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) <= value; + wait_timer_init <= (others => '0'); + if (wait_timer_done = '1') then + for I in 0 to (2**BUS_WIDTH - 1) loop + hist_channel_stat(I) <= (others => '0'); + hist_channel_freq(I) <= + (hist_channel_freq(I) + hist_channel_stat(I)) / 2; + end loop; + wait_timer_init <= x"5f5_e100"; + else + if (CHANNEL_STAT_FILL_IN = '1') then + hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) <= + hist_channel_stat(to_integer(unsigned(CHANNEL_ID_IN))) + 1; + + value := (hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) + + unsigned(CHANNEL_ADC_IN)) / 2; + hist_channel_adc(to_integer(unsigned(CHANNEL_ID_IN))) <= value; + end if; end if; end if; end if; - end if; - end process PROC_CHANNEL_HIST; - - -- Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 28 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => wait_timer_init, - TIMER_DONE_OUT => wait_timer_done - ); - - ----------------------------------------------------------------------------- - -- TRBNet Slave Bus - ----------------------------------------------------------------------------- - - -- Give status info to the TRB Slow Control Channel - PROC_HISTOGRAMS_READ: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_no_more_data_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_ack_o <= '0'; - reset_hists_r <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - - reset_hists_r <= '0'; - - if (SLV_READ_IN = '1') then - if (unsigned(SLV_ADDR_IN) >= x"0000" and - unsigned(SLV_ADDR_IN) <= x"007f") then - slv_data_out_o(31 downto 0) <= std_logic_vector( - hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) - ); - slv_ack_o <= '1'; - elsif (unsigned(SLV_ADDR_IN) >= x"0080" and - unsigned(SLV_ADDR_IN) <= x"00ff") then - slv_data_out_o(31 downto 0) <= std_logic_vector( - hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) - ); - slv_ack_o <= '1'; - elsif (unsigned(SLV_ADDR_IN) >= x"0100" and - unsigned(SLV_ADDR_IN) <= x"017f") then - slv_data_out_o(31 downto 0) <= std_logic_vector( - hist_channel_adc(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) - ); - slv_ack_o <= '1'; - else - slv_ack_o <= '0'; - end if; - - elsif (SLV_WRITE_IN = '1') then - - case SLV_ADDR_IN is - - when x"0000" => - reset_hists_r <= '1'; - slv_ack_o <= '1'; - - when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; - end case; + end process PROC_CHANNEL_HIST; + + -- Timer + nx_timer_1: nx_timer + generic map ( + CTR_WIDTH => 28 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + TIMER_START_IN => wait_timer_init, + TIMER_DONE_OUT => wait_timer_done + ); + + --------------------------------------------------------------------------- + -- TRBNet Slave Bus + --------------------------------------------------------------------------- + + -- Give status info to the TRB Slow Control Channel + PROC_HISTOGRAMS_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + slv_data_out_o <= (others => '0'); + slv_no_more_data_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_ack_o <= '0'; + reset_hists_r <= '0'; else - slv_ack_o <= '0'; + slv_data_out_o <= (others => '0'); + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + + reset_hists_r <= '0'; + + if (SLV_READ_IN = '1') then + if (unsigned(SLV_ADDR_IN) >= x"0000" and + unsigned(SLV_ADDR_IN) <= x"007f") then + slv_data_out_o(31 downto 0) <= std_logic_vector( + hist_channel_stat(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) + ); + slv_ack_o <= '1'; + elsif (unsigned(SLV_ADDR_IN) >= x"0080" and + unsigned(SLV_ADDR_IN) <= x"00ff") then + slv_data_out_o(31 downto 0) <= std_logic_vector( + hist_channel_freq(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) + ); + slv_ack_o <= '1'; + elsif (unsigned(SLV_ADDR_IN) >= x"0100" and + unsigned(SLV_ADDR_IN) <= x"017f") then + slv_data_out_o(31 downto 0) <= std_logic_vector( + hist_channel_adc(to_integer(unsigned(SLV_ADDR_IN(7 downto 0)))) + ); + slv_ack_o <= '1'; + else + slv_ack_o <= '0'; + end if; + + elsif (SLV_WRITE_IN = '1') then + + case SLV_ADDR_IN is + + when x"0000" => + reset_hists_r <= '1'; + slv_ack_o <= '1'; + + when others => + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; + end case; + else + slv_ack_o <= '0'; + end if; end if; - end if; - end if; - end process PROC_HISTOGRAMS_READ; - -end generate hist_enable_1; - ----------------------------------------------------------------------------- - -- Output Signals - ----------------------------------------------------------------------------- + end if; + end process PROC_HISTOGRAMS_READ; - -- Slave - SLV_DATA_OUT <= slv_data_out_o; - SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; - SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; - SLV_ACK_OUT <= slv_ack_o; - end nx_histograms; + + --------------------------------------------------------------------------- + -- Output Signals + --------------------------------------------------------------------------- + + -- Slave + SLV_DATA_OUT <= slv_data_out_o; + SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; + SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; + SLV_ACK_OUT <= slv_ack_o; + + end generate hist_enable_1; + + hist_disable_1: if ENABLE = false generate + SLV_DATA_OUT <= (others => '0'); + SLV_NO_MORE_DATA_OUT <= '0'; + SLV_UNKNOWN_ADDR_OUT <= '0'; + SLV_ACK_OUT <= '0'; + end generate hist_disable_1; + +end nx_histograms; diff --git a/nxyter/source/nx_timer.vhd b/nxyter/source/nx_timer.vhd index 23993ea..3417a17 100644 --- a/nxyter/source/nx_timer.vhd +++ b/nxyter/source/nx_timer.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity nx_timer is generic ( - CTR_WIDTH : integer := 12 + CTR_WIDTH : integer range 2 to 32 := 12 ); port( CLK_IN : in std_logic; @@ -18,56 +18,61 @@ end entity; architecture Behavioral of nx_timer is -- Timer + signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0); + signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0); signal timer_done_o : std_logic; type STATES is (S_IDLE, - S_COUNT, - S_DONE + S_COUNT ); - signal STATE : STATES; + signal STATE, NEXT_STATE : STATES; begin - PROC_TIMER: process(CLK_IN) + PROC_TIMER_TRANSFER: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - timer_ctr <= (others => '0'); - timer_done_o <= '0'; - STATE <= S_IDLE; + timer_ctr <= (others => '0'); + STATE <= S_IDLE; else - timer_done_o <= '0'; - + timer_ctr <= timer_ctr_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_TIMER_TRANSFER; + + PROC_TIMER: process(STATE, + TIMER_START_IN, + timer_ctr + ) + begin + + case STATE is + when S_IDLE => + timer_done_o <= '0'; if (TIMER_START_IN > 0) then - timer_ctr <= TIMER_START_IN; - STATE <= S_COUNT; + timer_ctr_x <= TIMER_START_IN - 1; + NEXT_STATE <= S_COUNT; else - case STATE is - when S_IDLE => - if (TIMER_START_IN = 0) then - STATE <= S_IDLE; - else - timer_ctr <= TIMER_START_IN; - STATE <= S_COUNT; - end if; - - when S_COUNT => - if (timer_ctr > 0) then - timer_ctr <= timer_ctr - 1; - STATE <= S_COUNT; - else - STATE <= S_DONE; - end if; + timer_ctr_x <= (others => '0'); + NEXT_STATE <= S_IDLE; + end if; - when S_DONE => - timer_done_o <= '1'; - STATE <= S_IDLE; - - end case; + when S_COUNT => + if (timer_ctr > 0) then + timer_ctr_x <= timer_ctr - 1; + timer_done_o <= '0'; + NEXT_STATE <= S_COUNT; + else + timer_ctr_x <= (others => '0'); + timer_done_o <= '1'; + NEXT_STATE <= S_IDLE; end if; - end if; - end if; + + end case; + end process PROC_TIMER; ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index babd135..a8d2b62 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -658,8 +658,10 @@ begin slv_ack_o <= '1'; when x"0004" => - readout_time_max <= - unsigned(SLV_DATA_IN(11 downto 0)); + if (unsigned(SLV_DATA_IN(11 downto 0)) >= 1) then + readout_time_max <= + unsigned(SLV_DATA_IN(11 downto 0)); + end if; slv_ack_o <= '1'; when others => diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index bf8133f..205d8b3 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -10,14 +10,17 @@ package nxyter_components is component nXyter_FEE_board generic ( - BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + BOARD_ID : std_logic_vector(15 downto 0) ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - CLK_NX_IN : in std_logic; + CLK_NX_MAIN_IN : in std_logic; CLK_ADC_IN : in std_logic; + PLL_NX_CLK_LOCK_IN : in std_logic; + PLL_ADC_CLK_LOCK_IN : in std_logic; + TRIGGER_OUT : out std_logic; I2C_SDA_INOUT : inout std_logic; @@ -29,10 +32,11 @@ package nxyter_components is SPI_SDIO_INOUT : inout std_logic; SPI_CSB_OUT : out std_logic; - NX_CLK128_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; + NX_TIMESTAMP_TRIGGER_OUT : out std_logic; ADC_FCLK_IN : in std_logic_vector(1 downto 0); ADC_DCLK_IN : in std_logic_vector(1 downto 0); @@ -242,21 +246,23 @@ end component; component nxyter_registers port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ADDR_IN : in std_logic_vector(15 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - I2C_SM_RESET_OUT : out std_logic; - I2C_REG_RESET_OUT : out std_logic; - NX_TS_RESET_OUT : out std_logic; - OFFLINE_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) + CLK_IN : in std_logic; + RESET_IN : in std_logic; + PLL_NX_CLK_LOCK_IN : in std_logic; + PLL_ADC_CLK_LOCK_IN : in std_logic; + I2C_SM_RESET_OUT : out std_logic; + I2C_REG_RESET_OUT : out std_logic; + NX_TS_RESET_OUT : out std_logic; + OFFLINE_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ADDR_IN : in std_logic_vector(15 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -331,6 +337,7 @@ component nx_data_receiver port ( CLK_IN : in std_logic; RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; TRIGGER_IN : in std_logic; NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); @@ -409,7 +416,7 @@ end component; component nx_trigger_validate generic ( - BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" + BOARD_ID : std_logic_vector(15 downto 0) ); port ( CLK_IN : in std_logic; @@ -446,7 +453,8 @@ end component; component nx_event_buffer generic ( - BOARD_ID : std_logic_vector(15 downto 0)); + BOARD_ID : std_logic_vector(15 downto 0) + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; @@ -479,7 +487,7 @@ end component; component nx_histograms generic ( BUS_WIDTH : integer; - ENABLE : integer + ENABLE : boolean ); port ( CLK_IN : in std_logic; @@ -499,6 +507,21 @@ component nx_histograms DEBUG_OUT : out std_logic_vector(15 downto 0)); end component; +component ram_dp_128x32 + port ( + WrAddress : in std_logic_vector(6 downto 0); + RdAddress : in std_logic_vector(6 downto 0); + Data : in std_logic_vector(31 downto 0); + WE : in std_logic; + RdClock : in std_logic; + RdClockEn : in std_logic; + Reset : in std_logic; + WrClock : in std_logic; + WrClockEn : in std_logic; + Q : out std_logic_vector(31 downto 0) + ); +end component; + ------------------------------------------------------------------------------- component level_to_pulse @@ -512,7 +535,7 @@ end component; component pulse_to_level generic ( - NUM_CYCLES : unsigned(4 downto 0) := "11111" + NUM_CYCLES : integer range 2 to 15 ); port ( CLK_IN : in std_logic; @@ -522,9 +545,23 @@ component pulse_to_level ); end component; +component pulse_dtrans + generic ( + CLK_RATIO : integer range 2 to 15 + ); + port ( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); +end component; + component Gray_Decoder generic ( - WIDTH : integer + WIDTH : integer range 2 to 32 ); port ( CLK_IN : in std_logic; @@ -536,7 +573,7 @@ end component; component Gray_Encoder generic ( - WIDTH : integer + WIDTH : integer range 2 to 32 ); port ( CLK_IN : in std_logic; @@ -568,22 +605,23 @@ end component; component nx_fpga_timestamp port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - NX_CLK_IN : in std_logic; - TIMESTAMP_SYNC_IN : in std_logic; - TRIGGER_IN : in std_logic; - TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); - TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); - NX_TIMESTAMP_SYNC_OUT : out std_logic; - SLV_READ_IN : in std_logic; - SLV_WRITE_IN : in std_logic; - SLV_DATA_OUT : out std_logic_vector(31 downto 0); - SLV_DATA_IN : in std_logic_vector(31 downto 0); - SLV_ACK_OUT : out std_logic; - SLV_NO_MORE_DATA_OUT : out std_logic; - SLV_UNKNOWN_ADDR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(15 downto 0) + CLK_IN : in std_logic; + RESET_IN : in std_logic; + NX_MAIN_CLK_IN : in std_logic; + TIMESTAMP_SYNC_IN : in std_logic; + TRIGGER_IN : in std_logic; + TIMESTAMP_CURRENT_OUT : out unsigned(11 downto 0); + TIMESTAMP_HOLD_OUT : out unsigned(11 downto 0); + NX_TIMESTAMP_SYNC_OUT : out std_logic; + NX_TIMESTAMP_TRIGGER_OUT : out std_logic; + SLV_READ_IN : in std_logic; + SLV_WRITE_IN : in std_logic; + SLV_DATA_OUT : out std_logic_vector(31 downto 0); + SLV_DATA_IN : in std_logic_vector(31 downto 0); + SLV_ACK_OUT : out std_logic; + SLV_NO_MORE_DATA_OUT : out std_logic; + SLV_UNKNOWN_ADDR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -651,7 +689,7 @@ end component; component nx_timer generic ( - CTR_WIDTH : integer + CTR_WIDTH : integer range 2 to 32 ); port ( CLK_IN : in std_logic; @@ -678,7 +716,8 @@ type debug_array_t is array(integer range <>) of std_logic_vector(15 downto 0); component debug_multiplexer generic ( - NUM_PORTS : integer range 1 to 32); + NUM_PORTS : integer range 1 to 32 + ); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 7386ccb..7cbcaa5 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -18,17 +18,19 @@ entity nXyter_FEE_board is BOARD_ID : std_logic_vector(15 downto 0) := x"ffff" ); port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_NX_IN : in std_logic; - CLK_ADC_IN : in std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_NX_MAIN_IN : in std_logic; + CLK_ADC_IN : in std_logic; + PLL_NX_CLK_LOCK_IN : in std_logic; + PLL_ADC_CLK_LOCK_IN : in std_logic; TRIGGER_OUT : out std_logic; -- I2C Ports - I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line - I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line - I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine - I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers + I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line + I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line + I2C_SM_RESET_OUT : out std_logic; -- reset nXyter I2C SMachine + I2C_REG_RESET_OUT : out std_logic; -- reset I2C registers -- ADC SPI SPI_SCLK_OUT : out std_logic; @@ -36,11 +38,12 @@ entity nXyter_FEE_board is SPI_CSB_OUT : out std_logic; -- nXyter Timestamp Ports - NX_CLK128_IN : in std_logic; - NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); + NX_DATA_CLK_IN : in std_logic; + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; - + NX_TIMESTAMP_TRIGGER_OUT : out std_logic; + -- ADC nXyter Pulse Hight Ports ADC_FCLK_IN : in std_logic_vector(1 downto 0); ADC_DCLK_IN : in std_logic_vector(1 downto 0); @@ -52,17 +55,17 @@ entity nXyter_FEE_board is -- Event Buffer --LVL1 trigger to FEE - LVL1_TRG_DATA_VALID_IN : in std_logic; - LVL1_VALID_TIMING_TRG_IN : in std_logic; - LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- Status + Info TypE - LVL1_INVALID_TRG_IN : in std_logic; - - LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); - LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); - LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); - LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); - + LVL1_TRG_DATA_VALID_IN : in std_logic; + LVL1_VALID_TIMING_TRG_IN : in std_logic; + LVL1_VALID_NOTIMING_TRG_IN : in std_logic; -- Status + Info TypE + LVL1_INVALID_TRG_IN : in std_logic; + + LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0); + LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0); + LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0); + LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0); + --Response from FEE FEE_TRG_RELEASE_OUT : out std_logic; FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0); @@ -72,16 +75,16 @@ entity nXyter_FEE_board is FEE_DATA_ALMOST_FULL_IN : in std_logic; -- TRBNet RegIO Port for the slave bus - REGIO_ADDR_IN : in std_logic_vector(15 downto 0); - REGIO_DATA_IN : in std_logic_vector(31 downto 0); - REGIO_DATA_OUT : out std_logic_vector(31 downto 0); - REGIO_READ_ENABLE_IN : in std_logic; - REGIO_WRITE_ENABLE_IN : in std_logic; - REGIO_TIMEOUT_IN : in std_logic; - REGIO_DATAREADY_OUT : out std_logic; - REGIO_WRITE_ACK_OUT : out std_logic; - REGIO_NO_MORE_DATA_OUT : out std_logic; - REGIO_UNKNOWN_ADDR_OUT : out std_logic; + REGIO_ADDR_IN : in std_logic_vector(15 downto 0); + REGIO_DATA_IN : in std_logic_vector(31 downto 0); + REGIO_DATA_OUT : out std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN : in std_logic; + REGIO_WRITE_ENABLE_IN : in std_logic; + REGIO_TIMEOUT_IN : in std_logic; + REGIO_DATAREADY_OUT : out std_logic; + REGIO_WRITE_ACK_OUT : out std_logic; + REGIO_NO_MORE_DATA_OUT : out std_logic; + REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- Debug Signals DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) @@ -95,107 +98,106 @@ architecture Behavioral of nXyter_FEE_board is ------------------------------------------------------------------------------- -- Signals ------------------------------------------------------------------------------- - -- Clock 256 - signal clk_250_o : std_logic; - - -- Bus Handler - constant NUM_PORTS : integer := 13; - - signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); - signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); - signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0); - signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0); - signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0); - signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0); - signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0); - signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); - - -- TRB Register - signal i2c_sm_reset_o : std_logic; - signal nx_ts_reset_1 : std_logic; - signal nx_ts_reset_2 : std_logic; - signal nx_ts_reset_o : std_logic; - signal i2c_reg_reset_o : std_logic; - - -- NX Register Access - signal i2c_lock : std_logic; - signal i2c_command : std_logic_vector(31 downto 0); - signal i2c_command_busy : std_logic; - signal i2c_data : std_logic_vector(31 downto 0); - signal spi_lock : std_logic; - signal spi_command : std_logic_vector(31 downto 0); - signal spi_command_busy : std_logic; - signal spi_data : std_logic_vector(31 downto 0); - - -- SPI Interface ADC - signal spi_sdi : std_logic; - signal spi_sdo : std_logic; - - -- Data Receiver - signal adc_data_valid : std_logic; - signal adc_new_data : std_logic; - - signal new_timestamp : std_logic_vector(31 downto 0); - signal new_adc_data : std_logic_vector(11 downto 0); - signal new_data : std_logic; - - -- Data Delay - signal new_timestamp_delayed : std_logic_vector(31 downto 0); - signal new_adc_data_delayed : std_logic_vector(11 downto 0); - signal new_data_delayed : std_logic; - signal new_data_fifo_delay : std_logic_vector(6 downto 0); + + -- Bus Handler + constant NUM_PORTS : integer := 13; + + signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_no_more_data : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_ack : std_logic_vector(NUM_PORTS-1 downto 0); + signal slv_addr : std_logic_vector(NUM_PORTS*16-1 downto 0); + signal slv_data_rd : std_logic_vector(NUM_PORTS*32-1 downto 0); + signal slv_data_wr : std_logic_vector(NUM_PORTS*32-1 downto 0); + signal slv_unknown_addr : std_logic_vector(NUM_PORTS-1 downto 0); + + -- TRB Register + signal i2c_sm_reset_o : std_logic; + signal nx_ts_reset_1 : std_logic; + signal nx_ts_reset_2 : std_logic; + signal nx_ts_reset_o : std_logic; + signal i2c_reg_reset_o : std_logic; + + -- NX Register Access + signal i2c_lock : std_logic; + signal i2c_command : std_logic_vector(31 downto 0); + signal i2c_command_busy : std_logic; + signal i2c_data : std_logic_vector(31 downto 0); + signal spi_lock : std_logic; + signal spi_command : std_logic_vector(31 downto 0); + signal spi_command_busy : std_logic; + signal spi_data : std_logic_vector(31 downto 0); + + -- SPI Interface ADC + signal spi_sdi : std_logic; + signal spi_sdo : std_logic; + + -- Data Receiver + signal adc_data_valid : std_logic; + signal adc_new_data : std_logic; + + signal new_timestamp : std_logic_vector(31 downto 0); + signal new_adc_data : std_logic_vector(11 downto 0); + signal new_data : std_logic; + + -- Data Delay + signal new_timestamp_delayed : std_logic_vector(31 downto 0); + signal new_adc_data_delayed : std_logic_vector(11 downto 0); + signal new_data_delayed : std_logic; + signal new_data_fifo_delay : std_logic_vector(6 downto 0); -- Data Validate - signal timestamp : std_logic_vector(13 downto 0); - signal timestamp_channel_id : std_logic_vector(6 downto 0); - signal timestamp_status : std_logic_vector(2 downto 0); - signal adc_data : std_logic_vector(11 downto 0); - signal data_valid : std_logic; - - signal nx_token_return : std_logic; - signal nx_nomore_data : std_logic; - - -- Trigger Validate - signal trigger_data : std_logic_vector(31 downto 0); - signal trigger_data_clk : std_logic; - signal event_buffer_clear : std_logic; - signal trigger_validate_busy : std_logic; - signal validate_nomore_data : std_logic; - - signal trigger_validate_fill : std_logic; - signal trigger_validate_bin : std_logic_vector(6 downto 0); - signal trigger_validate_adc : std_logic_vector(11 downto 0); - - -- Event Buffer - signal trigger_evt_busy : std_logic; - signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); - signal fee_data_o : std_logic_vector(31 downto 0); - signal fee_data_write_o : std_logic; - signal fee_data_finished_o : std_logic; - signal fee_almost_full_i : std_logic; - - -- Trigger Handler - signal trigger : std_logic; - signal timestamp_trigger : std_logic; - signal lvl2_trigger : std_logic; - signal trigger_busy : std_logic; - signal fast_clear : std_logic; - signal nxyter_offline : std_logic; - signal fee_trg_release_o : std_logic; - signal trigger_testpulse : std_logic; + signal timestamp : std_logic_vector(13 downto 0); + signal timestamp_channel_id : std_logic_vector(6 downto 0); + signal timestamp_status : std_logic_vector(2 downto 0); + signal adc_data : std_logic_vector(11 downto 0); + signal data_valid : std_logic; + + signal nx_token_return : std_logic; + signal nx_nomore_data : std_logic; + + -- Trigger Validate + signal trigger_data : std_logic_vector(31 downto 0); + signal trigger_data_clk : std_logic; + signal event_buffer_clear : std_logic; + signal trigger_validate_busy : std_logic; + signal validate_nomore_data : std_logic; + + signal trigger_validate_fill : std_logic; + signal trigger_validate_bin : std_logic_vector(6 downto 0); + signal trigger_validate_adc : std_logic_vector(11 downto 0); + + -- Event Buffer + signal trigger_evt_busy : std_logic; + signal fee_trg_statusbits_o : std_logic_vector(31 downto 0); + signal fee_data_o : std_logic_vector(31 downto 0); + signal fee_data_write_o : std_logic; + signal fee_data_finished_o : std_logic; + signal fee_almost_full_i : std_logic; + + -- Trigger Handler + signal trigger : std_logic; + signal timestamp_trigger : std_logic; + signal lvl2_trigger : std_logic; + signal trigger_busy : std_logic; + signal fast_clear : std_logic; + signal nxyter_offline : std_logic; + signal fee_trg_release_o : std_logic; + signal trigger_testpulse : std_logic; -- FPGA Timestamp - signal timestamp_current : unsigned(11 downto 0); - signal timestamp_hold : unsigned(11 downto 0); - signal nx_timestamp_sync : std_logic; + signal timestamp_current : unsigned(11 downto 0); + signal timestamp_hold : unsigned(11 downto 0); + signal nx_timestamp_sync : std_logic; + signal nx_timestamp_trigger_o : std_logic; -- Trigger Generator - signal trigger_intern : std_logic; - signal nx_testpulse_o : std_logic; + signal trigger_intern : std_logic; + signal nx_testpulse_o : std_logic; -- Debug Handler - constant DEBUG_NUM_PORTS : integer := 13; - signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); + constant DEBUG_NUM_PORTS : integer := 13; + signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); begin @@ -276,7 +278,7 @@ begin BUS_UNKNOWN_ADDR_IN => slv_unknown_addr, -- DEBUG - STAT_DEBUG => open + STAT_DEBUG => open ); @@ -287,7 +289,15 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - + + PLL_NX_CLK_LOCK_IN => PLL_NX_CLK_LOCK_IN, + PLL_ADC_CLK_LOCK_IN => PLL_ADC_CLK_LOCK_IN, + + I2C_SM_RESET_OUT => i2c_sm_reset_o, + I2C_REG_RESET_OUT => i2c_reg_reset_o, + NX_TS_RESET_OUT => nx_ts_reset_1, + OFFLINE_OUT => nxyter_offline, + SLV_READ_IN => slv_read(0), SLV_WRITE_IN => slv_write(0), SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), @@ -296,11 +306,7 @@ begin SLV_ACK_OUT => slv_ack(0), SLV_NO_MORE_DATA_OUT => slv_no_more_data(0), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0), - I2C_SM_RESET_OUT => i2c_sm_reset_o, - I2C_REG_RESET_OUT => i2c_reg_reset_o, - NX_TS_RESET_OUT => nx_ts_reset_1, - OFFLINE_OUT => nxyter_offline, - + DEBUG_OUT => debug_line(0) ); @@ -391,23 +397,24 @@ begin nx_fpga_timestamp_1: nx_fpga_timestamp port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - NX_CLK_IN => CLK_NX_IN, - TIMESTAMP_SYNC_IN => nx_ts_reset_o, - TRIGGER_IN => timestamp_trigger, - TIMESTAMP_CURRENT_OUT => timestamp_current, - TIMESTAMP_HOLD_OUT => timestamp_hold, - NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync, - SLV_READ_IN => open, - SLV_WRITE_IN => open, - SLV_DATA_OUT => open, - SLV_DATA_IN => open, - SLV_ACK_OUT => open, - SLV_NO_MORE_DATA_OUT => open, - SLV_UNKNOWN_ADDR_OUT => open, - - DEBUG_OUT => debug_line(4) + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, + TIMESTAMP_SYNC_IN => nx_ts_reset_o, + TRIGGER_IN => timestamp_trigger, + TIMESTAMP_CURRENT_OUT => timestamp_current, + TIMESTAMP_HOLD_OUT => timestamp_hold, + NX_TIMESTAMP_SYNC_OUT => nx_timestamp_sync, + NX_TIMESTAMP_TRIGGER_OUT => nx_timestamp_trigger_o, + SLV_READ_IN => open, + SLV_WRITE_IN => open, + SLV_DATA_OUT => open, + SLV_DATA_IN => open, + SLV_ACK_OUT => open, + SLV_NO_MORE_DATA_OUT => open, + SLV_UNKNOWN_ADDR_OUT => open, + + DEBUG_OUT => debug_line(4) ); ------------------------------------------------------------------------------- @@ -492,9 +499,10 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, + NX_MAIN_CLK_IN => CLK_NX_MAIN_IN, TRIGGER_IN => lvl2_trigger, - NX_TIMESTAMP_CLK_IN => NX_CLK128_IN, + NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, ADC_CLK_DAT_IN => CLK_ADC_IN, @@ -673,7 +681,7 @@ begin nx_histograms_1: nx_histograms generic map ( BUS_WIDTH => 7, - ENABLE => 1 + ENABLE => false ) port map ( CLK_IN => CLK_IN, @@ -710,6 +718,10 @@ begin I2C_SM_RESET_OUT <= not i2c_sm_reset_o; I2C_REG_RESET_OUT <= not i2c_reg_reset_o; +------------------------------------------------------------------------------- +-- Others +------------------------------------------------------------------------------- + NX_TIMESTAMP_TRIGGER_OUT <= nx_timestamp_trigger_o; ------------------------------------------------------------------------------- -- DEBUG Line Select diff --git a/nxyter/source/nxyter_registers.vhd b/nxyter/source/nxyter_registers.vhd index 9e0d6b4..f2dd7c6 100644 --- a/nxyter/source/nxyter_registers.vhd +++ b/nxyter/source/nxyter_registers.vhd @@ -12,9 +12,14 @@ entity nxyter_registers is -- Monitor PLL Locks PLL_NX_CLK_LOCK_IN : in std_logic; - PLL_ADC_CLK_LOCK_1_IN : in std_logic; - PLL_ADC_CLK_LOCK_2_IN : in std_logic; - + PLL_ADC_CLK_LOCK_IN : in std_logic; + + -- Signals + I2C_SM_RESET_OUT : out std_logic; + I2C_REG_RESET_OUT : out std_logic; + NX_TS_RESET_OUT : out std_logic; + OFFLINE_OUT : out std_logic; + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -24,25 +29,13 @@ entity nxyter_registers is SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; - - -- Signals - I2C_SM_RESET_OUT : out std_logic; - I2C_REG_RESET_OUT : out std_logic; - NX_TS_RESET_OUT : out std_logic; - OFFLINE_OUT : out std_logic; - + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity; architecture Behavioral of nxyter_registers is - - signal slv_data_out_o : std_logic_vector(31 downto 0); - signal slv_no_more_data_o : std_logic; - signal slv_unknown_addr_o : std_logic; - signal slv_ack_o : std_logic; - - + -- I2C Reset signal i2c_sm_reset_start : std_logic; signal i2c_reg_reset_start : std_logic; @@ -64,9 +57,21 @@ architecture Behavioral of nxyter_registers is signal STATE : STATES; -- Wait Timer - signal wait_timer_init : unsigned(7 downto 0); - signal wait_timer_done : std_logic; - + signal wait_timer_init : unsigned(7 downto 0); + signal wait_timer_done : std_logic; + + -- PLL Locks + signal pll_nx_clk_lock_t : std_logic; + signal pll_nx_clk_lock : std_logic; + signal pll_adc_clk_lock_t : std_logic; + signal pll_adc_clk_lock : std_logic; + + -- Slave Bus + signal slv_data_out_o : std_logic_vector(31 downto 0); + signal slv_no_more_data_o : std_logic; + signal slv_unknown_addr_o : std_logic; + signal slv_ack_o : std_logic; + begin DEBUG_OUT(0) <= CLK_IN; @@ -154,6 +159,23 @@ begin end process PROC_I2C_SM_RESET; + PROC_PLL_LOCKS: process (CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + pll_nx_clk_lock_t <= '0'; + pll_nx_clk_lock <= '0'; + pll_adc_clk_lock_t <= '0'; + pll_adc_clk_lock <= '0'; + else + pll_nx_clk_lock_t <= PLL_NX_CLK_LOCK_IN; + pll_nx_clk_lock <= pll_nx_clk_lock_t; + pll_adc_clk_lock_t <= PLL_ADC_CLK_LOCK_IN; + pll_adc_clk_lock <= pll_adc_clk_lock_t; + end if; + end if; + end process PROC_PLL_LOCKS; + ----------------------------------------------------------------------------- -- Slave Bus ----------------------------------------------------------------------------- @@ -210,20 +232,15 @@ begin slv_ack_o <= '1'; when x"0004" => - slv_data_out_o(0) <= PLL_NX_CLK_LOCK_IN; + slv_data_out_o(0) <= pll_nx_clk_lock; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; when x"0005" => - slv_data_out_o(0) <= PLL_ADC_CLK_LOCK_1_IN; + slv_data_out_o(0) <= pll_adc_clk_lock; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - when x"0006" => - slv_data_out_o(0) <= PLL_ADC_CLK_LOCK_2_IN; - slv_data_out_o(31 downto 1) <= (others => '0'); - slv_ack_o <= '1'; - when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/pulse_dtrans.vhd b/nxyter/source/pulse_dtrans.vhd new file mode 100644 index 0000000..2e66bec --- /dev/null +++ b/nxyter/source/pulse_dtrans.vhd @@ -0,0 +1,74 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.nxyter_components.all; + +entity pulse_dtrans is + generic ( + CLK_RATIO : integer range 2 to 15 := 4 + ); + port ( + CLK_A_IN : in std_logic; + RESET_A_IN : in std_logic; + PULSE_A_IN : in std_logic; + CLK_B_IN : in std_logic; + RESET_B_IN : in std_logic; + PULSE_B_OUT : out std_logic + ); + +end entity; + +architecture Behavioral of pulse_dtrans is + + signal pulse_a_l : std_logic; + + signal pulse_b_t : std_logic; + signal pulse_b_l : std_logic; + signal pulse_b_o : std_logic; + +begin + + ----------------------------------------------------------------------------- + -- Clock A Domain + ----------------------------------------------------------------------------- + pulse_to_level_1: pulse_to_level + generic map ( + NUM_CYCLES => CLK_RATIO + ) + port map ( + CLK_IN => CLK_A_IN, + RESET_IN => RESET_A_IN, + PULSE_IN => PULSE_A_IN, + LEVEL_OUT => pulse_a_l + ); + + ----------------------------------------------------------------------------- + -- Clock B Domain + ----------------------------------------------------------------------------- + + PROC_SYNC_PULSE: process(CLK_B_IN) + begin + if( rising_edge(CLK_B_IN) ) then + if( RESET_B_IN = '1' ) then + pulse_b_t <= '0'; + pulse_b_l <= '0'; + else + pulse_b_t <= pulse_a_l; + pulse_b_l <= pulse_b_t; + end if; + end if; + end process PROC_SYNC_PULSE; + + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => CLK_B_IN, + RESET_IN => RESET_B_IN, + LEVEL_IN => pulse_b_l, + PULSE_OUT => pulse_b_o + ); + + -- Outputs + PULSE_B_OUT <= pulse_b_o; + +end Behavioral; diff --git a/nxyter/source/pulse_to_level.vhd b/nxyter/source/pulse_to_level.vhd index 568d4fa..50871ea 100644 --- a/nxyter/source/pulse_to_level.vhd +++ b/nxyter/source/pulse_to_level.vhd @@ -2,11 +2,11 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use nxyter_components.all; +use work.nxyter_components.all; entity pulse_to_level is generic ( - NUM_CYCLES : unsigned(4 downto 0) := "11111" + NUM_CYCLES : integer range 2 to 15 := 4 ); port ( CLK_IN : in std_logic; @@ -20,17 +20,19 @@ end entity; architecture Behavioral of pulse_to_level is - signal start_timer : unsigned(4 downto 0); - signal timer_done : std_logic; - signal level_o : std_logic; + signal start_timer_x : unsigned(4 downto 0); + + signal start_timer : unsigned(4 downto 0); + signal timer_done : std_logic; + signal level_o : std_logic; type STATES is (IDLE, WAIT_TIMER - ); - signal STATE : STATES; + ); + signal STATE, NEXT_STATE : STATES; begin - + nx_timer_1: nx_timer generic map ( CTR_WIDTH => 5 @@ -41,44 +43,55 @@ begin TIMER_START_IN => start_timer, TIMER_DONE_OUT => timer_done ); - - PROC_CONVERT: process(CLK_IN) + + PROC_CONVERT_TRANSFER: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - start_timer <= (others => '0'); - level_o <= '0'; - STATE <= IDLE; + start_timer <= (others => '0'); + STATE <= IDLE; else - level_o <= '0'; - start_timer <= (others => '0'); - - case STATE is + start_timer <= start_timer_x; + STATE <= NEXT_STATE; + end if; + end if; + end process PROC_CONVERT_TRANSFER; + + PROC_CONVERT: process(STATE, + PULSE_IN, + timer_done + ) + constant TIMER_VALUE : + unsigned(4 downto 0) := to_unsigned(NUM_CYCLES - 1, 5); - when IDLE => - if (PULSE_IN = '1') then - level_o <= '1'; - start_timer <= NUM_CYCLES; - STATE <= WAIT_TIMER; - else - STATE <= IDLE; - end if; + begin - when WAIT_TIMER => - level_o <= '1'; - if (timer_done = '1') then - STATE <= IDLE; - else - STATE <= WAIT_TIMER; - end if; + case STATE is + when IDLE => + if (PULSE_IN = '1') then + level_o <= '1'; + start_timer_x <= TIMER_VALUE; + NEXT_STATE <= WAIT_TIMER; + else + level_o <= '0'; + start_timer_x <= (others => '0'); + NEXT_STATE <= IDLE; + end if; - when others => null; + when WAIT_TIMER => + start_timer_x <= (others => '0'); + if (timer_done = '0') then + level_o <= '1'; + NEXT_STATE <= WAIT_TIMER; + else + level_o <= '0'; + NEXT_STATE <= IDLE; + end if; - end case; - end if; - end if; + end case; end process PROC_CONVERT; - LEVEL_OUT <= level_o; - + -- Output Signals + LEVEL_OUT <= level_o; + end Behavioral; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 24da5bb..baa9298 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -4,8 +4,7 @@ 0x8102 : w w: Reset and Sync Timestamps (nXyter and FPGA) 0x8103 : r/w Put nxyter into offline mode 0x8104 : r PLL Lock nXyter Main Clock (250MHz) -0x8105 : r PLL Lock ADC Clock 1 (31.25MHz) -0x8106 : r PLL Lock ADC Clock 2 (31.25MHz) +0x8105 : r PLL Lock ADC Clock (31.25MHz) -- NX I2C Setup Handler 0x8200 : r/w I2C Memeory Register (Depth: 0 - 45 ... 0x822c) diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index dfd1fcb..80d5d26 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -148,12 +148,14 @@ add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" add_file -vhdl -lib "work" "cores/fifo_ts_12to12_dc.vhd" +add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" add_file -vhdl -lib "work" "source/nxyter_components.vhd" add_file -vhdl -lib "work" "source/level_to_pulse.vhd" add_file -vhdl -lib "work" "source/pulse_to_level.vhd" +add_file -vhdl -lib "work" "source/pulse_dtrans.vhd" add_file -vhdl -lib "work" "source/gray_decoder.vhd" add_file -vhdl -lib "work" "source/gray_encoder.vhd" add_file -vhdl -lib "work" "source/nx_timer.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index b044557..b438635 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -48,10 +48,11 @@ entity trb3_periph is NX1_SPI_SCLK_OUT : out std_logic; NX1_SPI_SDIO_INOUT : inout std_logic; NX1_SPI_CSB_OUT : out std_logic; - NX1_CLK128_IN : in std_logic; + NX1_DATA_CLK_IN : in std_logic; NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX1_CLK256A_OUT : out std_logic; + NX1_MAIN_CLK_OUT : out std_logic; NX1_TESTPULSE_OUT : out std_logic; + NX1_TS_HOLD_OUT : out std_logic; NX1_ADC_FCLK_IN : in std_logic; NX1_ADC_DCLK_IN : in std_logic; NX1_ADC_SAMPLE_CLK_OUT : out std_logic; @@ -76,10 +77,11 @@ entity trb3_periph is NX2_SPI_SCLK_OUT : out std_logic; NX2_SPI_SDIO_INOUT : inout std_logic; NX2_SPI_CSB_OUT : out std_logic; - NX2_CLK128_IN : in std_logic; + NX2_DATA_CLK_IN : in std_logic; NX2_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX2_CLK256A_OUT : out std_logic; + NX2_MAIN_CLK_OUT : out std_logic; NX2_TESTPULSE_OUT : out std_logic; + NX2_TS_HOLD_OUT : out std_logic; NX2_ADC_FCLK_IN : in std_logic; NX2_ADC_DCLK_IN : in std_logic; NX2_ADC_SAMPLE_CLK_OUT : out std_logic; @@ -157,10 +159,10 @@ end entity; architecture trb3_periph_arch of trb3_periph is - -- For 250MHz PLL nxyter clock, THE_250M_ODDR_1 - -- attribute ODDRAPPS : string; - -- attribute ODDRAPPS of THE_250M_ODDR_1 : label is "SCLK_ALIGNED"; - -- attribute ODDRAPPS of THE_250M_ODDR_2 : label is "SCLK_ALIGNED"; + -- For 250MHz PLL nxyter clock, THE_32M_ODDR_1 + attribute ODDRAPPS : string; + attribute ODDRAPPS of THE_250M_ODDR_1 : label is "SCLK_ALIGNED"; + attribute ODDRAPPS of THE_250M_ODDR_2 : label is "SCLK_ALIGNED"; --Constants constant REGIO_NUM_STAT_REGS : integer := 5; @@ -282,12 +284,15 @@ architecture trb3_periph_arch of trb3_periph is signal time_counter : unsigned(31 downto 0); -- nXyter-FEB-Board Clocks - signal nx_main_clk : std_logic; + signal nx_main_clk : std_logic; signal pll_nx_clk_lock : std_logic; signal clk_adc_dat_1 : std_logic; signal clk_adc_dat_2 : std_logic; signal pll_adc_clk_lock_1 : std_logic; signal pll_adc_clk_lock_2 : std_logic; + + signal nx1_adc_sample_clk : std_logic; + signal nx2_adc_sample_clk : std_logic; -- nXyter 1 Regio Bus signal nx1_regio_addr_in : std_logic_vector (15 downto 0); @@ -302,7 +307,6 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_regio_unknown_addr_out : std_logic; signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0); - signal nx1_clk128_sim_o : std_logic; signal fee1_trigger : std_logic; -- nXyter 2 Regio Bus @@ -318,7 +322,6 @@ architecture trb3_periph_arch of trb3_periph is signal nx2_regio_unknown_addr_out : std_logic; signal nx2_timestamp_sim_o : std_logic_vector(7 downto 0); - signal nx2_clk128_sim_o : std_logic; signal fee2_trigger : std_logic; begin @@ -697,10 +700,13 @@ begin port map ( CLK_IN => clk_100_i, RESET_IN => reset_i, - CLK_NX_IN => nx_main_clk, + CLK_NX_MAIN_IN => nx_main_clk, CLK_ADC_IN => clk_adc_dat_1, - TRIGGER_OUT => fee1_trigger, + PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock, + PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_1, + TRIGGER_OUT => fee1_trigger, + I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, I2C_SCL_INOUT => NX1_I2C_SCL_INOUT, I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT, @@ -710,19 +716,18 @@ begin SPI_SDIO_INOUT => NX1_SPI_SDIO_INOUT, SPI_CSB_OUT => NX1_SPI_CSB_OUT, - NX_CLK128_IN => NX1_CLK128_IN, + NX_DATA_CLK_IN => NX1_DATA_CLK_IN, NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN, - -- NX_CLK128_IN => nx1_clk128_sim_o, - -- NX_TIMESTAMP_IN => nx1_timestamp_sim_o, NX_RESET_OUT => NX1_RESET_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, - + NX_TIMESTAMP_TRIGGER_OUT => NX1_TS_HOLD_OUT, + ADC_FCLK_IN(0) => NX1_ADC_FCLK_IN, ADC_FCLK_IN(1) => NX1B_ADC_FCLK_IN, ADC_DCLK_IN(0) => NX1_ADC_DCLK_IN, ADC_DCLK_IN(1) => NX1B_ADC_DCLK_IN, - ADC_SAMPLE_CLK_OUT => NX1_ADC_SAMPLE_CLK_OUT, + ADC_SAMPLE_CLK_OUT => nx1_adc_sample_clk, ADC_A_IN(0) => NX1_ADC_A_IN, ADC_A_IN(1) => NX1B_ADC_A_IN, ADC_B_IN(0) => NX1_ADC_B_IN, @@ -775,8 +780,10 @@ begin port map ( CLK_IN => clk_100_i, RESET_IN => reset_i, - CLK_NX_IN => nx_main_clk, + CLK_NX_MAIN_IN => nx_main_clk, CLK_ADC_IN => clk_adc_dat_2, + PLL_NX_CLK_LOCK_IN => pll_nx_clk_lock, + PLL_ADC_CLK_LOCK_IN => pll_adc_clk_lock_2, TRIGGER_OUT => fee2_trigger, I2C_SDA_INOUT => NX2_I2C_SDA_INOUT, @@ -788,17 +795,18 @@ begin SPI_SDIO_INOUT => NX2_SPI_SDIO_INOUT, SPI_CSB_OUT => NX2_SPI_CSB_OUT, - NX_CLK128_IN => NX2_CLK128_IN, + NX_DATA_CLK_IN => NX2_DATA_CLK_IN, NX_TIMESTAMP_IN => NX2_TIMESTAMP_IN, NX_RESET_OUT => NX2_RESET_OUT, NX_TESTPULSE_OUT => NX2_TESTPULSE_OUT, - + NX_TIMESTAMP_TRIGGER_OUT => NX2_TS_HOLD_OUT, + ADC_FCLK_IN(0) => NX2_ADC_FCLK_IN, ADC_FCLK_IN(1) => NX2B_ADC_FCLK_IN, ADC_DCLK_IN(0) => NX2_ADC_DCLK_IN, ADC_DCLK_IN(1) => NX2B_ADC_DCLK_IN, - ADC_SAMPLE_CLK_OUT => NX2_ADC_SAMPLE_CLK_OUT, + ADC_SAMPLE_CLK_OUT => nx2_adc_sample_clk, ADC_A_IN(0) => NX2_ADC_A_IN, ADC_A_IN(1) => NX2B_ADC_A_IN, ADC_B_IN(0) => NX2_ADC_B_IN, @@ -847,7 +855,7 @@ begin -- nXyter Main and ADC Clocks ----------------------------------------------------------------------------- - -- nXyter Main Clock (250/256 MHz) + -- nXyter Main Clock (250MHz) pll_nx_clk250_1: entity work.pll_nx_clk250 port map ( CLK => CLK_PCLK_RIGHT, @@ -855,24 +863,25 @@ begin LOCK => pll_nx_clk_lock ); - NX1_CLK256A_OUT <= nx_main_clk; - NX2_CLK256A_OUT <= nx_main_clk; - - -- THE_250M_ODDR_1: ODDRXD1 - -- port map( - -- SCLK => nx_main_clk, - -- DA => '1', - -- DB => '0', - -- Q => NX1_CLK256A_OUT - -- ); - -- - -- THE_250M_ODDR_2: ODDRXD1 - -- port map( - -- SCLK => nx_main_clk, - -- DA => '1', - -- DB => '0', - -- Q => NX2_CLK256A_OUT - -- ); + --NX1_MAIN_CLK_OUT <= nx_main_clk; + --NX2_MAIN_CLK_OUT <= nx_main_clk; + + -- Drivers for Nxyter Main Clocks + THE_250M_ODDR_1: ODDRXD1 + port map( + SCLK => nx_main_clk, + DA => '1', + DB => '0', + Q => NX1_MAIN_CLK_OUT + ); + + THE_250M_ODDR_2: ODDRXD1 + port map( + SCLK => nx_main_clk, + DA => '1', + DB => '0', + Q => NX2_MAIN_CLK_OUT + ); -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be -- based on same ClockSource as nXyter Main Clock) @@ -890,24 +899,16 @@ begin LOCK => pll_adc_clk_lock_2 ); -------------------------------------------------------------------------------- --- Timestamp Simulator -------------------------------------------------------------------------------- --- nxyter_timestamp_sim_1: nxyter_timestamp_sim --- port map ( --- CLK_IN => CLK_GPLL_LEFT, --- RESET_IN => reset_i, --- TIMESTAMP_OUT => nx1_timestamp_sim_o, --- CLK128_OUT => nx1_clk128_sim_o --- ); + -- ADC Sample Clocks + NX1_ADC_SAMPLE_CLK_OUT <= nx1_adc_sample_clk; + NX2_ADC_SAMPLE_CLK_OUT <= nx2_adc_sample_clk; - --------------------------------------------------------------------------- -- Test Connector - Logic Analyser --------------------------------------------------------------------------- -- TEST_LINE(0) <= clk_100_i; - -- TEST_LINE(1) <= NX1_CLK128_IN; + -- TEST_LINE(1) <= NX1_DATA_CLK_IN; -- TEST_LINE(15 downto 2) <= (others => '0'); diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 69cab84..5468e66 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -11,20 +11,21 @@ BLOCK RD_DURING_WR_PATHS ; # CLK_PCLK_RIGHT : real Oszillator 200MHz # CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities # - # CLK_PCLK_RIGHT --> nx_main_clk 1+2 - # (250/256 MHz) -----> nXyter Main Clock 1+2 + # CLK_PCLK_RIGHT --> nx_main_clk 1+2 + # (250 MHz) -----> nXyter Main Clock 1+2 # | # |----> FPGA Timestamp Entity 1+2 # - # nXyter Main Clock 1+2 --> nXyter Data Clk -----> FPGA Data Receiver - # (* 1/2) | + # nx_main_clk 1+2 --> nXyter Data Clk + # (1/2 = 125MHz) -----> FPGA Data Receiver + # | # |----> Johnson 1/4 --> ADC SCLK # # CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1 - # (nx_main_clk * 3/4) -----> ADC Handler 1 + # (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 1 # # CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2 - # (nx_main_clk * 3/4) -----> ADC Handler 2 + # (nx_main_clk * 3/4 = 187.5) -----> ADC Handler 2 # Speed for the configuration Flash access SYSCONFIG MCCLK_FREQ = 20; @@ -35,8 +36,8 @@ BLOCK RD_DURING_WR_PATHS ; #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT NX1_CLK128_IN 125 MHz; - FREQUENCY PORT NX2_CLK128_IN 125 MHz; + FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; + FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz; USE PRIMARY NET "nx_main_clk"; USE PRIMARY NET "clk_100_i_c"; @@ -79,14 +80,14 @@ MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/trigger_x" 5 ns; # look at .par and .twr.setup file for clocks # and .mrp or errors -PROHIBIT PRIMARY NET "NX1_CLK128_IN_c"; -PROHIBIT SECONDARY NET "NX1_CLK128_IN_c"; +PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; +PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; -PROHIBIT PRIMARY NET "NX2_CLK128_IN_c"; -PROHIBIT SECONDARY NET "NX2_CLK128_IN_c"; +PROHIBIT PRIMARY NET "NX2_DATA_CLK_IN_c"; +PROHIBIT SECONDARY NET "NX2_DATA_CLK_IN_c"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN"; +INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_DATA_CLK_IN"; DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN"; +INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_DATA_CLK_IN"; -- 2.43.0