From 75167560577cc22c352c9963959cc2261c296284 Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 17 Mar 2021 17:08:53 +0100 Subject: [PATCH] Clean up XCKU IP cores - Remove XML files, which are apparently not required - Set build directory for each core - Add build directories to gitignore files - Set XCI options that are otherwise set during build --- media_interfaces/xcku/.gitignore | 1 + .../gth_xcku_2gbps0_100mhz.xci | 2 +- .../gth_xcku_2gbps0_100mhz.xml | 22448 --------------- .../gth_xcku_2gbps0_200mhz.xci | 2 +- .../gth_xcku_2gbps0_200mhz.xml | 22450 ---------------- .../gth_xcku_2gbps4_120mhz.xci | 2 +- .../gth_xcku_2gbps4_120mhz.xml | 22446 --------------- xilinx/xcku/.gitignore | 1 + .../fifo_18x16_dualport_oreg_xcku.xci | 7 +- .../fifo_18x16_dualport_oreg_xcku.xml | 10743 -------- .../xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci | 7 +- .../xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xml | 10740 -------- .../fifo_18x512_oreg_xcku.xci | 2 +- .../fifo_18x512_oreg_xcku.xml | 10745 -------- .../fifo_19x16_obuf_xcku.xci | 7 +- .../fifo_19x16_obuf_xcku.xml | 10744 -------- .../xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci | 7 +- .../xcku/fifo_19x16_xcku/fifo_19x16_xcku.xml | 10744 -------- .../fifo_36x512_oreg_xcku.xci | 2 +- .../fifo_36x512_oreg_xcku.xml | 10748 -------- .../fifo_36x8k_oreg_xcku.xci | 2 +- .../fifo_36x8k_oreg_xcku.xml | 10749 -------- xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci | 2 +- xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xml | 10746 -------- 24 files changed, 33 insertions(+), 153314 deletions(-) create mode 100644 media_interfaces/xcku/.gitignore delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xml delete mode 100644 media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xml create mode 100644 xilinx/xcku/.gitignore delete mode 100644 xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml delete mode 100644 xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xml delete mode 100644 xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xml delete mode 100644 xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml delete mode 100644 xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xml delete mode 100644 xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xml delete mode 100644 xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xml delete mode 100644 xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xml diff --git a/media_interfaces/xcku/.gitignore b/media_interfaces/xcku/.gitignore new file mode 100644 index 0000000..de8b137 --- /dev/null +++ b/media_interfaces/xcku/.gitignore @@ -0,0 +1 @@ +/*/build/ diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci index 2985865..6b43383 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xci @@ -1369,7 +1369,7 @@ IP_Flow 8 TRUE - . + build . 2020.1 diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml b/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml deleted file mode 100644 index 6e15473..0000000 --- a/media_interfaces/xcku/gth_xcku_2gbps0_100mhz/gth_xcku_2gbps0_100mhz.xml +++ /dev/null @@ -1,22448 +0,0 @@ - - - xilinx.com - customized_ip - gth_xcku_2gbps0_100mhz - 1.0 - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - gtwizard_ultrascale_v1_7_8_gtwizard_ultrascale - - - outputProductCRC - 9:1dd46ae3 - - - - - - - gtwiz_userclk_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_tx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk2_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_rx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_usrclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_usrclk2_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_rx_active_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_error_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_error_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_clk_freerun_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_all_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_pll_and_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_pll_and_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_datapath_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_done_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_rx_done_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll0lock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll1lock_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_rx_cdr_stable_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_tx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_rx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_reset_qpll0reset_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_reset_qpll1reset_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe3_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gthe4_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_txoutclk_period_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_cnt_tol_in - - in - - 17 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_gtye4_cpll_cal_bufg_ce_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userdata_tx_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userdata_rx_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - bgbypassb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - bgmonitorenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - bgpdb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - bgrcalovrd_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1F - - - - - - illegal - false - - - - - - bgrcalovrdenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - drpaddr_common_in - - in - - 8 - 0 - - - - wire - xilinx_elaborateports - - - - 0x000 - - - - - - illegal - false - - - - - - drpclk_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - drpdi_common_in - - in - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0000 - - - - - - illegal - false - - - - - - drpen_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - drpwe_common_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtgrefclk0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtgrefclk1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtnorthrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtnorthrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtnorthrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtnorthrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtsouthrefclk00_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtsouthrefclk01_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtsouthrefclk10_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - gtsouthrefclk11_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - pcierateqpll0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pcierateqpll1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - pmarsvd0_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - pmarsvd1_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - qpll0clkrsvd0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll0clkrsvd1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll0fbdiv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll0lockdetclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll0locken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll0pd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpll0refclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpll0reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpll1clkrsvd0_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1clkrsvd1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1fbdiv_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - qpll1lockdetclk_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1locken_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x0 - - - - - - illegal - false - - - - - - qpll1pd_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpll1refclksel_in - - in - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpll1reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - qpllrsvd1_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - qpllrsvd2_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - qpllrsvd3_in - - in - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - qpllrsvd4_in - - in - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0x00 - - - - - - illegal - false - - - - - - rcalenb_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0x1 - - - - - - illegal - false - - - - - - sdm0data_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0toggle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm0width_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1data_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1toggle_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - sdm1width_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tcongpi_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconpowerup_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconreset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - tconrsvdin1_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - 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2 - - - C_ENABLE_COMMON_USRCLK - 0 - - - C_USER_GTPOWERGOOD_DELAY_EN - 0 - - - C_SIM_CPLL_CAL_BYPASS - 1 - - - C_LOCATE_COMMON - 0 - - - C_LOCATE_RESET_CONTROLLER - 0 - - - C_LOCATE_USER_DATA_WIDTH_SIZING - 0 - - - C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_IN_SYSTEM_IBERT_CORE - 1 - - - C_LOCATE_RX_USER_CLOCKING - 1 - - - C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_TX_USER_CLOCKING - 1 - - - C_RESET_CONTROLLER_INSTANCE_CTRL - 0 - - - C_RX_BUFFBYPASS_MODE - 0 - - - C_RX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_RX_BUFFER_MODE - 1 - - - C_RX_CB_DISP - "00000000" - - - C_RX_CB_K - "00000000" - - - C_RX_CB_MAX_LEVEL - 1 - - - C_RX_CB_LEN_SEQ - 1 - - - C_RX_CB_NUM_SEQ - 0 - - - C_RX_CB_VAL - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - - - C_RX_CC_DISP - "00000000" - - - C_RX_CC_ENABLE - 1 - - - C_RESET_SEQUENCE_INTERVAL - 0 - - - C_RX_CC_K - "01010101" - - - C_RX_CC_LEN_SEQ - 4 - - - C_RX_CC_NUM_SEQ - 2 - - - C_RX_CC_PERIODICITY - 5000 - - - C_RX_CC_VAL - "00010100000010111100000101000000101111000001010000001011110000110001010010111100" - - - C_RX_COMMA_M_ENABLE - 1 - - - C_RX_COMMA_M_VAL - "1010000011" - - - C_RX_COMMA_P_ENABLE - 1 - - - C_RX_COMMA_P_VAL - "0101111100" - - - C_RX_DATA_DECODING - 1 - - - C_RX_ENABLE - 1 - - - C_RX_INT_DATA_WIDTH - 20 - - - C_RX_LINE_RATE - 2 - - - C_RX_MASTER_CHANNEL_IDX - 8 - - - C_RX_OUTCLK_BUFG_GT_DIV - 1 - - - C_RX_OUTCLK_FREQUENCY - 100.0000000 - - - C_RX_OUTCLK_SOURCE - 1 - - - C_RX_PLL_TYPE - 2 - - - C_RX_RECCLK_OUTPUT - 0x000000000000000000000000000000000000000000000000 - - - C_RX_REFCLK_FREQUENCY - 100 - - - C_RX_SLIDE_MODE - 0 - - - C_RX_USER_CLOCKING_CONTENTS - 0 - - - C_RX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_RX_USER_CLOCKING_SOURCE - 0 - - - C_RX_USER_DATA_WIDTH - 16 - - - C_RX_USRCLK_FREQUENCY - 100.0000000 - - - C_RX_USRCLK2_FREQUENCY - 100.0000000 - - - C_SECONDARY_QPLL_ENABLE - 0 - - - C_SECONDARY_QPLL_REFCLK_FREQUENCY - 257.8125 - - - C_TOTAL_NUM_CHANNELS - 1 - - - C_TOTAL_NUM_COMMONS - 0 - - - C_TOTAL_NUM_COMMONS_EXAMPLE - 0 - - - C_TXPROGDIV_FREQ_ENABLE - 0 - - - C_TXPROGDIV_FREQ_SOURCE - 2 - - - C_TXPROGDIV_FREQ_VAL - 100 - - - C_TX_BUFFBYPASS_MODE - 0 - - - C_TX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_TX_BUFFER_MODE - 1 - - - C_TX_DATA_ENCODING - 1 - - - C_TX_ENABLE - 1 - - - C_TX_INT_DATA_WIDTH - 20 - - - C_TX_LINE_RATE - 2 - - - C_TX_MASTER_CHANNEL_IDX - 8 - - - C_TX_OUTCLK_BUFG_GT_DIV - 1 - - - C_TX_OUTCLK_FREQUENCY - 100.0000000 - - - C_TX_OUTCLK_SOURCE - 1 - - - C_TX_PLL_TYPE - 2 - - - C_TX_REFCLK_FREQUENCY - 100 - - - C_TX_USER_CLOCKING_CONTENTS - 0 - - - C_TX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_TX_USER_CLOCKING_SOURCE - 0 - - - C_TX_USER_DATA_WIDTH - 16 - - - C_TX_USRCLK_FREQUENCY - 100.0000000 - - - C_TX_USRCLK2_FREQUENCY - 100.0000000 - - - - - - choice_list_00d9575a - 16 - 32 - 64 - - - choice_list_04c1b6c3 - RXOUTCLKPMA - RXOUTCLKPCS - RXPLLREFCLK_DIV1 - RXPROGDIVCLK - - - choice_list_0fbde0c1 - 20 - - - choice_list_13717074 - -20 - -40 - - - choice_list_24871ac1 - AC - DC - - - choice_list_3179277f - QPLL0 - QPLL1 - CPLL - - - choice_list_39947cc7 - TXOUTCLKPMA - TXOUTCLKPCS - TXPLLREFCLK_DIV1 - TXPROGDIVCLK - - - choice_list_556e59ba - 0 - 100 - 200 - 300 - 400 - 500 - 600 - 700 - 800 - 900 - 1000 - 1100 - 1200 - 1300 - 1400 - 1500 - 1600 - 1700 - 1800 - 1900 - 2000 - 2100 - 2200 - 2300 - 2400 - 2500 - 2600 - 2700 - 2800 - 2900 - 3000 - 3100 - 3200 - 3300 - 3400 - 3500 - 3600 - 3700 - 3800 - 3900 - 4000 - 4100 - 4200 - 4300 - 4400 - 4500 - 4600 - 4700 - 4800 - 4900 - 5000 - 5100 - 5200 - 5300 - 5400 - 5500 - 5600 - 5700 - 5800 - 5900 - 6000 - 6100 - 6200 - 6300 - 6400 - 6500 - 6600 - 6700 - 6800 - 6900 - 7000 - 7100 - 7200 - 7300 - 7400 - 7500 - 7600 - 7700 - 7800 - 7900 - 8000 - 8100 - 8200 - 8300 - 8400 - 8500 - 8600 - 8700 - 8800 - 8900 - 9000 - 9100 - 9200 - 9300 - 9400 - 9500 - 9600 - 9700 - 9800 - 9900 - 10000 - - - choice_list_6b979ebc - 250 - - - choice_list_707d3027 - 80 - 100 - 125 - 133.3333333 - 160 - 166.6666667 - 200 - 250 - 266.6666667 - 320 - 333.3333333 - 400 - 500 - 533.3333333 - 666.6666667 - 800 - - - choice_list_7612b160 - X0Y8 - - - choice_list_822b7946 - CPLL - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_b0901792 - 100 - 200 - 400 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 0 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - - false - - - - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 0 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - CPLL - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 100 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 1 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXOUTCLKPMA - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - CPLL - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 100 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - LPM - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.19976 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 4 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00010100000010111100000101000000101111000001010000001011110000110001010010111100 - - - RX_CC_K - 01010101 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - EXAMPLE_DESIGN - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 21 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 5 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 8 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - true - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - - false - - - - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - false - - - - false - - - - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - CPLL - - - - false - - - - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 100 - - - - false - - - - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPO_OUT - -1 - - - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSWING_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSERRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK2_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTDIV_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRESET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCK_OUT - 0 - - - - false - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPHALIGNERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSERR_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRBSLOCKED_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLKOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIDERDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT - 0 - - - - false - - - - - - Component_Name - gth_xcku_2gbps0_100mhz - - - - - UltraScale FPGAs Transceivers Wizard - 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci index 7710d3a..c8cede8 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xci @@ -1369,7 +1369,7 @@ IP_Flow 8 TRUE - . + build . 2020.1 diff --git a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xml b/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xml deleted file mode 100644 index b615140..0000000 --- a/media_interfaces/xcku/gth_xcku_2gbps0_200mhz/gth_xcku_2gbps0_200mhz.xml +++ /dev/null @@ -1,22450 +0,0 @@ - - - xilinx.com - customized_ip - gth_xcku_2gbps0_200mhz - 1.0 - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - gtwizard_ultrascale_v1_7_8_gtwizard_ultrascale - - - outputProductCRC - 9:510310c5 - - - - - - - gtwiz_userclk_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_tx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk_out - 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- illegal - false - - - - - - gtwiz_userclk_rx_active_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_done_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_tx_error_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_start_user_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_buffbypass_rx_done_out - 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- - - 0 - - - - - - illegal - false - - - - - - resetexception_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxbufstatus_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxbyteisaligned_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxbyterealign_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcdrlock_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcdrphdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanbondseq_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanisaligned_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchanrealign_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxchbondo_out - - out - - 4 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxckcaldone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxclkcorcnt_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcominitdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcommadet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxcomsasdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxcomwakedet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxctrl0_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl1_out - - out - - 15 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl2_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxctrl3_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxdata_out - - out - - 127 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdataextendrsvd_out - - out - - 7 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdatavalid_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxdlysresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxelecidle_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxheader_out - - out - - 5 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxheadervalid_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxlfpstresetdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxlfpsu2lpexitdet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxlfpsu3wakedet_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - rxmonitorout_out - - out - - 6 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstarted_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstrobedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxosintstrobestarted_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxoutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxoutclkfabric_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxoutclkpcs_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxphaligndone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxphalignerr_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxpmaresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - rxprbserr_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxprbslocked_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxprgdivresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxqpisenn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxqpisenp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxratedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxrecclkout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - rxsliderdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslipdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslipoutclkrdy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxslippmardy_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxstartofseq_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxstatus_out - - out - - 2 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxsyncout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - rxvalid_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txbufstatus_out - - out - - 1 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - txcomfinish_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txdccdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - txdlysresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txoutclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txoutclkfabric_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txoutclkpcs_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txphaligndone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txphinitdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txpmaresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - txprgdivresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txqpisenn_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txqpisenp_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txratedone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txresetdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - true - - - - - - txsyncdone_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - txsyncout_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - false - - - - - - - - C_CHANNEL_ENABLE - "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000" - - - C_PCIE_ENABLE - 0 - - - C_PCIE_CORECLK_FREQ - 250 - - - C_COMMON_SCALING_FACTOR - 1 - - - C_CPLL_VCO_FREQUENCY - 2000.0 - - - C_FORCE_COMMONS - 0 - - - C_FREERUN_FREQUENCY - 100 - - - C_GT_TYPE - 0 - - - C_GT_REV - 17 - - - C_INCLUDE_CPLL_CAL - 2 - - - C_ENABLE_COMMON_USRCLK - 0 - - - C_USER_GTPOWERGOOD_DELAY_EN - 0 - - - C_SIM_CPLL_CAL_BYPASS - 1 - - - C_LOCATE_COMMON - 0 - - - C_LOCATE_RESET_CONTROLLER - 0 - - - C_LOCATE_USER_DATA_WIDTH_SIZING - 0 - - - C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_IN_SYSTEM_IBERT_CORE - 1 - - - C_LOCATE_RX_USER_CLOCKING - 1 - - - C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_TX_USER_CLOCKING - 1 - - - C_RESET_CONTROLLER_INSTANCE_CTRL - 0 - - - C_RX_BUFFBYPASS_MODE - 0 - - - C_RX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_RX_BUFFER_MODE - 1 - - - C_RX_CB_DISP - "00000000" - - - C_RX_CB_K - "00000000" - - - C_RX_CB_MAX_LEVEL - 1 - - - C_RX_CB_LEN_SEQ - 1 - - - C_RX_CB_NUM_SEQ - 0 - - - C_RX_CB_VAL - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - - - C_RX_CC_DISP - "00000000" - - - C_RX_CC_ENABLE - 1 - - - C_RESET_SEQUENCE_INTERVAL - 0 - - - C_RX_CC_K - "01010101" - - - C_RX_CC_LEN_SEQ - 4 - - - C_RX_CC_NUM_SEQ - 2 - - - C_RX_CC_PERIODICITY - 5000 - - - C_RX_CC_VAL - "00010100000010111100000101000000101111000001010000001011110000110001010010111100" - - - C_RX_COMMA_M_ENABLE - 1 - - - C_RX_COMMA_M_VAL - "1010000011" - - - C_RX_COMMA_P_ENABLE - 1 - - - C_RX_COMMA_P_VAL - "0101111100" - - - C_RX_DATA_DECODING - 1 - - - C_RX_ENABLE - 1 - - - C_RX_INT_DATA_WIDTH - 20 - - - C_RX_LINE_RATE - 2 - - - C_RX_MASTER_CHANNEL_IDX - 8 - - - C_RX_OUTCLK_BUFG_GT_DIV - 1 - - - C_RX_OUTCLK_FREQUENCY - 100.0000000 - - - C_RX_OUTCLK_SOURCE - 1 - - - C_RX_PLL_TYPE - 2 - - - C_RX_RECCLK_OUTPUT - 0x000000000000000000000000000000000000000000000000 - - - C_RX_REFCLK_FREQUENCY - 200 - - - C_RX_SLIDE_MODE - 0 - - - C_RX_USER_CLOCKING_CONTENTS - 0 - - - C_RX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_RX_USER_CLOCKING_SOURCE - 0 - - - C_RX_USER_DATA_WIDTH - 16 - - - C_RX_USRCLK_FREQUENCY - 100.0000000 - - - C_RX_USRCLK2_FREQUENCY - 100.0000000 - - - C_SECONDARY_QPLL_ENABLE - 0 - - - C_SECONDARY_QPLL_REFCLK_FREQUENCY - 257.8125 - - - C_TOTAL_NUM_CHANNELS - 1 - - - C_TOTAL_NUM_COMMONS - 0 - - - C_TOTAL_NUM_COMMONS_EXAMPLE - 0 - - - C_TXPROGDIV_FREQ_ENABLE - 0 - - - C_TXPROGDIV_FREQ_SOURCE - 2 - - - C_TXPROGDIV_FREQ_VAL - 100 - - - C_TX_BUFFBYPASS_MODE - 0 - - - C_TX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_TX_BUFFER_MODE - 1 - - - C_TX_DATA_ENCODING - 1 - - - C_TX_ENABLE - 1 - - - C_TX_INT_DATA_WIDTH - 20 - - - C_TX_LINE_RATE - 2 - - - C_TX_MASTER_CHANNEL_IDX - 8 - - - C_TX_OUTCLK_BUFG_GT_DIV - 1 - - - C_TX_OUTCLK_FREQUENCY - 100.0000000 - - - C_TX_OUTCLK_SOURCE - 1 - - - C_TX_PLL_TYPE - 2 - - - C_TX_REFCLK_FREQUENCY - 200 - - - C_TX_USER_CLOCKING_CONTENTS - 0 - - - C_TX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_TX_USER_CLOCKING_SOURCE - 0 - - - C_TX_USER_DATA_WIDTH - 16 - - - C_TX_USRCLK_FREQUENCY - 100.0000000 - - - C_TX_USRCLK2_FREQUENCY - 100.0000000 - - - - - - choice_list_00d9575a - 16 - 32 - 64 - - - choice_list_0fbde0c1 - 20 - - - choice_list_13717074 - -20 - -40 - - - choice_list_24871ac1 - AC - DC - - - choice_list_3179277f - QPLL0 - QPLL1 - CPLL - - - choice_list_3afc3821 - TXOUTCLKPMA - TXOUTCLKPCS - TXPLLREFCLK_DIV1 - TXPLLREFCLK_DIV2 - TXPROGDIVCLK - - - choice_list_556e59ba - 0 - 100 - 200 - 300 - 400 - 500 - 600 - 700 - 800 - 900 - 1000 - 1100 - 1200 - 1300 - 1400 - 1500 - 1600 - 1700 - 1800 - 1900 - 2000 - 2100 - 2200 - 2300 - 2400 - 2500 - 2600 - 2700 - 2800 - 2900 - 3000 - 3100 - 3200 - 3300 - 3400 - 3500 - 3600 - 3700 - 3800 - 3900 - 4000 - 4100 - 4200 - 4300 - 4400 - 4500 - 4600 - 4700 - 4800 - 4900 - 5000 - 5100 - 5200 - 5300 - 5400 - 5500 - 5600 - 5700 - 5800 - 5900 - 6000 - 6100 - 6200 - 6300 - 6400 - 6500 - 6600 - 6700 - 6800 - 6900 - 7000 - 7100 - 7200 - 7300 - 7400 - 7500 - 7600 - 7700 - 7800 - 7900 - 8000 - 8100 - 8200 - 8300 - 8400 - 8500 - 8600 - 8700 - 8800 - 8900 - 9000 - 9100 - 9200 - 9300 - 9400 - 9500 - 9600 - 9700 - 9800 - 9900 - 10000 - - - choice_list_6b979ebc - 250 - - - choice_list_6c5a0a73 - RXOUTCLKPMA - RXOUTCLKPCS - RXPLLREFCLK_DIV1 - RXPLLREFCLK_DIV2 - RXPROGDIVCLK - - - choice_list_707d3027 - 80 - 100 - 125 - 133.3333333 - 160 - 166.6666667 - 200 - 250 - 266.6666667 - 320 - 333.3333333 - 400 - 500 - 533.3333333 - 666.6666667 - 800 - - - choice_list_7612b160 - X0Y8 - - - choice_list_822b7946 - CPLL - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_b0901792 - 100 - 200 - 400 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 0 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - - false - - - - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 0 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 100.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - CPLL - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 200 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 1 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXOUTCLKPMA - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - CPLL - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 200 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - LPM - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.19976 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 4 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00010100000010111100000101000000101111000001010000001011110000110001010010111100 - - - RX_CC_K - 01010101 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - EXAMPLE_DESIGN - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 23 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 5 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 8 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - true - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - - false - - - - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - false - - - - false - - - - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - CPLL - - - - false - - - - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 100 - - - - false - - - - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - 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- false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDADDR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDEN_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDI_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDWE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDO_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBTXUART_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPDIR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSQ_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CDRSTEPSX_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CFGRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CLKRSVD1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFREQLOCK_IN - -1 - - - - false - - - - - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHICALSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIDWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EVODDPHIXWREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANRESET_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_EYESCANTRIGGER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_FREQOS_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTHRXP_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK0_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRESETSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRSVD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTRXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK0_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK1_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTTXRESETSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_INCPCTRL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTYRXP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPBACK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LOOPRSVD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKRXTXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_LPBKTXRXSEREN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEEQRXEQADAPTDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTIDLE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERSTTXSYNCSTART_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIEUSERRATEDONE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCSRSVDIN2_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FREQLOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLK_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RESETOVRD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RSTCLKENTX_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RX8B10BEN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXAFECFOKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXBUFRESET_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRFREQRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRHOLD_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDROVRDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRRESET_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCDRRESETRSV_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDEN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDI_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDLEVEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDMASTER_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCHBONDSLAVE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXCKCALRESET_IN - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT - 0 - - - - false - - - - - - Component_Name - gth_xcku_2gbps0_200mhz - - - - - UltraScale FPGAs Transceivers Wizard - 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - diff --git a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci b/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci index e4a72e5..7fec2d3 100644 --- a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci +++ b/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xci @@ -1369,7 +1369,7 @@ IP_Flow 8 TRUE - . + build . 2020.1 diff --git a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xml b/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xml deleted file mode 100644 index 98bade8..0000000 --- a/media_interfaces/xcku/gth_xcku_2gbps4_120mhz/gth_xcku_2gbps4_120mhz.xml +++ /dev/null @@ -1,22446 +0,0 @@ - - - xilinx.com - customized_ip - gth_xcku_2gbps4_120mhz - 1.0 - - - - xilinx_elaborateports - Elaborate Ports - :vivado.xilinx.com:elaborate.ports - gtwizard_ultrascale_v1_7_8_gtwizard_ultrascale - - - outputProductCRC - 9:7418d113 - - - - - - - gtwiz_userclk_tx_reset_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_active_in - - in - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - required - true - - - - - - gtwiz_userclk_tx_srcclk_out - - out - - 0 - 0 - - - - wire - xilinx_elaborateports - - - - 0 - - - - - - illegal - false - - - - - - gtwiz_userclk_tx_usrclk_out - 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2 - - - C_ENABLE_COMMON_USRCLK - 0 - - - C_USER_GTPOWERGOOD_DELAY_EN - 0 - - - C_SIM_CPLL_CAL_BYPASS - 1 - - - C_LOCATE_COMMON - 0 - - - C_LOCATE_RESET_CONTROLLER - 0 - - - C_LOCATE_USER_DATA_WIDTH_SIZING - 0 - - - C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_IN_SYSTEM_IBERT_CORE - 1 - - - C_LOCATE_RX_USER_CLOCKING - 1 - - - C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER - 0 - - - C_LOCATE_TX_USER_CLOCKING - 1 - - - C_RESET_CONTROLLER_INSTANCE_CTRL - 0 - - - C_RX_BUFFBYPASS_MODE - 0 - - - C_RX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_RX_BUFFER_MODE - 1 - - - C_RX_CB_DISP - "00000000" - - - C_RX_CB_K - "00000000" - - - C_RX_CB_MAX_LEVEL - 1 - - - C_RX_CB_LEN_SEQ - 1 - - - C_RX_CB_NUM_SEQ - 0 - - - C_RX_CB_VAL - "00000000000000000000000000000000000000000000000000000000000000000000000000000000" - - - C_RX_CC_DISP - "00000000" - - - C_RX_CC_ENABLE - 1 - - - C_RESET_SEQUENCE_INTERVAL - 0 - - - C_RX_CC_K - "01010101" - - - C_RX_CC_LEN_SEQ - 4 - - - C_RX_CC_NUM_SEQ - 2 - - - C_RX_CC_PERIODICITY - 5000 - - - C_RX_CC_VAL - "00010100000010111100000101000000101111000001010000001011110000110001010010111100" - - - C_RX_COMMA_M_ENABLE - 1 - - - C_RX_COMMA_M_VAL - "1010000011" - - - C_RX_COMMA_P_ENABLE - 1 - - - C_RX_COMMA_P_VAL - "0101111100" - - - C_RX_DATA_DECODING - 1 - - - C_RX_ENABLE - 1 - - - C_RX_INT_DATA_WIDTH - 20 - - - C_RX_LINE_RATE - 2.4 - - - C_RX_MASTER_CHANNEL_IDX - 8 - - - C_RX_OUTCLK_BUFG_GT_DIV - 1 - - - C_RX_OUTCLK_FREQUENCY - 120.0000000 - - - C_RX_OUTCLK_SOURCE - 1 - - - C_RX_PLL_TYPE - 2 - - - C_RX_RECCLK_OUTPUT - 0x000000000000000000000000000000000000000000000000 - - - C_RX_REFCLK_FREQUENCY - 120 - - - C_RX_SLIDE_MODE - 0 - - - C_RX_USER_CLOCKING_CONTENTS - 0 - - - C_RX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_RX_USER_CLOCKING_SOURCE - 0 - - - C_RX_USER_DATA_WIDTH - 16 - - - C_RX_USRCLK_FREQUENCY - 120.0000000 - - - C_RX_USRCLK2_FREQUENCY - 120.0000000 - - - C_SECONDARY_QPLL_ENABLE - 0 - - - C_SECONDARY_QPLL_REFCLK_FREQUENCY - 257.8125 - - - C_TOTAL_NUM_CHANNELS - 1 - - - C_TOTAL_NUM_COMMONS - 0 - - - C_TOTAL_NUM_COMMONS_EXAMPLE - 0 - - - C_TXPROGDIV_FREQ_ENABLE - 0 - - - C_TXPROGDIV_FREQ_SOURCE - 2 - - - C_TXPROGDIV_FREQ_VAL - 120 - - - C_TX_BUFFBYPASS_MODE - 0 - - - C_TX_BUFFER_BYPASS_INSTANCE_CTRL - 0 - - - C_TX_BUFFER_MODE - 1 - - - C_TX_DATA_ENCODING - 1 - - - C_TX_ENABLE - 1 - - - C_TX_INT_DATA_WIDTH - 20 - - - C_TX_LINE_RATE - 2.4 - - - C_TX_MASTER_CHANNEL_IDX - 8 - - - C_TX_OUTCLK_BUFG_GT_DIV - 1 - - - C_TX_OUTCLK_FREQUENCY - 120.0000000 - - - C_TX_OUTCLK_SOURCE - 1 - - - C_TX_PLL_TYPE - 2 - - - C_TX_REFCLK_FREQUENCY - 120 - - - C_TX_USER_CLOCKING_CONTENTS - 0 - - - C_TX_USER_CLOCKING_INSTANCE_CTRL - 0 - - - C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK - 1 - - - C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 - 1 - - - C_TX_USER_CLOCKING_SOURCE - 0 - - - C_TX_USER_DATA_WIDTH - 16 - - - C_TX_USRCLK_FREQUENCY - 120.0000000 - - - C_TX_USRCLK2_FREQUENCY - 120.0000000 - - - - - - choice_list_00d9575a - 16 - 32 - 64 - - - choice_list_04c1b6c3 - RXOUTCLKPMA - RXOUTCLKPCS - RXPLLREFCLK_DIV1 - RXPROGDIVCLK - - - choice_list_0fbde0c1 - 20 - - - choice_list_13717074 - -20 - -40 - - - choice_list_24871ac1 - AC - DC - - - choice_list_39947cc7 - TXOUTCLKPMA - TXOUTCLKPCS - TXPLLREFCLK_DIV1 - TXPROGDIVCLK - - - choice_list_556e59ba - 0 - 100 - 200 - 300 - 400 - 500 - 600 - 700 - 800 - 900 - 1000 - 1100 - 1200 - 1300 - 1400 - 1500 - 1600 - 1700 - 1800 - 1900 - 2000 - 2100 - 2200 - 2300 - 2400 - 2500 - 2600 - 2700 - 2800 - 2900 - 3000 - 3100 - 3200 - 3300 - 3400 - 3500 - 3600 - 3700 - 3800 - 3900 - 4000 - 4100 - 4200 - 4300 - 4400 - 4500 - 4600 - 4700 - 4800 - 4900 - 5000 - 5100 - 5200 - 5300 - 5400 - 5500 - 5600 - 5700 - 5800 - 5900 - 6000 - 6100 - 6200 - 6300 - 6400 - 6500 - 6600 - 6700 - 6800 - 6900 - 7000 - 7100 - 7200 - 7300 - 7400 - 7500 - 7600 - 7700 - 7800 - 7900 - 8000 - 8100 - 8200 - 8300 - 8400 - 8500 - 8600 - 8700 - 8800 - 8900 - 9000 - 9100 - 9200 - 9300 - 9400 - 9500 - 9600 - 9700 - 9800 - 9900 - 10000 - - - choice_list_6b979ebc - 250 - - - choice_list_7612b160 - X0Y8 - - - choice_list_818913bc - 96 - 120 - 150 - 160 - 192 - 200 - 240 - 300 - 320 - 384 - 400 - 480 - 600 - 640 - 800 - - - choice_list_822b7946 - CPLL - - - choice_list_98c4d361 - 257.8125 - - - choice_list_a0d11b39 - 100 - 200 - 250 - 300 - 350 - 400 - 500 - 550 - 600 - 700 - 800 - 850 - 900 - 950 - 1000 - 1100 - - - choice_list_a533ccf9 - 250 - 125 - 62.5 - - - choice_list_afcf1f92 - GTH - - - choice_list_afd99295 - 120 - 240 - 480 - - - choice_list_be18be20 - 6 - 7 - 8 - 9 - 10 - 11 - 12 - 13 - 14 - 15 - - - choice_list_de3f4419 - QPLL1 - CPLL - - - choice_list_e6469819 - 1 - 2 - 4 - - - choice_pairs_03018cc1 - 1 - 2 - 0 - - - choice_pairs_0c77e1fe - 0 - 1 - - - choice_pairs_1040277f - AVTT - FLOAT - GND - PROGRAMMABLE - - - choice_pairs_1436b008 - MULTI - SINGLE - - - choice_pairs_1ebf969f - None - GTH-10GBASE-KR - GTH-10GBASE-R - GTH-12G_SDI - GTH-1G_10G_25G_switchable - GTH-3G_SDI - GTH-Aurora_64B66B - GTH-Aurora_8B10B - GTH-Bandwidth_Engine - GTH-CAUI_10 - GTH-CEI_11G_SR - GTH-CPRI_10G - GTH-CPRI_10_1G - GTH-CPRI_3G - GTH-CPRI_6G - GTH-DisplayPort_1_62G - GTH-DisplayPort_2_7G - GTH-DisplayPort_5_4G - GTH-Gigabit_Ethernet - GTH-HDMI - GTH-HD_SDI - GTH-HMC_12_5G - GTH-Interlaken_10G - GTH-Interlaken_12_5G - GTH-Interlaken_6_25G - GTH-JESD204 - GTH-JESD204_3_125G - GTH-JESD204_6_375G - GTH-OTL4_10 - GTH-OTU2 - GTH-OTU2e - GTH-QSGMII - GTH-RXAUI - GTH-SATA - GTH-SRIO_Gen2 - GTH-XAUI - GTH-XLAUI - - - choice_pairs_40d02874 - 10GBASE_KR - CUSTOM - PCIE_GEN1_GEN2 - PCIE_GEN3 - QPI - - - choice_pairs_4e550952 - NONE - EXAMPLE_DESIGN - - - choice_pairs_7b0c3758 - RX - BOTH - TX - - - choice_pairs_85f99b7f - K28.1 - K28.5 - NONE - - - choice_pairs_8846c8f0 - RAW - 8B10B - 64B66B - 64B66B_CAUI - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_88c85933 - 8B10B - 64B66B_ASYNC - 64B66B_ASYNC_CAUI - RAW - 64B66B - 64B66B_CAUI - 64B67B - 64B67B_CAUI - - - choice_pairs_93c2d4ee - CORE - EXAMPLE_DESIGN - - - choice_pairs_9c19f015 - 1 - 2 - - - choice_pairs_a537ddda - 0 - 1 - - - choice_pairs_aa541099 - AUTO - DFE - LPM - - - choice_pairs_ae574462 - OFF - PCS - PMA - AUTO - - - choice_pairs_b0974ef0 - 1 - 2 - 0 - - - choice_pairs_d4feb97d - DISABLE - ENABLE - - - choice_pairs_f05b8192 - CHANNEL - NAME - - - The UltraScale FPGAs Transceivers Wizard provides a simple and robust method of configuring one or more serial transceivers in UltraScale and UltraScale+ devices. Start from scratch, or use a configuration preset to target an industry standard. The highly flexible Transceivers Wizard generates a customized IP core for the transceivers, configuration options, and enabled ports you've selected, optionally including a variety of helper blocks to simplify common functionality. In addition, it can produce an example design for simple simulation and hardware usage demonstration. - - - GT_TYPE - Transceiver type - For devices which contain more than one serial transceiver type, select the type of transceiver to configure - GTH - - - INTERNAL_GT_PRIM_TYPE - gthe3 - - - - false - - - - - - GT_REV - Transceiver revision - Select the serial transceiver silicon revision - 0 - - - GT_DIRECTION - Transmit and/or Receive direction - Enable transmit and/or receive - BOTH - - - RX_ENABLE - Enabled - Enable the receiver for use - true - - - - false - - - - - - TX_ENABLE - Enabled - Enable the transmitter for use - true - - - - false - - - - - - CHANNEL_ENABLE - Enable channel - Indicate whether this transceiver channel is instantiated and enabled for use - X0Y8 - - - TX_MASTER_CHANNEL - Master TX channel - Designate an enabled transceiver as the master TX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - RX_MASTER_CHANNEL - Master RX channel - Designate an enabled transceiver as the master RX channel for various purposes such as user clock generation and buffer bypass (if selected) - X0Y8 - - - - false - - - - - - INTERNAL_TOTAL_NUM_CHANNELS - Total number of channels - 1 - - - - false - - - - - - INTERNAL_TOTAL_NUM_COMMONS - Total number of commons required - 0 - - - - false - - - - - - LOCATE_COMMON - Include transceiver COMMON in the - If a QPLL is used for either the transmitter or the receiver, indicate whether the transceiver COMMON block is instantiated within the core, or outside of the core in the example design. Exclusion from the core may allow placement of separate but compatible transceiver interfaces within a single quad. - CORE - - - - false - - - - - - INTERNAL_NUM_COMMONS_CORE - Number of commons in core - 0 - - - - false - - - - - - INTERNAL_NUM_COMMONS_EXAMPLE - Number of commons in example - 0 - - - - false - - - - - - INTERNAL_TX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - INTERNAL_RX_USRCLK_FREQUENCY - 120.0000000 - - - - false - - - - - - RX_PPM_OFFSET - PPM offset between receiver and transmitter - Specify the PPM offset between received data and transmitted data - 0 - - - OOB_ENABLE - Enable Out of Band signaling (OOB)/Electrical Idle - Enable or disable Out of Band signaling (OOB)/Electrical Idle - false - - - - false - - - - - - RX_SSC_PPM - Spread spectrum clocking - Specify the spread spectrum clocking modulation in PPM - 0 - - - INS_LOSS_NYQ - Insertion loss at Nyquist (dB) - Indicate the transmitter to receiver insertion loss at the Nyquist frequency, in dB - 20 - - - PCIE_CORECLK_FREQ - 250 - - - PCIE_USERCLK_FREQ - 250 - - - TX_LINE_RATE - Line rate (Gb/s) - Enter the transmitter line rate in Gb/s - 2.4 - - - TX_PLL_TYPE - PLL type - Select the transmitter PLL type - CPLL - - - TX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a transmitter reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - TX_DATA_ENCODING - Encoding - Select the encoding format for data transmission, or choose 'Raw' for no data encoding - 8B10B - - - TX_USER_DATA_WIDTH - User data width - Select the width at which the user logic will provide parallel data to the serial transceiver for transmission - 16 - - - TX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal transmitter data path - 20 - - - TX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the transmitter buffer - 1 - - - TX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and transmitter line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect transmitter reference clock options including current selection - 0 - - - - false - - - - - - TX_OUTCLK_SOURCE - TXOUTCLK source - Select the source of TXOUTCLK - TXOUTCLKPMA - - - TX_DIFF_SWING_EMPH_MODE - Differential swing and emphasis mode - Select the transmitter differential swing and emphasis mode for your application - CUSTOM - - - RX_LINE_RATE - Line rate (Gb/s) - Enter the receiver line rate in Gb/s - 2.4 - - - RX_PLL_TYPE - PLL type - Select the receiver PLL type - CPLL - - - RX_REFCLK_FREQUENCY - Actual Reference clock (MHz) - Select a receiver reference clock frequency from among those supported for the selected line rate and PLL type - 120 - - - RX_DATA_DECODING - Decoding - Select the decoding format for data reception, or choose 'Raw' for no data decoding - 8B10B - - - RX_USER_DATA_WIDTH - User data width - Select the width at which the serial transceiver will provide received parallel data to the user logic - 16 - - - RX_INT_DATA_WIDTH - Internal data width - Select the width of the serial transceiver internal receiver data path - 20 - - - RX_BUFFER_MODE - Buffer - Select whether to enable or to bypass the receiver elastic buffer - 1 - - - RX_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and receiver line rates, enter the numerator which produces the desired 24-bit fractional part of the QPLL feedback divider as displayed. Note that changes affect receiver reference clock options including current selection. When receiver and transmitter share a QPLL, values must match and are set by the transmitter selection - 0 - - - - false - - - - - - RX_EQ_MODE - Equalization mode - Specify the equalization mode, or allow the core to select a mode. Refer to the product guide for guidelines on selecting between DFE and LPM modes. - LPM - - - RX_JTOL_FC - Mask corner frequency (MHz) - Refer to the product guide for guidelines on setting jitter tolerance mask corner frequency. - 1.4397121 - - - RX_JTOL_LF_SLOPE - Mask low frequency slope (dB/decade) - Refer to the product guide for guidelines on setting jitter tolerance mask low frequency slope. - -20 - - - RX_OUTCLK_SOURCE - RXOUTCLK source - Select the source of RXOUTCLK - RXOUTCLKPMA - - - SIM_CPLL_CAL_BYPASS - 1 - - - PCIE_ENABLE - false - - - RX_TERMINATION - Termination - Select the receiver termination - PROGRAMMABLE - - - RX_TERMINATION_PROG_VALUE - Programmable termination voltage (mV) - Select the termination voltage (in mV) when in programmable mode - 800 - - - RX_COUPLING - Link coupling - Select the link coupling - AC - - - RX_BUFFER_BYPASS_MODE - Receiver elastic buffer bypass mode - Control whether the receiver elastic buffer bypass operates in multi-lane mode or single-lane mode - MULTI - - - - false - - - - - - RX_BUFFER_RESET_ON_CB_CHANGE - Reset receiver elastic buffer on channel bonding change - Control whether the receiver elastic buffer is reset on change to RXCHANBONDMASTER, RXCHANBONDSLAVE or RXCHANBONDLEVEL - ENABLE - - - - false - - - - - - RX_BUFFER_RESET_ON_COMMAALIGN - Reset receiver elastic buffer on comma alignment - Control whether the receiver elastic buffer is reset on comma alignment - DISABLE - - - RX_BUFFER_RESET_ON_RATE_CHANGE - Reset receiver elastic buffer on rate change - Control whether the receiver elastic buffer is reset on rate change - ENABLE - - - TX_BUFFER_RESET_ON_RATE_CHANGE - Reset transmitter buffer on rate change - Control whether the transmitter buffer is reset on rate change - ENABLE - - - RESET_SEQUENCE_INTERVAL - Reset sequence time interval (ns) - Select 0 to specify that all transceiver elements are reset in parallel when the reset controller helper block is used (default behavior). If sequential transceiver element resets are desired in order to mitigate the transient load requirements of the power supplies, then select a nonzero value to specify the time interval, in nanoseconds, between reset state changes of those transceiver elements. When the reset controller helper block is used, the Wizard performs the sequencing and enforces the time interval - 0 - - - RX_COMMA_PRESET - Comma value preset - K28.5 - - - RX_COMMA_VALID_ONLY - Valid comma values for 8B/10B decoding - Select the range of comma characters decoded by the 8B/10B decoder - 0 - - - RX_COMMA_P_ENABLE - Detect plus comma - Indicate whether or not the specified bit pattern is detected as a plus comma - true - - - RX_COMMA_M_ENABLE - Detect minus comma - Indicate whether or not the specified bit pattern is detected as a minus comma - true - - - RX_COMMA_DOUBLE_ENABLE - Detect combined plus/minus (double-length) comma - Indicate whether or not the comma detection block searches for the specified plus comma and minus comma bit patterns together in sequence - false - - - RX_COMMA_P_VAL - Plus comma value - Specify the bit pattern for plus comma detection, where the rightmost bit is the first bit received - 0101111100 - - - RX_COMMA_M_VAL - Minus comma value - Specify the bit pattern for minus comma detection, where the rightmost bit is the first bit received - 1010000011 - - - RX_COMMA_MASK - Mask - Set any bit in the mask field to 0 to make the corresponding bit of the specified plus and minus comma values a "don't care" - 1111111111 - - - RX_COMMA_ALIGN_WORD - Alignment boundary - Select which data byte boundaries are allowed for comma alignment - 2 - - - RX_COMMA_SHOW_REALIGN_ENABLE - Show realign comma - Indicate whether or not commas that cause realignment are brought out to the RXDATA port. Disable to reduce receiver data path latency - true - - - RX_SLIDE_MODE - Manual alignment (RXSLIDE) mode - Select whether to enable manual alignment, and in what mode if enabled - OFF - - - RX_CB_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable channel bonding, and how many sequences to use if enabled - 0 - - - - false - - - - - - RX_CB_LEN_SEQ - Length of each sequence - Select the number of characters in each channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_SKEW - Sequence maximum skew - Select a channel bonding maximum skew value which is less than half the minimum distance between instances of the channel bonding sequence - 1 - - - - false - - - - - - RX_CB_MAX_LEVEL - Maximum channel bonding level to be used - Select the maximum channel bonding level that will be used in the system channel bonding topology - 1 - - - - false - - - - - - RX_CB_MASK - 00000000 - - - - false - - - - - - RX_CB_VAL - 00000000000000000000000000000000000000000000000000000000000000000000000000000000 - - - - false - - - - - - RX_CB_K - 00000000 - - - - false - - - - - - RX_CB_DISP - 00000000 - - - - false - - - - - - RX_CB_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_0_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_0_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_0 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_0 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_1 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_1 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_2 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_2 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CB_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a channel bonding sequence - false - - - - false - - - - - - RX_CB_VAL_1_3 - Value - Specify the value for this channel bonding sequence and pattern - 00000000 - - - - false - - - - - - RX_CB_K_1_3 - K character - Indicate whether or not the corresponding channel bonding value is a K character - false - - - - false - - - - - - RX_CB_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding channel bonding value uses inverted disparity to signify control a character via deliberate error - false - - - - false - - - - - - RX_CC_NUM_SEQ - Enable and select number of sequences to use - Select whether to enable clock correction, and how many sequences to use if enabled - 2 - - - RX_CC_LEN_SEQ - Length of each sequence - Select the number of characters in each channel clock correction sequence - 4 - - - RX_CC_PERIODICITY - Periodicity of the sequence (in bytes) - Specify the separation between clock correction sequences, in bytes - 5000 - - - RX_CC_KEEP_IDLE - Keep idle - Control whether at least one clock correction sequence is kept in the data stream for every continuous stream of clock correction sequences received - ENABLE - - - RX_CC_PRECEDENCE - Precedence - Control whether clock correction takes precedence over channel bonding when both operations are triggered at the same time - ENABLE - - - - false - - - - - - RX_CC_REPEAT_WAIT - Minimum repetition - Specify the number of RXUSRCLK cycles following a clock correction during which the elastic buffer is not permitted to execute another clock correction - 0 - - - RX_CC_MASK - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - 00000000 - - - - false - - - - - - RX_CC_VAL - 00010100000010111100000101000000101111000001010000001011110000110001010010111100 - - - RX_CC_K - 01010101 - - - - false - - - - - - RX_CC_DISP - 00000000 - - - - false - - - - - - RX_CC_MASK_0_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_1 - Value - Specify the value for this clock correction sequence and pattern - 11000101 - - - RX_CC_K_0_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_0_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_0_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_0_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_0_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_0_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_0_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_0 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_0 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_0 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_0 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_1 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_1 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_1 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_1 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_2 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_2 - Value - Specify the value for this clock correction sequence and pattern - 10111100 - - - RX_CC_K_1_2 - K character - Indicate whether or not the corresponding clock correction value is a K character - true - - - RX_CC_DISP_1_2 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - RX_CC_MASK_1_3 - Don't care - Mark this pattern "don't care" to always consider it as a match within a clock correction sequence - false - - - RX_CC_VAL_1_3 - Value - Specify the value for this clock correction sequence and pattern - 01010000 - - - RX_CC_K_1_3 - K character - Indicate whether or not the corresponding clock correction value is a K character - false - - - RX_CC_DISP_1_3 - Inverted disparity - Indicate whether or not the corresponding clock correction value uses inverted disparity to signify control a character via deliberate error - false - - - ENABLE_OPTIONAL_PORTS - Enable optional ports - Indicate whether a port should be included - rxcdrreset_in rxpcsreset_in rxpmareset_in txpcsreset_in txpippmen_in txpippmovrden_in txpippmpd_in txpippmsel_in txpippmstepsize_in txpmareset_in rxresetdone_out txbufstatus_out txresetdone_out - - - RX_REFCLK_SOURCE - Receiver reference clock source - Select a reference clock input to drive the PLL chosen for receiver operation - X0Y8 clk0+2 - - - TX_REFCLK_SOURCE - Transmitter reference clock source - Select a reference clock input to drive the PLL chosen for transmitter operation - X0Y8 clk0+2 - - - RX_RECCLK_OUTPUT - Drive recovered clock out of device - Indicate whether this transceiver channel should drive its recovered clock out of the device, and which reference clock buffer location to use - - - - LOCATE_RESET_CONTROLLER - Include reset controller in the - Indicate whether the transceiver reset controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - LOCATE_TX_BUFFER_BYPASS_CONTROLLER - Include transmitter buffer bypass controller in the - If the transmitter buffer is bypassed, indicate whether the transmitter buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_RX_BUFFER_BYPASS_CONTROLLER - Include receiver elastic buffer bypass controller in the - If the receiver elastic buffer is bypassed, indicate whether the receiver elastic buffer bypass controller is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - - false - - - - - - LOCATE_IN_SYSTEM_IBERT_CORE - Include In-System IBERT core - Indicate whether or not the In-System IBERT core should be instantiated in the example design. - EXAMPLE_DESIGN - - - LOCATE_TX_USER_CLOCKING - Include simple transmitter user clocking network in the - Indicate whether the simple, inferred transmitter user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_RX_USER_CLOCKING - Include simple receiver user clocking network in the - Indicate whether the simple, inferred receiver user clocking network is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion allows greater control of the network. - EXAMPLE_DESIGN - - - LOCATE_USER_DATA_WIDTH_SIZING - Include user data width sizing in the - Indicate whether the user data width sizing helper block is instantiated within the core, or outside of the core in the example design. Inclusion may simplify transceiver usage, while exclusion may allow greater control. - CORE - - - ORGANIZE_PORTS_BY - In the example design, organize ports across multiple channels by - If multiple transceivers are used, the example design can organize core ports either by name (iterating through each channel per port) or by channel (iterating through each port per channel) - NAME - - - - false - - - - - - PRESET - Transceiver configuration preset - You may select a transceiver configuration preset to pre-populate Transceivers Wizard selections with those relevant to a particular protocol or electrical standard - None - - - INTERNAL_PRESET - Transceiver configuration preset - None - - - INTERNAL_PORT_USAGE_UPDATED - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLEMENT_UPDATED - 27 - - - - false - - - - - - INTERNAL_CHANNEL_SITES_UPDATED - 7 - - - - false - - - - - - INTERNAL_CHANNEL_COLUMN_LOC_MAX - 96 - - - - false - - - - - - INTERNAL_RX_COMMA_PRESET_UPDATE - 9 - - - - false - - - - - - INTERNAL_UPDATE_IP_SYMBOL_drpclk_in - true - - - - false - - - - - - SECONDARY_QPLL_ENABLE - Enable secondary QPLL - Enable and configure the QPLL which is not used in this core configuration - false - - - - false - - - - - - SECONDARY_QPLL_LINE_RATE - Line rate of second core (Gb/s) - Enter the line rate, in Gb/s, for the data direction(s) of the core instance which will be clocked by the secondary QPLL - 10.3125 - - - - false - - - - - - SECONDARY_QPLL_FRACN_NUMERATOR - Fractional part of QPLL feedback divider - For supported transceiver types and line rates, entering the requested reference clock frequency and clicking Calculate above sets this numerator which produces the desired 24-bit fractional part of the secondary QPLL feedback divider as displayed. Note that any subsequent changes to this value affect secondary reference clock options including current selection - 0 - - - - false - - - - - - SECONDARY_QPLL_REFCLK_FREQUENCY - Actual Reference clock frequency (MHz) - Select a reference clock frequency from among those supported for the secondary QPLL at the selected line rate - 257.8125 - - - - false - - - - - - TXPROGDIV_FREQ_ENABLE - Enable selectable TXOUTCLK frequency - Enable selection of the TXOUTCLK frequency when using the TX programmable divider, instead of allowing the Wizard to choose the TXOUTCLK frequency - false - - - - false - - - - - - TXPROGDIV_FREQ_SOURCE - Programmable divider clock source - Select which PLL source is used to generate the selectable TXOUTCLK frequency - CPLL - - - - false - - - - - - TXPROGDIV_FREQ_VAL - TXOUTCLK frequency (MHz) - Select the TXOUTCLK frequency to be generated by the TX programmable divider - 120 - - - - false - - - - - - SATA_TX_BURST_LEN - TX COM sequence burst length - Select the number of bursts that make up a SATA COM sequence - 15 - - - FREERUN_FREQUENCY - Free-running and DRP clock frequency (MHz) - Enter the frequency of the free-running clock used to bring up the core. For configurations which use the CPLL, this clock must also be used for the transceiver channel DRP interface - 100 - - - INCLUDE_CPLL_CAL - 2 - - - USER_GTPOWERGOOD_DELAY_EN - Select 1 to enable powergood delay circuit - 1 - - - DISABLE_LOC_XDC - Select to disable generation of LOC constraints in xdc - 0 - - - ENABLE_COMMON_USRCLK - 0 - - - USB_ENABLE - false - - - PCIE_64BIT - false - - - PCIE_GEN4_EIOS - false - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_TX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_SRCCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_USRCLK2_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERCLK_RX_ACTIVE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_TX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_START_USER_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_DONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_BUFFBYPASS_RX_ERROR_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_CLK_FREERUN_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_ALL_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_PLL_AND_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DATAPATH_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1LOCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_CDR_STABLE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_TX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_RX_DONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL0RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_RESET_QPLL1RESET_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE3_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTHE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_TXOUTCLK_PERIOD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_CNT_TOL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_GTYE4_CPLL_CAL_BUFG_CE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_TX_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTWIZ_USERDATA_RX_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGBYPASSB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGMONITORENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGPDB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BGRCALOVRDENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPADDR_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPCLK_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDI_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPEN_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPWE_COMMON_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTGREFCLK1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTNORTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK00_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK01_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK10_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_GTSOUTHREFCLK11_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PCIERATEQPLL1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD0_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1CLKRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBDIV_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKDETCLK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCKEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1PD_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKSEL_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD2_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD3_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLRSVD4_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RCALENB_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1DATA_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1RESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TOGGLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1WIDTH_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONPOWERUP_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRESET_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONRSVDIN1_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBCFGSTREAMEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDO_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBDRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBENABLE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBGPI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBINTR_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBIOLMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMBRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMCAPTURE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMDBGUPDATE_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMREGEN_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSHIFT_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMSYSRST_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTCK_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_UBMDMTDI_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPDO_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_DRPRDY_COMMON_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_PMARSVDOUT1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL0REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1FBCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1LOCK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1OUTREFCLK_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLL1REFCLKLOST_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_QPLLDMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR0_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_REFCLKOUTMONITOR1_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1_SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK0SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXRECCLK1SEL_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM0TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1FINALOUT_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_SDM1TESTDATA_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TCONGPO_OUT - -1 - - - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSWING_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCALLIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCIN_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCMODE_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYSCLKSEL_IN - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSERRDY_IN - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXUSRCLK2_IN - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTCEMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTDIV_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRESET_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_BUFGTRSTMASK_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLFBCLKLOST_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_CPLLLOCK_OUT - 0 - - - - false - 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0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPOUTCLKRDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSLIPPMARDY_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTARTOFSEQ_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXSYNCOUT_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_RXVALID_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXBUFSTATUS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXCOMFINISH_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDCCDONE_OUT - -1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXDLYSRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLK_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKFABRIC_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXOUTCLKPCS_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHALIGNDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPHINITDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPMARESETDONE_OUT - 1 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXPRGDIVRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENN_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXQPISENP_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRATEDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXRESETDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCDONE_OUT - 0 - - - - false - - - - - - INTERNAL_PORT_ENABLED_TXSYNCOUT_OUT - 0 - - - - false - - - - - - Component_Name - gth_xcku_2gbps4_120mhz - - - - - UltraScale FPGAs Transceivers Wizard - 8 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2020.1 - - - - - - - diff --git a/xilinx/xcku/.gitignore b/xilinx/xcku/.gitignore new file mode 100644 index 0000000..de8b137 --- /dev/null +++ b/xilinx/xcku/.gitignore @@ -0,0 +1 @@ +/*/build/ diff --git a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci index ed2915a..5a5546a 100644 --- a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci +++ b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci @@ -13,11 +13,13 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 1 @@ -68,10 +70,12 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 0 @@ -123,6 +127,7 @@ 100000000 + 0 0 0.000 0 @@ -511,7 +516,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml deleted file mode 100644 index 9cfac03..0000000 --- a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml +++ /dev/null @@ -1,10743 +0,0 @@ - - - xilinx.com - customized_ip - fifo_18x16_dualport_oreg_xcku - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - 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1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_list_fa1519db - 18 - 9 - 18 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_26bda4ef - Asynchronous_Reset - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_18x16_dualport_oreg_xcku - - - - true - - - - - - Fifo_Implementation - Independent_Clocks_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 18 - - - - true - - - - - - Input_Depth - 16 - - - - true - - - - - - Output_Data_Width - 18 - - - - false - - - - - - Output_Depth - 16 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - true - - - - - - Reset_Type - Asynchronous_Reset - - - - false - - - - - - Full_Flags_Reset_Value - 0 - - - - true - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - false - - - - false - - - - - - Data_Count_Width - 4 - - - - false - - - - - - Write_Data_Count - false - - - - true - - - - - - Write_Data_Count_Width - 4 - - - - false - - - - - - Read_Data_Count - false - - - - true - - - - - - Read_Data_Count_Width - 4 - - - - false - - - - - - Disable_Timing_Violations - false - - - - true - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Constant - - - - true - - - - - - Full_Threshold_Assert_Value - 7 - - - - true - - - - - - Full_Threshold_Negate_Value - 6 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - true - - - - true - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci b/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci index 32f8df1..d2420e1 100644 --- a/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci +++ b/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xci @@ -13,11 +13,13 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 1 @@ -68,10 +70,12 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 0 @@ -123,6 +127,7 @@ 100000000 + 0 0 0.000 0 @@ -511,7 +516,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xml b/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xml deleted file mode 100644 index 40ccc9e..0000000 --- a/xilinx/xcku/fifo_18x1k_xcku/fifo_18x1k_xcku.xml +++ /dev/null @@ -1,10740 +0,0 @@ - - - xilinx.com - customized_ip - fifo_18x1k_xcku - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - 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- - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 1020 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 1019 - - - C_PROG_FULL_TYPE - 1 - - - C_RD_DATA_COUNT_WIDTH - 10 - - - C_RD_DEPTH - 1024 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 10 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 0 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 10 - - - C_WR_DEPTH - 1024 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 10 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_1936dea0 - 18 - 9 - 18 - 36 - 72 - 144 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_18x1k_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 18 - - - - true - - - - - - Input_Depth - 1024 - - - - true - - - - - - Output_Data_Width - 18 - - - - false - - - - - - Output_Depth - 1024 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - false - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - false - - - - true - - - - - - Data_Count_Width - 10 - - - - false - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 10 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 10 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Constant - - - - true - - - - - - Full_Threshold_Assert_Value - 1020 - - - - true - - - - - - Full_Threshold_Negate_Value - 1019 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - false - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci b/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci index 65fdc29..d5d0198 100644 --- a/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci +++ b/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xci @@ -511,7 +511,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xml b/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xml deleted file mode 100644 index 950118f..0000000 --- a/xilinx/xcku/fifo_18x512_oreg_xcku/fifo_18x512_oreg_xcku.xml +++ /dev/null @@ -1,10745 +0,0 @@ - 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dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 1 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 9 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 18 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 18 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 0 - - - C_HAS_ALMOST_EMPTY - 0 - - - C_HAS_ALMOST_FULL - 0 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 1 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 0 - - - C_HAS_SRST - 1 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 0 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 0 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 2 - - - C_PRELOAD_REGS - 1 - - - C_PRIM_FIFO_TYPE - 512x36 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 510 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 509 - - - C_PROG_FULL_TYPE - 3 - - - C_RD_DATA_COUNT_WIDTH - 9 - - - C_RD_DEPTH - 512 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 9 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 1 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 9 - - - C_WR_DEPTH - 512 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 9 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_1936dea0 - 18 - 9 - 18 - 36 - 72 - 144 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_18x512_oreg_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 18 - - - - true - - - - - - Input_Depth - 512 - - - - true - - - - - - Output_Data_Width - 18 - - - - false - - - - - - Output_Depth - 512 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - true - - - - true - - - - - - Data_Count_Width - 9 - - - - true - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 9 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 9 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Input_Port - - - - true - - - - - - Full_Threshold_Assert_Value - 510 - - - - false - - - - - - Full_Threshold_Negate_Value - 509 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - 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false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci index 0e81e3e..928fe0c 100644 --- a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci +++ b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xci @@ -13,11 +13,13 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 1 @@ -68,10 +70,12 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 0 @@ -123,6 +127,7 @@ 100000000 + 0 0 0.000 0 @@ -511,7 +516,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml b/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml deleted file mode 100644 index 38d632d..0000000 --- a/xilinx/xcku/fifo_19x16_obuf_xcku/fifo_19x16_obuf_xcku.xml +++ /dev/null @@ -1,10744 +0,0 @@ - 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dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axis_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 1 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 4 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 19 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 19 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 0 - - - C_HAS_ALMOST_EMPTY - 0 - - - C_HAS_ALMOST_FULL - 0 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 1 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 0 - - - C_HAS_SRST - 1 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 0 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 0 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 1 - - - C_PRELOAD_REGS - 0 - - - C_PRIM_FIFO_TYPE - 512x36 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 14 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 13 - - - C_PROG_FULL_TYPE - 3 - - - C_RD_DATA_COUNT_WIDTH - 4 - - - C_RD_DEPTH - 16 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 4 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 0 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 4 - - - C_WR_DEPTH - 16 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 4 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_08ae7940 - 19 - 19 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_19x16_obuf_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 19 - - - - true - - - - - - Input_Depth - 16 - - - - true - - - - - - Output_Data_Width - 19 - - - - false - - - - - - Output_Depth - 16 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - false - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - true - - - - true - - - - - - Data_Count_Width - 4 - - - - true - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 4 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 4 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Input_Port - - - - true - - - - - - Full_Threshold_Assert_Value - 14 - - - - false - - - - - - Full_Threshold_Negate_Value - 13 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - 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false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - false - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci b/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci index 589c5db..487f34f 100644 --- a/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci +++ b/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xci @@ -13,11 +13,13 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 1 @@ -68,10 +70,12 @@ 100000000 + 0 0 0.000 100000000 + 0 0 0.000 0 @@ -123,6 +127,7 @@ 100000000 + 0 0 0.000 0 @@ -511,7 +516,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xml b/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xml deleted file mode 100644 index 776e665..0000000 --- a/xilinx/xcku/fifo_19x16_xcku/fifo_19x16_xcku.xml +++ /dev/null @@ -1,10744 +0,0 @@ - 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STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_ar_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_r_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axis_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 1 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 4 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 19 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 19 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 0 - - - C_HAS_ALMOST_EMPTY - 0 - - - C_HAS_ALMOST_FULL - 0 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 1 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 0 - - - C_HAS_SRST - 1 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 0 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 0 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 1 - - - C_PRELOAD_REGS - 0 - - - C_PRIM_FIFO_TYPE - 512x36 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 8 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 7 - - - C_PROG_FULL_TYPE - 1 - - - C_RD_DATA_COUNT_WIDTH - 4 - - - C_RD_DEPTH - 16 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 4 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 0 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 4 - - - C_WR_DEPTH - 16 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 4 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_08ae7940 - 19 - 19 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_19x16_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 19 - - - - true - - - - - - Input_Depth - 16 - - - - true - - - - - - Output_Data_Width - 19 - - - - false - - - - - - Output_Depth - 16 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - false - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - true - - - - true - - - - - - Data_Count_Width - 4 - - - - true - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 4 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 4 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Constant - - - - true - - - - - - Full_Threshold_Assert_Value - 8 - - - - true - - - - - - Full_Threshold_Negate_Value - 7 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - 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false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - false - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci b/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci index 9fef5f5..bcb1a52 100644 --- a/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci +++ b/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xci @@ -511,7 +511,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xml b/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xml deleted file mode 100644 index 22207d3..0000000 --- a/xilinx/xcku/fifo_36x512_oreg_xcku/fifo_36x512_oreg_xcku.xml +++ /dev/null @@ -1,10748 +0,0 @@ - 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dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_b_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_ar_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_r_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axis_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 1 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 9 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 36 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 36 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 0 - - - C_HAS_ALMOST_EMPTY - 0 - - - C_HAS_ALMOST_FULL - 0 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 1 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 0 - - - C_HAS_SRST - 1 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 0 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 0 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 2 - - - C_PRELOAD_REGS - 1 - - - C_PRIM_FIFO_TYPE - 512x36 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 510 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 509 - - - C_PROG_FULL_TYPE - 3 - - - C_RD_DATA_COUNT_WIDTH - 9 - - - C_RD_DEPTH - 512 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 9 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 1 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 9 - - - C_WR_DEPTH - 512 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 9 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_list_f3564c51 - 36 - 9 - 18 - 36 - 72 - 144 - 288 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_36x512_oreg_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 36 - - - - true - - - - - - Input_Depth - 512 - - - - true - - - - - - Output_Data_Width - 36 - - - - false - - - - - - Output_Depth - 512 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - true - - - - true - - - - - - Data_Count_Width - 9 - - - - true - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 9 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 9 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Input_Port - - - - true - - - - - - Full_Threshold_Assert_Value - 510 - - - - false - - - - - - Full_Threshold_Negate_Value - 509 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci b/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci index b272c86..f72f2b0 100644 --- a/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci +++ b/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xci @@ -511,7 +511,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xml b/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xml deleted file mode 100644 index 73c20ae..0000000 --- a/xilinx/xcku/fifo_36x8k_oreg_xcku/fifo_36x8k_oreg_xcku.xml +++ /dev/null @@ -1,10749 +0,0 @@ - - - xilinx.com - customized_ip - fifo_36x8k_oreg_xcku - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - BD_ATTRIBUTE.TYPE - INTERIOR - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - M_AXI - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - core_clk - - - - - - - CLK - - - clk - - - - - - FREQ_HZ - clock frequency - specify frequency of the clock connected to port clk - 100000000 - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - ASSOCIATED_BUSIF - - - - none - - - - - ASSOCIATED_RESET - - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - true - - - - - - master_aclk - - - - - - - CLK - - - m_aclk - - - - - - ASSOCIATED_BUSIF - M_AXIS:M_AXI - - - FREQ_HZ - m_aclk frequency - specify frequency of the clock connected to port m_aclk - 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- 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_aw_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_aw_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_aw_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_aw_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_aw_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_w_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_w_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_w_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_b_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_b_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_b_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_ar_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_full_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty_thresh - - in - - 3 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_wr_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_rd_data_count - - out - - 4 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_ar_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_ar_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axi_r_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axi_r_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axi_r_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - axis_injectsbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_injectdbiterr - - in - - - std_logic - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_full_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty_thresh - - in - - 9 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_wr_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_rd_data_count - - out - - 10 - 0 - - - - std_logic_vector - dummy_view - - - - 0 - - - - - - false - - - - - - axis_sbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_dbiterr - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_overflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_underflow - - out - - - std_logic - dummy_view - - - - 0x0 - - - - - - false - - - - - - axis_prog_full - - out - - - STD_LOGIC - dummy_view - - - - 0 - - - - - - false - - - - - - axis_prog_empty - - out - - - STD_LOGIC - dummy_view - - - - 1 - - - - - - false - - - - - - - - C_COMMON_CLOCK - 1 - - - C_SELECT_XPM - 0 - - - C_COUNT_TYPE - 0 - - - C_DATA_COUNT_WIDTH - 13 - - - C_DEFAULT_VALUE - BlankString - - - C_DIN_WIDTH - 36 - - - C_DOUT_RST_VAL - 0 - - - C_DOUT_WIDTH - 36 - - - C_ENABLE_RLOCS - 0 - - - C_FAMILY - kintexu - - - C_FULL_FLAGS_RST_VAL - 0 - - - C_HAS_ALMOST_EMPTY - 0 - - - C_HAS_ALMOST_FULL - 0 - - - C_HAS_BACKUP - 0 - - - C_HAS_DATA_COUNT - 1 - - - C_HAS_INT_CLK - 0 - - - C_HAS_MEMINIT_FILE - 0 - - - C_HAS_OVERFLOW - 0 - - - C_HAS_RD_DATA_COUNT - 0 - - - C_HAS_RD_RST - 0 - - - C_HAS_RST - 0 - - - C_HAS_SRST - 1 - - - C_HAS_UNDERFLOW - 0 - - - C_HAS_VALID - 0 - - - C_HAS_WR_ACK - 0 - - - C_HAS_WR_DATA_COUNT - 0 - - - C_HAS_WR_RST - 0 - - - C_IMPLEMENTATION_TYPE - 0 - - - C_INIT_WR_PNTR_VAL - 0 - - - C_MEMORY_TYPE - 1 - - - C_MIF_FILE_NAME - BlankString - - - C_OPTIMIZATION_MODE - 0 - - - C_OVERFLOW_LOW - 0 - - - C_PRELOAD_LATENCY - 2 - - - C_PRELOAD_REGS - 1 - - - C_PRIM_FIFO_TYPE - 1kx36 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL - 2 - - - C_PROG_EMPTY_THRESH_NEGATE_VAL - 3 - - - C_PROG_EMPTY_TYPE - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL - 8190 - - - C_PROG_FULL_THRESH_NEGATE_VAL - 8189 - - - C_PROG_FULL_TYPE - 3 - - - C_RD_DATA_COUNT_WIDTH - 13 - - - C_RD_DEPTH - 8192 - - - C_RD_FREQ - 1 - - - C_RD_PNTR_WIDTH - 13 - - - C_UNDERFLOW_LOW - 0 - - - C_USE_DOUT_RST - 1 - - - C_USE_ECC - 0 - - - C_USE_EMBEDDED_REG - 1 - - - C_USE_PIPELINE_REG - 0 - - - C_POWER_SAVING_MODE - 0 - - - C_USE_FIFO16_FLAGS - 0 - - - C_USE_FWFT_DATA_COUNT - 0 - - - C_VALID_LOW - 0 - - - C_WR_ACK_LOW - 0 - - - C_WR_DATA_COUNT_WIDTH - 13 - - - C_WR_DEPTH - 8192 - - - C_WR_FREQ - 1 - - - C_WR_PNTR_WIDTH - 13 - - - C_WR_RESPONSE_LATENCY - 1 - - - C_MSGON_VAL - 1 - - - C_ENABLE_RST_SYNC - 1 - - - C_EN_SAFETY_CKT - 0 - - - C_ERROR_INJECTION_TYPE - 0 - - - C_SYNCHRONIZER_STAGE - 2 - - - C_INTERFACE_TYPE - 0 - - - C_AXI_TYPE - 1 - - - C_HAS_AXI_WR_CHANNEL - 1 - - - C_HAS_AXI_RD_CHANNEL - 1 - - - C_HAS_SLAVE_CE - 0 - - - C_HAS_MASTER_CE - 0 - - - C_ADD_NGC_CONSTRAINT - 0 - - - C_USE_COMMON_OVERFLOW - 0 - - - C_USE_COMMON_UNDERFLOW - 0 - - - C_USE_DEFAULT_SETTINGS - 0 - - - C_AXI_ID_WIDTH - 1 - - - C_AXI_ADDR_WIDTH - 32 - - - C_AXI_DATA_WIDTH - 64 - - - C_AXI_LEN_WIDTH - 8 - - - C_AXI_LOCK_WIDTH - 1 - - - C_HAS_AXI_ID - 0 - - - C_HAS_AXI_AWUSER - 0 - - - C_HAS_AXI_WUSER - 0 - - - C_HAS_AXI_BUSER - 0 - - - C_HAS_AXI_ARUSER - 0 - - - C_HAS_AXI_RUSER - 0 - - - C_AXI_ARUSER_WIDTH - 1 - - - C_AXI_AWUSER_WIDTH - 1 - - - C_AXI_WUSER_WIDTH - 1 - - - C_AXI_BUSER_WIDTH - 1 - - - C_AXI_RUSER_WIDTH - 1 - - - C_HAS_AXIS_TDATA - 1 - - - C_HAS_AXIS_TID - 0 - - - C_HAS_AXIS_TDEST - 0 - - - C_HAS_AXIS_TUSER - 1 - - - C_HAS_AXIS_TREADY - 1 - - - C_HAS_AXIS_TLAST - 0 - - - C_HAS_AXIS_TSTRB - 0 - - - C_HAS_AXIS_TKEEP - 0 - - - C_AXIS_TDATA_WIDTH - 8 - - - C_AXIS_TID_WIDTH - 1 - - - C_AXIS_TDEST_WIDTH - 1 - - - C_AXIS_TUSER_WIDTH - 4 - - - C_AXIS_TSTRB_WIDTH - 1 - - - C_AXIS_TKEEP_WIDTH - 1 - - - C_WACH_TYPE - 0 - - - C_WDCH_TYPE - 0 - - - C_WRCH_TYPE - 0 - - - C_RACH_TYPE - 0 - - - C_RDCH_TYPE - 0 - - - C_AXIS_TYPE - 0 - - - C_IMPLEMENTATION_TYPE_WACH - 1 - - - C_IMPLEMENTATION_TYPE_WDCH - 1 - - - C_IMPLEMENTATION_TYPE_WRCH - 1 - - - C_IMPLEMENTATION_TYPE_RACH - 1 - - - C_IMPLEMENTATION_TYPE_RDCH - 1 - - - C_IMPLEMENTATION_TYPE_AXIS - 1 - - - C_APPLICATION_TYPE_WACH - 0 - - - C_APPLICATION_TYPE_WDCH - 0 - - - C_APPLICATION_TYPE_WRCH - 0 - - - C_APPLICATION_TYPE_RACH - 0 - - - C_APPLICATION_TYPE_RDCH - 0 - - - C_APPLICATION_TYPE_AXIS - 0 - - - C_PRIM_FIFO_TYPE_WACH - 512x36 - - - C_PRIM_FIFO_TYPE_WDCH - 512x72 - - - C_PRIM_FIFO_TYPE_WRCH - 512x36 - - - C_PRIM_FIFO_TYPE_RACH - 512x36 - - - C_PRIM_FIFO_TYPE_RDCH - 512x72 - - - C_PRIM_FIFO_TYPE_AXIS - 1kx18 - - - C_USE_ECC_WACH - 0 - - - C_USE_ECC_WDCH - 0 - - - C_USE_ECC_WRCH - 0 - - - C_USE_ECC_RACH - 0 - - - C_USE_ECC_RDCH - 0 - - - C_USE_ECC_AXIS - 0 - - - C_ERROR_INJECTION_TYPE_WACH - 0 - - - C_ERROR_INJECTION_TYPE_WDCH - 0 - - - C_ERROR_INJECTION_TYPE_WRCH - 0 - - - C_ERROR_INJECTION_TYPE_RACH - 0 - - - C_ERROR_INJECTION_TYPE_RDCH - 0 - - - C_ERROR_INJECTION_TYPE_AXIS - 0 - - - C_DIN_WIDTH_WACH - 1 - - - C_DIN_WIDTH_WDCH - 64 - - - C_DIN_WIDTH_WRCH - 2 - - - C_DIN_WIDTH_RACH - 32 - - - C_DIN_WIDTH_RDCH - 64 - - - C_DIN_WIDTH_AXIS - 1 - - - C_WR_DEPTH_WACH - 16 - - - C_WR_DEPTH_WDCH - 1024 - - - C_WR_DEPTH_WRCH - 16 - - - C_WR_DEPTH_RACH - 16 - - - C_WR_DEPTH_RDCH - 1024 - - - C_WR_DEPTH_AXIS - 1024 - - - C_WR_PNTR_WIDTH_WACH - 4 - - - C_WR_PNTR_WIDTH_WDCH - 10 - - - C_WR_PNTR_WIDTH_WRCH - 4 - - - C_WR_PNTR_WIDTH_RACH - 4 - - - C_WR_PNTR_WIDTH_RDCH - 10 - - - C_WR_PNTR_WIDTH_AXIS - 10 - - - C_HAS_DATA_COUNTS_WACH - 0 - - - C_HAS_DATA_COUNTS_WDCH - 0 - - - C_HAS_DATA_COUNTS_WRCH - 0 - - - C_HAS_DATA_COUNTS_RACH - 0 - - - C_HAS_DATA_COUNTS_RDCH - 0 - - - C_HAS_DATA_COUNTS_AXIS - 0 - - - C_HAS_PROG_FLAGS_WACH - 0 - - - C_HAS_PROG_FLAGS_WDCH - 0 - - - C_HAS_PROG_FLAGS_WRCH - 0 - - - C_HAS_PROG_FLAGS_RACH - 0 - - - C_HAS_PROG_FLAGS_RDCH - 0 - - - C_HAS_PROG_FLAGS_AXIS - 0 - - - C_PROG_FULL_TYPE_WACH - 0 - - - C_PROG_FULL_TYPE_WDCH - 0 - - - C_PROG_FULL_TYPE_WRCH - 0 - - - C_PROG_FULL_TYPE_RACH - 0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_list_f3564c51 - 36 - 9 - 18 - 36 - 72 - 144 - 288 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_36x8k_oreg_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 36 - - - - true - - - - - - Input_Depth - 8192 - - - - true - - - - - - Output_Data_Width - 36 - - - - false - - - - - - Output_Depth - 8192 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - true - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - true - - - - true - - - - - - Data_Count_Width - 13 - - - - true - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 13 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 13 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Input_Port - - - - true - - - - - - Full_Threshold_Assert_Value - 8190 - - - - false - - - - - - Full_Threshold_Negate_Value - 8189 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - true - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - diff --git a/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci b/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci index e49f937..457eeca 100644 --- a/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci +++ b/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xci @@ -511,7 +511,7 @@ IP_Flow 5 TRUE - . + build . 2020.1 diff --git a/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xml b/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xml deleted file mode 100644 index c05364e..0000000 --- a/xilinx/xcku/fifo_sbuf_xcku/fifo_sbuf_xcku.xml +++ /dev/null @@ -1,10746 +0,0 @@ - - - xilinx.com - customized_ip - fifo_sbuf_xcku - 1.0 - - - M_AXIS - - - - - - - TDATA - - - m_axis_tdata - - - - - TDEST - - - m_axis_tdest - - - - - TID - - - m_axis_tid - - - - - TKEEP - - - m_axis_tkeep - - - - - TLAST - - - m_axis_tlast - - - - - TREADY - - - m_axis_tready - - - - - TSTRB - - - m_axis_tstrb - - - - - TUSER - - - m_axis_tuser - - - - - TVALID - - - m_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXIS - - - - - - - TDATA - - - s_axis_tdata - - - - - TDEST - - - s_axis_tdest - - - - - TID - - - s_axis_tid - - - - - TKEEP - - - s_axis_tkeep - - - - - TLAST - - - s_axis_tlast - - - - - TREADY - - - s_axis_tready - - - - - TSTRB - - - s_axis_tstrb - - - - - TUSER - - - s_axis_tuser - - - - - TVALID - - - s_axis_tvalid - - - - - - TDATA_NUM_BYTES - 0 - - - none - - - - - TDEST_WIDTH - 0 - - - none - - - - - TID_WIDTH - 0 - - - none - - - - - TUSER_WIDTH - 0 - - - none - - - - - HAS_TREADY - 0 - - - none - - - - - HAS_TSTRB - 0 - - - none - - - - - HAS_TKEEP - 0 - - - none - - - - - HAS_TLAST - 0 - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - LAYERED_METADATA - undef - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - S_AXI - - - - - - - - - ARADDR - - - s_axi_araddr - - - - - ARBURST - - - s_axi_arburst - - - - - ARCACHE - - - s_axi_arcache - - - - - ARID - - - s_axi_arid - - - - - ARLEN - - - s_axi_arlen - - - - - ARLOCK - - - s_axi_arlock - - - - - ARPROT - - - s_axi_arprot - - - - - ARQOS - - - s_axi_arqos - - - - - ARREADY - - - s_axi_arready - - - - - ARREGION - - - s_axi_arregion - - - - - ARSIZE - - - s_axi_arsize - - - - - ARUSER - - - s_axi_aruser - - - - - ARVALID - - - s_axi_arvalid - - - - - AWADDR - - - s_axi_awaddr - - - - - AWBURST - - - s_axi_awburst - - - - - AWCACHE - - - s_axi_awcache - - - - - AWID - - - s_axi_awid - - - - - AWLEN - - - s_axi_awlen - - - - - AWLOCK - - - s_axi_awlock - - - - - AWPROT - - - s_axi_awprot - - - - - AWQOS - - - s_axi_awqos - - - - - AWREADY - - - s_axi_awready - - - - - AWREGION - - - s_axi_awregion - - - - - AWSIZE - - - s_axi_awsize - - - - - AWUSER - - - s_axi_awuser - - - - - AWVALID - - - s_axi_awvalid - - - - - BID - - - s_axi_bid - - - - - BREADY - - - s_axi_bready - - - - - BRESP - - - s_axi_bresp - - - - - BUSER - - - s_axi_buser - - - - - BVALID - - - s_axi_bvalid - - - - - RDATA - - - s_axi_rdata - - - - - RID - - - s_axi_rid - - - - - RLAST - - - s_axi_rlast - - - - - RREADY - - - s_axi_rready - - - - - RRESP - - - s_axi_rresp - - - - - RUSER - - - s_axi_ruser - - - - - RVALID - - - s_axi_rvalid - - - - - WDATA - - - s_axi_wdata - - - - - WID - - - s_axi_wid - - - - - WLAST - - - s_axi_wlast - - - - - WREADY - - - s_axi_wready - - - - - WSTRB - - - s_axi_wstrb - - - - - WUSER - - - s_axi_wuser - - - - - WVALID - - - s_axi_wvalid - - - - - - BD_ATTRIBUTE.TYPE - INTERIOR - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 1 - - - none - - - - - MAX_BURST_LENGTH - 1 - - - none - - - - - PHASE - 0.000 - - - none - - - - - CLK_DOMAIN - - - - none - - - - - NUM_READ_THREADS - 1 - - - none - - - - - NUM_WRITE_THREADS - 1 - - - none - - - - - RUSER_BITS_PER_BYTE - 0 - - - none - - - - - WUSER_BITS_PER_BYTE - 0 - - - none - - - - - INSERT_VIP - 0 - - - simulation.rtl - - - - - - - - false - - - - - - M_AXI - - - - - - - ARADDR - - - m_axi_araddr - - - - - ARBURST - - - m_axi_arburst - - - - - ARCACHE - - - m_axi_arcache - - - - - ARID - - - m_axi_arid - - - - - ARLEN - - - m_axi_arlen - - - - - ARLOCK - - - m_axi_arlock - - - - - ARPROT - - - m_axi_arprot - - - - - ARQOS - - - m_axi_arqos - - - - - ARREADY - - - m_axi_arready - - - - - ARREGION - - - m_axi_arregion - - - - - ARSIZE - - - m_axi_arsize - - - - - ARUSER - - - m_axi_aruser - - - - - ARVALID - - - m_axi_arvalid - - - - - AWADDR - - - m_axi_awaddr - - - - - AWBURST - - - m_axi_awburst - - - - - AWCACHE - - - m_axi_awcache - - - - - AWID - - - m_axi_awid - - - - - AWLEN - - - m_axi_awlen - - - - - AWLOCK - - - m_axi_awlock - - - - - AWPROT - - - m_axi_awprot - - - - - AWQOS - - - m_axi_awqos - - - - - AWREADY - - - m_axi_awready - - - - - AWREGION - - - m_axi_awregion - - - - - AWSIZE - - - m_axi_awsize - - - - - AWUSER - - - m_axi_awuser - - - - - AWVALID - - - m_axi_awvalid - - - - - BID - - - m_axi_bid - - - - - BREADY - - - m_axi_bready - - - - - BRESP - - - m_axi_bresp - - - - - BUSER - - - m_axi_buser - - - - - BVALID - - - m_axi_bvalid - - - - - RDATA - - - m_axi_rdata - - - - - RID - - - m_axi_rid - - - - - RLAST - - - m_axi_rlast - - - - - RREADY - - - m_axi_rready - - - - - RRESP - - - m_axi_rresp - - - - - RUSER - - - m_axi_ruser - - - - - RVALID - - - m_axi_rvalid - - - - - WDATA - - - m_axi_wdata - - - - - WID - - - m_axi_wid - - - - - WLAST - - - m_axi_wlast - - - - - WREADY - - - m_axi_wready - - - - - WSTRB - - - m_axi_wstrb - - - - - WUSER - - - m_axi_wuser - - - - - WVALID - - - m_axi_wvalid - - - - - - DATA_WIDTH - 1 - - - none - - - - - PROTOCOL - AXI4LITE - - - none - - - - - FREQ_HZ - 100000000 - - - none - - - - - ID_WIDTH - 0 - - - none - - - - - ADDR_WIDTH - 1 - - - none - - - - - AWUSER_WIDTH - 0 - - - none - - - - - ARUSER_WIDTH - 0 - - - none - - - - - WUSER_WIDTH - 0 - - - none - - - - - RUSER_WIDTH - 0 - - - none - - - - - BUSER_WIDTH - 0 - - - none - - - - - READ_WRITE_MODE - READ_WRITE - - - none - - - - - HAS_BURST - 0 - - - none - - - - - HAS_LOCK - 0 - - - none - - - - - HAS_PROT - 0 - - - none - - - - - HAS_CACHE - 0 - - - none - - - - - HAS_QOS - 0 - - - none - - - - - HAS_REGION - 0 - - - none - - - - - HAS_WSTRB - 0 - - - none - - - - - HAS_BRESP - 0 - - - none - - - - - HAS_RRESP - 0 - - - none - - - - - SUPPORTS_NARROW_BURST - 0 - - - none - - - - - NUM_READ_OUTSTANDING - 1 - - - none - - - - - NUM_WRITE_OUTSTANDING - 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0 - - - C_PROG_FULL_TYPE_RDCH - 0 - - - C_PROG_FULL_TYPE_AXIS - 0 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_WRCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RACH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_RDCH - 1023 - - - C_PROG_FULL_THRESH_ASSERT_VAL_AXIS - 1023 - - - C_PROG_EMPTY_TYPE_WACH - 0 - - - C_PROG_EMPTY_TYPE_WDCH - 0 - - - C_PROG_EMPTY_TYPE_WRCH - 0 - - - C_PROG_EMPTY_TYPE_RACH - 0 - - - C_PROG_EMPTY_TYPE_RDCH - 0 - - - C_PROG_EMPTY_TYPE_AXIS - 0 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH - 1022 - - - C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS - 1022 - - - C_REG_SLICE_MODE_WACH - 0 - - - C_REG_SLICE_MODE_WDCH - 0 - - - C_REG_SLICE_MODE_WRCH - 0 - - - C_REG_SLICE_MODE_RACH - 0 - - - C_REG_SLICE_MODE_RDCH - 0 - - - C_REG_SLICE_MODE_AXIS - 0 - - - - - - choice_list_087d29fa - 0 - 1 - 2 - 4 - 8 - 16 - 32 - 64 - 128 - 256 - 512 - - - choice_list_08ae7940 - 19 - 19 - - - choice_list_165ed04b - 64 - - - choice_list_6727dfa6 - 1 - 0 - - - choice_list_8af5a703 - 0 - 1 - - - choice_list_bf1143fa - 16 - 32 - 64 - 128 - 256 - 512 - 1024 - 2048 - 4096 - 8192 - 16384 - 32768 - 65536 - 131072 - - - choice_pairs_0721dec1 - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Multiple_Programmable_Empty_Threshold_Constants - Single_Programmable_Empty_Threshold_Input_Port - Multiple_Programmable_Empty_Threshold_Input_Ports - - - choice_pairs_08e28d5f - Active_High - Active_Low - - - choice_pairs_0d7cd34d - Common_Clock_Builtin_FIFO - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - Common_Clock_Shift_Register - Independent_Clocks_Builtin_FIFO - Independent_Clocks_Block_RAM - Independent_Clocks_Distributed_RAM - - - choice_pairs_3c123ec0 - Common_Clock_Block_RAM - Common_Clock_Distributed_RAM - - - choice_pairs_53eba4dc - Native - AXI_MEMORY_MAPPED - AXI_STREAM - - - choice_pairs_541ed8d9 - Embedded_Reg - Fabric_Reg - Both - - - choice_pairs_5548b404 - Common_Clock - Independent_Clock - - - choice_pairs_5f1451ad - Standard_FIFO - First_Word_Fall_Through - - - choice_pairs_619f3529 - AXI4 - AXI3 - AXI4_Lite - - - choice_pairs_8334cf20 - Data_FIFO - Packet_FIFO - Low_Latency_Data_FIFO - - - choice_pairs_88535724 - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Multiple_Programmable_Full_Threshold_Constants - Single_Programmable_Full_Threshold_Input_Port - Multiple_Programmable_Full_Threshold_Input_Ports - - - choice_pairs_9b232fe1 - Slave_Interface_Clock_Enable - Master_Interface_Clock_Enable - - - choice_pairs_a8c5818a - Fully_Registered - Light_Weight - - - choice_pairs_ae1178b5 - Asynchronous_Reset - Synchronous_Reset - - - choice_pairs_b3e9d19b - FIFO - Register_Slice - Pass_Through_Wire - - - choice_pairs_bec132cf - FIFO - Register_Slice - - - choice_pairs_c94a1851 - Hard_ECC - Soft_ECC - - - choice_pairs_ccb14e2b - READ_WRITE - READ_ONLY - WRITE_ONLY - - - choice_pairs_eb98f74b - No_Programmable_Empty_Threshold - Single_Programmable_Empty_Threshold_Constant - Single_Programmable_Empty_Threshold_Input_Port - - - choice_pairs_ec2b452f - No_Programmable_Full_Threshold - Single_Programmable_Full_Threshold_Constant - Single_Programmable_Full_Threshold_Input_Port - - - The FIFO Generator is a parameterizable first-in/first-out memory queue generator. Use it to generate resource and performance optimized FIFOs with common or independent read/write clock domains, and optional fixed or programmable full and empty flags and handshaking signals. Choose from a selection of memory resource types for implementation. Optional Hamming code based error detection and correction as well as error injection capability for system test help to insure data integrity. FIFO width and depth are parameterizable, and for native interface FIFOs, asymmetric read and write port widths are also supported. - - - Component_Name - fifo_sbuf_xcku - - - - true - - - - - - Fifo_Implementation - Common_Clock_Block_RAM - - - - true - - - - - - synchronization_stages - 2 - - - - true - - - - - - synchronization_stages_axi - 2 - - - - true - - - - - - INTERFACE_TYPE - Native - - - - true - - - - - - Performance_Options - Standard_FIFO - - - - true - - - - - - asymmetric_port_width - false - - - - true - - - - - - Input_Data_Width - 19 - - - - true - - - - - - Input_Depth - 16 - - - - true - - - - - - Output_Data_Width - 19 - - - - false - - - - - - Output_Depth - 16 - - - - false - - - - - - Enable_ECC - false - - - - true - - - - - - Use_Embedded_Registers - false - - - - true - - - - - - Reset_Pin - true - - - - true - - - - - - Enable_Reset_Synchronization - true - - - - false - - - - - - Reset_Type - Synchronous_Reset - - - - true - - - - - - Full_Flags_Reset_Value - 0 - - - - false - - - - - - Use_Dout_Reset - true - - - - true - - - - - - Dout_Reset_Value - 0 - - - - true - - - - - - dynamic_power_saving - false - - - - false - - - - - - Almost_Full_Flag - false - - - - true - - - - - - Almost_Empty_Flag - false - - - - true - - - - - - Valid_Flag - false - - - - true - - - - - - Valid_Sense - Active_High - - - - false - - - - - - Underflow_Flag - false - - - - true - - - - - - Underflow_Sense - Active_High - - - - false - - - - - - Write_Acknowledge_Flag - false - - - - true - - - - - - Write_Acknowledge_Sense - Active_High - - - - false - - - - - - Overflow_Flag - false - - - - true - - - - - - Overflow_Sense - Active_High - - - - false - - - - - - Inject_Sbit_Error - false - - - - false - - - - - - Inject_Dbit_Error - false - - - - false - - - - - - ecc_pipeline_reg - false - - - - false - - - - - - Use_Extra_Logic - false - - - - false - - - - - - Data_Count - false - - - - true - - - - - - Data_Count_Width - 4 - - - - false - - - - - - Write_Data_Count - false - - - - false - - - - - - Write_Data_Count_Width - 4 - - - - false - - - - - - Read_Data_Count - false - - - - false - - - - - - Read_Data_Count_Width - 4 - - - - false - - - - - - Disable_Timing_Violations - false - - - - false - - - - - - Read_Clock_Frequency - 1 - - - - false - - - - - - Write_Clock_Frequency - 1 - - - - false - - - - - - Programmable_Full_Type - Single_Programmable_Full_Threshold_Constant - - - - true - - - - - - Full_Threshold_Assert_Value - 5 - - - - true - - - - - - Full_Threshold_Negate_Value - 4 - - - - false - - - - - - Programmable_Empty_Type - No_Programmable_Empty_Threshold - - - - true - - - - - - Empty_Threshold_Assert_Value - 2 - - - - false - - - - - - Empty_Threshold_Negate_Value - 3 - - - - false - - - - - - PROTOCOL - AXI4 - - - - false - - - - - - Clock_Type_AXI - Common_Clock - - - - true - - - - - - HAS_ACLKEN - false - - - - false - - - - - - Clock_Enable_Type - Slave_Interface_Clock_Enable - - - - false - - - - - - READ_WRITE_MODE - READ_WRITE - - - - true - - - - - - ID_WIDTH - 0 - - - - false - - - - - - ADDRESS_WIDTH - 32 - - - - false - - - - - - DATA_WIDTH - 64 - - - - false - - - - - - AWUSER_Width - 0 - - - - false - - - - - - WUSER_Width - 0 - - - - false - - - - - - BUSER_Width - 0 - - - - false - - - - - - ARUSER_Width - 0 - - - - false - - - - - - RUSER_Width - 0 - - - - false - - - - - - TDATA_NUM_BYTES - 1 - - - - true - - - - - - TID_WIDTH - 0 - - - - false - - - - - - TDEST_WIDTH - 0 - - - - false - - - - - - TUSER_WIDTH - 4 - - - - false - - - - - - Enable_TREADY - true - - - - false - - - - - - Enable_TLAST - false - - - - true - - - - - - HAS_TSTRB - false - - - - false - - - - - - TSTRB_WIDTH - 1 - - - - false - - - - - - HAS_TKEEP - false - - - - false - - - - - - TKEEP_WIDTH - 1 - - - - false - - - - - - wach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wach - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wach - false - - - - false - - - - - - Inject_Sbit_Error_wach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wach - false - - - - false - - - - - - Input_Depth_wach - 16 - - - - true - - - - - - Enable_Data_Counts_wach - false - - - - false - - - - - - Programmable_Full_Type_wach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wdch - false - - - - false - - - - - - Inject_Sbit_Error_wdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wdch - false - - - - false - - - - - - Input_Depth_wdch - 1024 - - - - true - - - - - - Enable_Data_Counts_wdch - false - - - - false - - - - - - Programmable_Full_Type_wdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - wrch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_wrch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_wrch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_wrch - false - - - - false - - - - - - Inject_Sbit_Error_wrch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_wrch - false - - - - false - - - - - - Input_Depth_wrch - 16 - - - - true - - - - - - Enable_Data_Counts_wrch - false - - - - false - - - - - - Programmable_Full_Type_wrch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_wrch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_wrch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_wrch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rach_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rach - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rach - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rach - false - - - - false - - - - - - Inject_Sbit_Error_rach - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rach - false - - - - false - - - - - - Input_Depth_rach - 16 - - - - true - - - - - - Enable_Data_Counts_rach - false - - - - false - - - - - - Programmable_Full_Type_rach - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rach - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rach - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rach - Empty Threshold Assert Value - 1022 - - - - false - - - - - - rdch_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_rdch - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_rdch - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_rdch - false - - - - false - - - - - - Inject_Sbit_Error_rdch - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_rdch - false - - - - false - - - - - - Input_Depth_rdch - 1024 - - - - true - - - - - - Enable_Data_Counts_rdch - false - - - - false - - - - - - Programmable_Full_Type_rdch - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_rdch - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_rdch - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_rdch - Empty Threshold Assert Value - 1022 - - - - false - - - - - - axis_type - Configuration Options - FIFO - - - - true - - - - - - FIFO_Implementation_axis - FIFO Implementation Type - Common_Clock_Block_RAM - - - - true - - - - - - FIFO_Application_Type_axis - FIFO Application Type - Data_FIFO - - - - false - - - - - - Enable_ECC_axis - false - - - - false - - - - - - Inject_Sbit_Error_axis - Single Bit Error Injection - false - - - - false - - - - - - Inject_Dbit_Error_axis - Double Bit Error Injection - false - - - - false - - - - - - Input_Depth_axis - 1024 - - - - true - - - - - - Enable_Data_Counts_axis - false - - - - false - - - - - - Programmable_Full_Type_axis - Deassert READY When - No_Programmable_Full_Threshold - - - - false - - - - - - Full_Threshold_Assert_Value_axis - Full Threshold Assert Value - 1023 - - - - false - - - - - - Programmable_Empty_Type_axis - Deassert VALID When - No_Programmable_Empty_Threshold - - - - false - - - - - - Empty_Threshold_Assert_Value_axis - Empty Threshold Assert Value - 1022 - - - - false - - - - - - Register_Slice_Mode_wach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_wrch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rach - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_rdch - Register Slice Options - Fully_Registered - - - - true - - - - - - Register_Slice_Mode_axis - Register Slice Options - Fully_Registered - - - - true - - - - - - Underflow_Flag_AXI - Underflow Flag - false - - - - false - - - - - - Underflow_Sense_AXI - Underflow (Read Error) - Active_High - - - - false - - - - - - Overflow_Flag_AXI - Overflow Flag - false - - - - false - - - - - - Overflow_Sense_AXI - Overflow (Write Error) - Active_High - - - - false - - - - - - Disable_Timing_Violations_AXI - false - - - - true - - - - - - Add_NGC_Constraint_AXI - false - - - - true - - - - - - Enable_Common_Underflow - false - - - - true - - - - - - Enable_Common_Overflow - false - - - - true - - - - - - enable_read_pointer_increment_by2 - false - - - - true - - - - - - Use_Embedded_Registers_axis - false - - - - false - - - - - - enable_low_latency - false - - - - false - - - - - - use_dout_register - false - - - - false - - - - - - Master_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Slave_interface_Clock_enable_memory_mapped - false - - - - false - - - - - - Output_Register_Type - Embedded_Reg - - - - false - - - - - - Enable_Safety_Circuit - false - - - - false - - - - - - Enable_ECC_Type - Hard_ECC - - - - false - - - - - - C_SELECT_XPM - 0 - - - - - FIFO Generator - - XPM_MEMORY - XPM_CDC - - 5 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2019.2 - - - - - - - - -- 2.43.0