From 758ddb625725303adc3f7b447b0a8846ddad75df Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sat, 9 Jul 2022 00:56:48 +0200 Subject: [PATCH] 1:3 hub, reset still shaky --- gbe_hub/trb3sc_gbe_hub.prj | 2 + gbe_hub/trb3sc_gbe_hub.vhd | 307 ++++++++++++++++++++++--------------- 2 files changed, 188 insertions(+), 121 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index a3e21b3..6dde03e 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -234,6 +234,8 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/rx_rb.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/tx_fifo.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/forwarder.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_lsm.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/scatter_ports.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gather_ports.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index f61bb1a..a951fd7 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -154,20 +154,193 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal mac_rx_err : std_logic; -- the new FIFO interface - signal fifo_data_rx : std_logic_vector(4 * 8 - 1 downto 0); - signal fifo_data_tx : std_logic_vector(4 * 8 - 1 downto 0); - signal fifo_full_rx : std_logic_vector(3 downto 0); - signal fifo_full_tx : std_logic_vector(3 downto 0); - signal fifo_wr_rx : std_logic_vector(3 downto 0); - signal fifo_wr_tx : std_logic_vector(3 downto 0); - signal fifo_start_rx : std_logic_vector(3 downto 0); - signal fifo_start_tx : std_logic_vector(3 downto 0); - signal frame_req_rx : std_logic_vector(3 downto 0); - signal frame_ack_rx : std_logic_vector(3 downto 0); - signal frame_avail_rx : std_logic_vector(3 downto 0); + + -- 10: frame_start + -- 9 : fifo_wr + -- 8 : fifo_eof + -- 7..0: fifo_data + type dl_rx_data_t is array(1 to 3) of std_logic_vector(10 downto 0); + signal dl_rx_data : dl_rx_data_t; + signal dl_rx_frame_req : std_logic_vector(3 downto 1); + signal dl_rx_frame_ack : std_logic_vector(3 downto 1); + signal dl_rx_frame_avail : std_logic_vector(3 downto 1); + signal dl_tx_fifofull : std_logic_vector(3 downto 1); + + -- 10: frame_start + -- 9 : fifo_wr + -- 8 : fifo_eof + -- 7..0: data + signal ul_rx_data : std_logic_vector(10 downto 0); + signal ul_tx_data : std_logic_vector(10 downto 0); + signal ul_tx_fifofull : std_logic; + signal ul_rx_frame_avail : std_logic; + signal ul_rx_frame_req : std_logic; + signal ul_rx_frame_ack : std_logic; + signal ul_rx_fifofull : std_logic; + + signal port_sel : std_logic_vector(3 downto 1); begin +--------------------------------------------------------------------------- +-- PCSC is four ports downlink +--------------------------------------------------------------------------- + THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo + generic map( + LINKS_ACTIVE => "1111" + ) + port map( + RESET => reset_i, + GSR_N => GSR_N, + CLK_SYS => clk_sys, + CLK_125 => CLK_SUPPL_PCLK, + CLK_125_RX => open, + -- SerDes 0 -- UPLINK + -- FIFO interface RX + FIFO_FULL_IN(0) => ul_rx_fifofull, + FIFO_WR_OUT(0) => ul_rx_data(9), + FIFO_DATA_OUT(8 downto 0) => ul_rx_data(8 downto 0), + FRAME_START_OUT(0) => ul_rx_data(10), + FRAME_REQ_IN(0) => ul_rx_frame_req, + FRAME_ACK_OUT(0) => ul_rx_frame_ack, + FRAME_AVAIL_OUT(0) => ul_rx_frame_avail, + -- FIFO interface TX + FIFO_WR_IN(0) => ul_tx_data(9), + FIFO_DATA_IN(8 downto 0) => ul_tx_data(8 downto 0), + FRAME_START_IN(0) => ul_tx_data(10), + FIFO_FULL_OUT(0) => ul_tx_fifofull, + -- SerDes 1 - DOWNLINK + -- FIFO interface RX + FIFO_FULL_IN(1) => ul_tx_fifofull, + FIFO_WR_OUT(1) => dl_rx_data(1)(9), + FIFO_DATA_OUT(17 downto 9) => dl_rx_data(1)(8 downto 0), + FRAME_START_OUT(1) => dl_rx_data(1)(10), + FRAME_REQ_IN(1) => dl_rx_frame_req(1), + FRAME_ACK_OUT(1) => dl_rx_frame_ack(1), + FRAME_AVAIL_OUT(1) => dl_rx_frame_avail(1), + -- FIFO interface TX + FIFO_WR_IN(1) => ul_rx_data(9), + FIFO_DATA_IN(17 downto 9) => ul_rx_data(8 downto 0), + FRAME_START_IN(1) => ul_rx_data(10), + FIFO_FULL_OUT(1) => dl_tx_fifofull(1), + -- SerDes 2 -- DOWNLINK + -- FIFO interface RX + FIFO_FULL_IN(2) => ul_tx_fifofull, + FIFO_WR_OUT(2) => dl_rx_data(2)(9), + FIFO_DATA_OUT(26 downto 18) => dl_rx_data(2)(8 downto 0), + FRAME_START_OUT(2) => dl_rx_data(2)(10), + FRAME_REQ_IN(2) => dl_rx_frame_req(2), + FRAME_ACK_OUT(2) => dl_rx_frame_ack(2), + FRAME_AVAIL_OUT(2) => dl_rx_frame_avail(2), + -- FIFO interface TX + FIFO_WR_IN(2) => ul_rx_data(9), + FIFO_DATA_IN(26 downto 18) => ul_rx_data(8 downto 0), + FRAME_START_IN(2) => ul_rx_data(10), + FIFO_FULL_OUT(2) => dl_tx_fifofull(2), + -- SerDes 3 -- DOWNLINK + -- FIFO interface RX + FIFO_FULL_IN(3) => ul_tx_fifofull, + FIFO_WR_OUT(3) => dl_rx_data(3)(9), + FIFO_DATA_OUT(35 downto 27) => dl_rx_data(3)(8 downto 0), + FRAME_START_OUT(3) => dl_rx_data(3)(10), + FRAME_REQ_IN(3) => dl_rx_frame_req(3), + FRAME_ACK_OUT(3) => dl_rx_frame_ack(3), + FRAME_AVAIL_OUT(3) => dl_rx_frame_avail(3), + -- FIFO interface TX + FIFO_WR_IN(3) => ul_rx_data(9), + FIFO_DATA_IN(35 downto 27) => ul_rx_data(8 downto 0), + FRAME_START_IN(3) => ul_rx_data(10), + FIFO_FULL_OUT(3) => dl_tx_fifofull(3), + -- SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + -- SerDes control + TX_PLOL_LOL_OUT => tx_pll_lol_c_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + RX_LINK_READY_OUT => open, + TX_LINK_READY_IN => open, + -- Debug + STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), + DEBUG_OUT => open + ); + + -- scattering: data from uplink is distributed to downlinks + THE_SCATTER: entity scatter_ports + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + FIFO_FULL_IN(3 downto 1) => dl_tx_fifofull(3 downto 1), + FIFO_FULL_OUT => ul_rx_fifofull, + FRAME_AVAIL_IN => ul_rx_frame_avail, + FRAME_REQ_OUT => ul_rx_frame_req, + FRAME_ACK_IN => ul_rx_frame_ack, + CYCLE_DONE_OUT => open, + -- + DEBUG => open + ); + + THE_GATHER: entity gather_ports + port map( + CLK => CLK_SUPPL_PCLK, + CLEAR => clear, + RESET => reset_i, + -- + FRAME_AVAIL_IN(3 downto 1) => dl_rx_frame_avail, + FRAME_REQ_OUT(3 downto 1) => dl_rx_frame_req, + FRAME_ACK_IN(3 downto 1) => dl_rx_frame_ack, + PORT_SELECT_OUT(3 downto 1) => port_sel, + CYCLE_DONE_OUT => open, + -- + DEBUG => open + ); + + THE_QUICK_MUX: process( port_sel, dl_rx_data ) + begin + case port_sel is + when b"001" => ul_tx_data <= dl_rx_data(1); + when b"010" => ul_tx_data <= dl_rx_data(2); + when b"100" => ul_tx_data <= dl_rx_data(3); + when others => ul_tx_data <= (others => '0'); + end case; + end process THE_QUICK_MUX; + + DBG(0) <= ul_rx_frame_avail; + DBG(3 downto 1) <= dl_rx_frame_avail; + DBG(4) <= ul_rx_frame_req; + DBG(7 downto 5) <= dl_rx_frame_req; + DBG(8) <= ul_rx_frame_ack; + DBG(11 downto 9) <= dl_rx_frame_ack; + DBG(12) <= ul_tx_fifofull; + DBG(15 downto 13) <= dl_tx_fifofull; + DBG(16) <= ul_rx_fifofull; + DBG(19 downto 17) <= port_sel; + DBG(20) <= '0'; + DBG(21) <= '0'; + DBG(22) <= '0'; + DBG(23) <= '0'; + DBG(24) <= '0'; + DBG(25) <= '0'; + DBG(26) <= '0'; + DBG(27) <= '0'; + DBG(28) <= '0'; + DBG(29) <= '0'; + DBG(30) <= '0'; + DBG(31) <= '0'; + DBG(32) <= '0'; + DBG(33) <= CLK_SUPPL_PCLK; + --------------------------------------------------------------------------- -- Clock & Reset Handling --------------------------------------------------------------------------- @@ -414,8 +587,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler -- LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) LED_GREEN <= not status(2); --'0'; LED_ORANGE <= not status(5); --'0'; - LED_RED <= not fw_link_active_int; --'0'; - LED_YELLOW <= not bw_link_active_int; --'0'; + LED_RED <= not '0'; + LED_YELLOW <= not '0'; --GEN_HUB_LEDS : for i in 0 to 6 generate -- LED_HUB_LINKOK(i+1) <= not '0'; @@ -469,114 +642,6 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_RJ_GREEN(1) <= not '0'; LED_RJ_RED(1) <= not '0'; ---------------------------------------------------------------------------- --- PCSC is four ports downlink ---------------------------------------------------------------------------- - THE_GBE_MED_RAW_PCSC: entity gbe_med_fifo - generic map( - LINKS_ACTIVE => "1111" - ) - port map( - RESET => reset_i, - GSR_N => GSR_N, - CLK_SYS => clk_sys, - CLK_125 => CLK_SUPPL_PCLK, - CLK_125_RX => open, - -- FIFO interface RX - FIFO_DATA_OUT => fifo_data_rx, - FIFO_FULL_IN => fifo_full_rx, - FIFO_WR_OUT => fifo_wr_rx, - FRAME_REQ_IN => frame_req_rx, - FRAME_ACK_OUT => frame_ack_rx, - FRAME_AVAIL_OUT => frame_avail_rx, - FRAME_START_OUT => frame_start_rx, - -- FIFO interface TX - FIFO_FULL_OUT => fifo_full_tx, - FIFO_WR_IN => fifo_wr_tx, - FIFO_DATA_IN => fifo_data_tx, - FRAME_START_IN => frame_start_tx, - -- SFP Connection - SD_PRSNT_N_IN(0) => HUB_MOD0(3), - SD_PRSNT_N_IN(1) => HUB_MOD0(4), - SD_PRSNT_N_IN(2) => HUB_MOD0(1), - SD_PRSNT_N_IN(3) => HUB_MOD0(2), - SD_LOS_IN(0) => HUB_LOS(3), - SD_LOS_IN(1) => HUB_LOS(4), - SD_LOS_IN(2) => HUB_LOS(1), - SD_LOS_IN(3) => HUB_LOS(2), - SD_TXDIS_OUT(0) => HUB_TXDIS(3), - SD_TXDIS_OUT(1) => HUB_TXDIS(4), - SD_TXDIS_OUT(2) => HUB_TXDIS(1), - SD_TXDIS_OUT(3) => HUB_TXDIS(2), - -- SerDes control - TX_PLOL_LOL_OUT => tx_pll_lol_c_i, - TX_PCS_RST_IN => tx_pcs_rst_i, - RX_LINK_READY_OUT => open, - TX_LINK_READY_IN => open, - -- Debug - STATUS_OUT => status_raw(3 * 32 - 1 downto 2 * 32), - DEBUG_OUT => open - ); - - -- scattering: data from uplink is distributed to downlinks - THE_SCATTER: entity scatter_ports - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- - FRAME_AVAIL_IN(3 downto 0) => , - FRAME_AVAIL_IN(15 downto 4) => (others => '0'), - FRAME_REQ_OUT(3 downto 0) => , - FRAME_REQ_OUT(15 downto 4) => open, - FRAME_ACK_IN(3 downto 0) => , - FRAME_ACK_IN(15 downto 4) => (others => '0'), - CYCLE_DONE_OUT => open, - -- - DEBUG => open - ); - - THE_GATHER: entity gather_ports - port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, - RESET => reset_i, - -- - FRAME_AVAIL_IN(3 downto 0) => , - FRAME_AVAIL_IN(15 downto 4) => (others => '0'), - FRAME_REQ_OUT(3 downto 0) => , - FRAME_REQ_OUT(15 downto 4) => open, - FRAME_ACK_IN(3 downto 0) => , - FRAME_ACK_IN(15 downto 4) => (others => '0'), - PORT_SELECT_OUT(3 downto 0) => , - PORT_SELECT_OUT(15 downto 4) => open, - CYCLE_DONE_OUT => open, - -- - DEBUG => open - ); - - DBG(3 downto 0) <= (others => '0'); - DBG(7 downto 4) <= (others => '0'); - DBG(11 downto 8) <= '0'; - DBG(15 downto 12) <= '0'; - DBG(16) <= '0'; - DBG(17) <= '0'; - DBG(18) <= '0'; - DBG(19) <= '0'; - DBG(20) <= '0'; - DBG(21) <= '0'; - DBG(22) <= '0'; - DBG(23) <= '0'; - DBG(24) <= '0'; - DBG(25) <= '0'; - DBG(26) <= '0'; - DBG(27) <= '0'; - DBG(28) <= '0'; - DBG(29) <= '0'; - DBG(30) <= '0'; - DBG(31) <= '0'; - DBG(32) <= '0'; - DBG(33) <= '0'; --------------------------------------------------------------------------- -- PCSB is two ports downlink (6port hub addon) or four ports downlink (8port hub addon) -- 2.43.0