From 762948198768aee56a67300aab6100e1f7b311ec Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 2 Jul 2021 19:36:59 +0200 Subject: [PATCH] updated DBO project to latest files --- DBO/config.vhd | 6 +- DBO/config_compile_frankfurt.pl | 6 +- DBO/mdctdc.lpf | 438 ++++++++++++++++++++++---------- DBO/mdctdc.prj | 19 +- DBO/mdctdc.vhd | 24 +- pinout/dbo.lpf | 18 +- 6 files changed, 352 insertions(+), 159 deletions(-) diff --git a/DBO/config.vhd b/DBO/config.vhd index 7e82d70..3dc2c8e 100644 --- a/DBO/config.vhd +++ b/DBO/config.vhd @@ -16,7 +16,7 @@ package config is --TDC settings constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 - constant FPGA_SIZE : string := "25KUM"; + constant FPGA_SIZE : string := "45KUM"; constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons @@ -39,7 +39,7 @@ package config is --input monitor and trigger generation logic constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 - constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant INCLUDE_STATISTICS : integer := c_YES; --1300 slices, 1 RAM @32 constant TRIG_GEN_INPUT_NUM : integer := 32; constant TRIG_GEN_OUTPUT_NUM : integer := 4; constant MONITOR_INPUT_NUM : integer := 32; @@ -57,7 +57,7 @@ package config is ------------------------------------------------------------------------------ type intlist_t is array(0 to 7) of integer; type hw_info_t is array(0 to 7) of unsigned(31 downto 0); - constant HW_INFO_BASE : unsigned(31 downto 0) := x"A6100000"; + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A7000000"; --declare constants, filled in body diff --git a/DBO/config_compile_frankfurt.pl b/DBO/config_compile_frankfurt.pl index db689d3..5421fa6 100644 --- a/DBO/config_compile_frankfurt.pl +++ b/DBO/config_compile_frankfurt.pl @@ -1,13 +1,13 @@ Familyname => 'ECP5UM', -Devicename => 'LFE5UM-25F', +Devicename => 'LFE5UM-45F', Package => 'CABGA381', Speedgrade => '8', TOPNAME => "mdctdc", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; -lm_license_file_for_par => "1702\@jspc29", -lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +lm_license_file_for_par => "1710\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', nodelist_file => '../nodelist_frankfurt.txt', diff --git a/DBO/mdctdc.lpf b/DBO/mdctdc.lpf index 74c50ea..5d31768 100644 --- a/DBO/mdctdc.lpf +++ b/DBO/mdctdc.lpf @@ -13,143 +13,305 @@ FREQUENCY NET "med2int_0.clk_full" 200 MHz; MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; -REGION "MEDIA" "R81C44D" 13 25; +REGION "MEDIA" "R57C34D" 13 30; LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; -# -# # UGROUP "INPGATE0" BBOX 1 1 -# # BLKNAME THE_TDC/gen_channels.0.inpgate[0] -# # ; -# # LOCATE UGROUP "INPGATE0" SITE "R14C4D"; -# -# UGROUP "ffarr0groupA" BBOX 3 3 -# BLKNAME THE_TDC/ffarr_0_0 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] -# ; -# LOCATE UGROUP "ffarr0groupA" SITE "R13C2D"; -# UGROUP "ffarr0groupA1" BBOX 1 1 -# BLKNAME THE_TDC/ffarr_0_0 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] -# ; -# LOCATE UGROUP "ffarr0groupA1" SITE "R13C2D"; -# -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[8] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[9] -# -# -# -# UGROUP "ffarr0groupA2" BBOX 1 1 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] -# ; -# LOCATE UGROUP "ffarr0groupA2" SITE "R13C3D"; -# -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[10] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[11] -# -# -# UGROUP "ffarr0groupA3" BBOX 1 1 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] -# ; -# LOCATE UGROUP "ffarr0groupA3" SITE "R14C2D"; -# -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[12] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[13] -# -# -# UGROUP "ffarr0groupA4" BBOX 1 1 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] -# ; -# LOCATE UGROUP "ffarr0groupA4" SITE "R14C3D"; -# -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[14] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[15] - - -# UGROUP "ffarr0groupB" BBOX 3 2 -# BLKNAME THE_TDC/ffarr_1_0 -# BLKNAME THE_TDC/ffarr_2_0 -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[8] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[8] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[9] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[9] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[10] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[10] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[11] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[11] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[12] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[12] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[13] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[13] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[14] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[14] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[15] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[15] -# ; -# -# -# LOCATE UGROUP "ffarr0groupB" SITE "R14C5D"; - -# -# UGROUP "ffarr0groupAD" BBOX 2 2 -# BLKNAME THE_TDC/ffarr_0_0[0] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_0_0[7] -# ; -# -# UGROUP "ffarr0groupBD" BBOX 2 2 -# BLKNAME THE_TDC/ffarr_1_0[0] -# BLKNAME THE_TDC/ffarr_2_0[0] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[1] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[2] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[3] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[4] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[5] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[6] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_1_0[7] -# BLKNAME THE_TDC/gen_channels.0.gen_ffarr_first.0.ffarr_2_0[7] -# ; -# -# LOCATE UGROUP "ffarr0groupAD" SITE "R13C2D"; -# LOCATE UGROUP "ffarr0groupBD" SITE "R13C4D"; +UGROUP "TDC0" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC1" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC2" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC3" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC4" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC5" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC6" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC7" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC8" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC9" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC10" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC11" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC12" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC13" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC14" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC15" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC16" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC17" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC18" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC19" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC20" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC21" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC22" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC23" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC24" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC25" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC26" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC27" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC28" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC29" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC30" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC31" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC32" BBOX 1 2 + BLKNAME GND; + + + +LOCATE UGROUP "TDC0" SITE "R59C86D" ; +LOCATE UGROUP "TDC0s" SITE "R59C84D" ; + +LOCATE UGROUP "TDC1" SITE "R62C86D" ; +LOCATE UGROUP "TDC1s" SITE "R62C84D" ; + +LOCATE UGROUP "TDC2" SITE "R63C86D" ; +LOCATE UGROUP "TDC2s" SITE "R63C84D" ; + +LOCATE UGROUP "TDC3" SITE "R36C86D" ; +LOCATE UGROUP "TDC3s" SITE "R36C84D" ; + +LOCATE UGROUP "TDC4" SITE "R42C86D" ; +LOCATE UGROUP "TDC4s" SITE "R42C84D" ; + +LOCATE UGROUP "TDC5" SITE "R68C86D" ; +LOCATE UGROUP "TDC5s" SITE "R68C84D" ; + +LOCATE UGROUP "TDC6" SITE "R65C86D" ; +LOCATE UGROUP "TDC6s" SITE "R65C84D" ; + +LOCATE UGROUP "TDC7" SITE "R45C86D" ; +LOCATE UGROUP "TDC7s" SITE "R45C84D" ; + +LOCATE UGROUP "TDC8" SITE "R29C86D" ; +LOCATE UGROUP "TDC8s" SITE "R29C84D" ; + +LOCATE UGROUP "TDC9" SITE "R26C86D" ; +LOCATE UGROUP "TDC9s" SITE "R26C84D" ; + +LOCATE UGROUP "TDC10" SITE "R32C86D" ; +LOCATE UGROUP "TDC10s" SITE "R32C84D" ; + +LOCATE UGROUP "TDC11" SITE "R25C86D" ; +LOCATE UGROUP "TDC11s" SITE "R25C84D" ; + +LOCATE UGROUP "TDC12" SITE "R32C86D" ; +LOCATE UGROUP "TDC12s" SITE "R32C84D" ; + +LOCATE UGROUP "TDC13" SITE "R23C86D" ; +LOCATE UGROUP "TDC13s" SITE "R23C84D" ; + +LOCATE UGROUP "TDC14" SITE "R36C86D" ; +LOCATE UGROUP "TDC14s" SITE "R36C84D" ; + +LOCATE UGROUP "TDC15" SITE "R14C86D" ; +LOCATE UGROUP "TDC15s" SITE "R14C84D" ; + +LOCATE UGROUP "TDC16" SITE "R62C3D" ; +LOCATE UGROUP "TDC16s" SITE "R62C5D" ; + +LOCATE UGROUP "TDC17" SITE "R65C3D" ; +LOCATE UGROUP "TDC17s" SITE "R65C5D" ; + +LOCATE UGROUP "TDC18" SITE "R41C3D" ; +LOCATE UGROUP "TDC18s" SITE "R41C5D" ; + +LOCATE UGROUP "TDC19" SITE "R68C3D" ; +LOCATE UGROUP "TDC19s" SITE "R68C5D" ; + +LOCATE UGROUP "TDC20" SITE "R63C3D" ; +LOCATE UGROUP "TDC20s" SITE "R63C5D" ; + +LOCATE UGROUP "TDC21" SITE "R38C3D" ; +LOCATE UGROUP "TDC21s" SITE "R38C5D" ; + +LOCATE UGROUP "TDC22" SITE "R36C3D" ; +LOCATE UGROUP "TDC22s" SITE "R36C5D" ; + +LOCATE UGROUP "TDC23" SITE "R35C3D" ; +LOCATE UGROUP "TDC23s" SITE "R35C5D" ; + +LOCATE UGROUP "TDC24" SITE "R12C3D" ; +LOCATE UGROUP "TDC24s" SITE "R12C5D" ; + +LOCATE UGROUP "TDC25" SITE "R11C3D" ; +LOCATE UGROUP "TDC25s" SITE "R11C5D" ; + +LOCATE UGROUP "TDC26" SITE "R32C3D" ; +LOCATE UGROUP "TDC26s" SITE "R32C5D" ; + +LOCATE UGROUP "TDC27" SITE "R14C3D" ; +LOCATE UGROUP "TDC27s" SITE "R14C5D" ; + +LOCATE UGROUP "TDC28" SITE "R26C3D" ; +LOCATE UGROUP "TDC28s" SITE "R26C5D" ; + +LOCATE UGROUP "TDC29" SITE "R15C3D" ; +LOCATE UGROUP "TDC29s" SITE "R15C5D" ; + +LOCATE UGROUP "TDC30" SITE "R17C3D" ; +LOCATE UGROUP "TDC30s" SITE "R17C5D" ; + +LOCATE UGROUP "TDC31" SITE "R23C3D" ; +LOCATE UGROUP "TDC31s" SITE "R23C5D" ; + +LOCATE UGROUP "TDC32" SITE "R12C86D" ; +LOCATE UGROUP "TDC32s" SITE "R12C84D" ; + + +UGROUP "TDC0s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC1s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC2s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC3s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC4s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC5s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC6s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC7s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC8s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC9s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC10s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC11s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC12s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC13s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC14s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC15s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC16s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC17s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC18s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC19s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC20s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC21s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC22s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC23s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC24s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC25s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC26s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC27s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC28s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC29s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC30s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC31s" BBOX 1 2 + BLKNAME GND; + +UGROUP "TDC32s" BBOX 1 2 + BLKNAME GND; diff --git a/DBO/mdctdc.prj b/DBO/mdctdc.prj index 0958775..cfaba95 100644 --- a/DBO/mdctdc.prj +++ b/DBO/mdctdc.prj @@ -4,7 +4,7 @@ impl -add workdir -type fpga # device options set_option -technology ECP5UM -set_option -part LFE5UM_25F +set_option -part LFE5UM_45F set_option -package BG381C set_option -speed_grade -8 set_option -part_companion "" @@ -51,8 +51,6 @@ impl -active "workdir" #################### -add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" - #Packages add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" @@ -65,7 +63,7 @@ add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" -add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" #Fifos @@ -134,15 +132,18 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" ######################################### #channel 0, backplane -add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" -add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" #channel 1, SFP #add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" #add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" ########################################## -add_file -vhdl -lib work "../../dirich/cores/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" @@ -174,7 +175,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" @@ -191,9 +192,7 @@ add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" - add_file -vhdl -lib work "./mdctdc.vhd" #add_file -fpga_constraint "./synplify.fdc" - diff --git a/DBO/mdctdc.vhd b/DBO/mdctdc.vhd index c765f89..7cc3833 100644 --- a/DBO/mdctdc.vhd +++ b/DBO/mdctdc.vhd @@ -21,6 +21,8 @@ entity mdctdc is OUTP : in std_logic_vector(31 downto 0); TEST : out std_logic_vector(3 downto 0); + INJ : out std_logic_vector(3 downto 0); + PTEN : out std_logic_vector(2 downto 1); RSTN : out std_logic_vector(2 downto 1); MISO : in std_logic_vector(2 downto 1); @@ -70,6 +72,7 @@ architecture arch of mdctdc is signal med2int : med2int_array_t(0 to 0); signal int2med : int2med_array_t(0 to 0); signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal additional_reg : std_logic_vector ( 31 downto 0); signal readout_rx : READOUT_RX; @@ -143,9 +146,9 @@ begin TX_DLM_WORD => open, --SFP Connection - SD_PRSNT_N_IN => GPIO(1), - SD_LOS_IN => GPIO(1), - SD_TXDIS_OUT => GPIO(0), + SD_PRSNT_N_IN => GPIO(0), + SD_LOS_IN => GPIO(0), + SD_TXDIS_OUT => GPIO(1), --Control Interface BUS_RX => bussci_rx, BUS_TX => bussci_tx, @@ -257,7 +260,8 @@ begin SPI_CLK_OUT(1 downto 0) => SCK, --Header HEADER_IO => open, - ADDITIONAL_REG(0) => led_off, + ADDITIONAL_REG => additional_reg, + --LCD LCD_DATA_IN => (others => '0'), --ADC @@ -284,6 +288,9 @@ begin FLASH_HOLD <= '1'; FLASH_WP <= '1'; + led_off <= additional_reg(0); + FLASH_OVERRIDE <= not additional_reg(1); + --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- @@ -297,6 +304,15 @@ begin LED(0) <= (med2int(0).stat_op(10) or med2int(0).stat_op(11)) and not led_off; LED(1) <= med2int(0).stat_op(9) and not led_off; LED(2) <= FLASH_SELECT and not led_off; + + +-------------------------------------------------------------------------- +-- Controls +--------------------------------------------------------------------------- + PTEN <= "11"; + INJ <= additional_reg(19 downto 16); --"0000"; + TEST <= additional_reg(27 downto 24); --"0000"; + ------------------------------------------------------------------------------- -- TDC diff --git a/pinout/dbo.lpf b/pinout/dbo.lpf index 852a60b..b00a7dd 100644 --- a/pinout/dbo.lpf +++ b/pinout/dbo.lpf @@ -37,7 +37,7 @@ IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS25 ; IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS25 ; LOCATE COMP "LED_0" SITE "P19"; -LOCATE COMP "LED_1" SITE "T17"; +LOCATE COMP "LED_1" SITE "P18"; LOCATE COMP "LED_2" SITE "U16"; DEFINE PORT GROUP "LED_group" "LED*"; IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 ; @@ -111,3 +111,19 @@ LOCATE COMP "TEST_2" SITE "D9"; LOCATE COMP "TEST_3" SITE "C8"; DEFINE PORT GROUP "Test_group" "TEST*"; IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "INJ_0" SITE "J17"; +LOCATE COMP "INJ_1" SITE "H17"; +LOCATE COMP "INJ_2" SITE "N4"; +LOCATE COMP "INJ_3" SITE "P4"; + +DEFINE PORT GROUP "INJ_group" "INJ*"; +IOBUF GROUP "INJ_group" IO_TYPE=LVCMOS25 ; + +LOCATE COMP "PTEN_1" SITE "A19"; +LOCATE COMP "PTEN_2" SITE "B8"; +DEFINE PORT GROUP "PTEN_group" "PTEN*"; +IOBUF GROUP "PTEN_group" IO_TYPE=LVCMOS25 ; + + + -- 2.43.0