From 76e45fed9521a607995f6f2aa8dfe9ae6009cf69 Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 4 Apr 2013 14:32:20 +0200 Subject: [PATCH] pin assignment correction - cu --- base/cbmtof.lpf | 195 ++++++++++++++++++++++++++++++++++ cbmtof/cbmtof.vhd | 40 ++++--- cbmtof/compile_constraints.pl | 2 +- 3 files changed, 219 insertions(+), 18 deletions(-) create mode 100644 base/cbmtof.lpf diff --git a/base/cbmtof.lpf b/base/cbmtof.lpf new file mode 100644 index 0000000..627d5a9 --- /dev/null +++ b/base/cbmtof.lpf @@ -0,0 +1,195 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_OSC" SITE "U20"; #oscillator 200 +#LOCATE COMP "CLK_CM_0" SITE "AC17"; #CM0 for serdes +LOCATE COMP "CLK_CM_1" SITE "P21"; #CM1 +LOCATE COMP "CLK_CM_2" SITE "N23"; #CM2 +LOCATE COMP "CLK_CM_3" SITE "N5"; #CM3 +LOCATE COMP "CLK_CM_4" SITE "T21"; #CM4 +LOCATE COMP "CLK_CM_5" SITE "U6"; #CM6 +LOCATE COMP "CLK_CM_6" SITE "Y26"; #CM7 +LOCATE COMP "CLK_CM_7" SITE "V17"; #CM8 +LOCATE COMP "CLK_CM_8" SITE "V20"; #CM9 +LOCATE COMP "CLK_EXT" SITE "C14"; #external + +DEFINE PORT GROUP "CLK_group" +"CLK_CM[*]" +"CLK_EXT" +"CLK_OSC"; +IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +################################################################# +# Clock Manager +################################################################# +LOCATE COMP "CLK_MNGR_USER_0" SITE "M23"; +LOCATE COMP "CLK_MNGR_USER_1" SITE "M24"; +LOCATE COMP "CLK_MNGR_USER_2" SITE "L24"; +LOCATE COMP "CLK_MNGR_USER_3" SITE "K25"; +DEFINE PORT GROUP "CLK_MNGR_group" "CLK_MNGR_USER*" ; +IOBUF GROUP "CLK_MNGR_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + + +################################################################# +# DAC & SPI +################################################################# +LOCATE COMP "OR_IN" SITE "B2"; +IOBUF PORT "OR_IN" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "DAC_SCK" SITE "K8"; +LOCATE COMP "DAC_CS" SITE "H6"; +LOCATE COMP "DAC_SDI" SITE "J4"; +LOCATE COMP "DAC_SDO" SITE "L5"; +LOCATE COMP "DAC_CLR" SITE "C3"; + +DEFINE PORT GROUP "DAC_group" "DAC*"; +IOBUF GROUP "DAC_group" IO_TYPE=LVDS25; + +LOCATE COMP "FLASH_CLK" SITE "V24"; +LOCATE COMP "FLASH_CS" SITE "T25"; +LOCATE COMP "FLASH_DIN" SITE "T24"; +LOCATE COMP "FLASH_DOUT" SITE "V21"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "A20"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# LED +################################################################# + +LOCATE COMP "LED_CLK_GREEN" SITE "P23"; +LOCATE COMP "LED_CLK_RED" SITE "R22"; +LOCATE COMP "LED_GREEN" SITE "K24"; +LOCATE COMP "LED_ORANGE" SITE "J24"; +LOCATE COMP "LED_RED" SITE "J26"; +LOCATE COMP "LED_YELLOW" SITE "K26"; +LOCATE COMP "LED_SFP_GREEN" SITE "W17"; +LOCATE COMP "LED_SFP_RED" SITE "AB23"; + +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; + + +################################################################# +# INPUT +################################################################# +LOCATE COMP "INPUT_1" SITE "AD3"; +LOCATE COMP "INPUT_2" SITE "AE4"; +LOCATE COMP "INPUT_3" SITE "AD4"; +LOCATE COMP "INPUT_4" SITE "AD1"; +LOCATE COMP "INPUT_5" SITE "AC2"; +LOCATE COMP "INPUT_6" SITE "AB3"; +LOCATE COMP "INPUT_7" SITE "AA1"; +LOCATE COMP "INPUT_8" SITE "AA3"; +LOCATE COMP "INPUT_9" SITE "V3"; +LOCATE COMP "INPUT_10" SITE "U4"; +LOCATE COMP "INPUT_11" SITE "T7"; +LOCATE COMP "INPUT_12" SITE "G5"; +LOCATE COMP "INPUT_13" SITE "K2"; +LOCATE COMP "INPUT_14" SITE "H4"; +LOCATE COMP "INPUT_15" SITE "G2"; +LOCATE COMP "INPUT_16" SITE "E1"; +LOCATE COMP "INPUT_17" SITE "D1"; +LOCATE COMP "INPUT_18" SITE "C2"; +LOCATE COMP "INPUT_19" SITE "F2"; +LOCATE COMP "INPUT_20" SITE "D4"; +LOCATE COMP "INPUT_21" SITE "V10"; +LOCATE COMP "INPUT_22" SITE "W8"; +LOCATE COMP "INPUT_23" SITE "AE2"; +LOCATE COMP "INPUT_24" SITE "AA7"; +LOCATE COMP "INPUT_25" SITE "Y6"; +LOCATE COMP "INPUT_26" SITE "AB5"; +LOCATE COMP "INPUT_27" SITE "Y5"; +LOCATE COMP "INPUT_28" SITE "Y3"; +LOCATE COMP "INPUT_29" SITE "W1"; +LOCATE COMP "INPUT_30" SITE "V6"; +LOCATE COMP "INPUT_31" SITE "T1"; +LOCATE COMP "INPUT_32" SITE "M4"; + +DEFINE PORT GROUP "INPUT_group" "INPUT*" ; +IOBUF GROUP "INPUT_group" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; + + +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_LOS" SITE "AE23"; #this was AF23 in cbmrich +LOCATE COMP "SFP_TXDIS" SITE "AD23"; +LOCATE COMP "SFP_MOD_0" SITE "AC23"; +LOCATE COMP "SFP_MOD_1" SITE "AB20"; +LOCATE COMP "SFP_MOD_2" SITE "AB21"; +LOCATE COMP "SFP_RATE_SEL" SITE "AF23"; # doesn't exist in cbmrich +LOCATE COMP "SFP_TXFAULT" SITE "AB22"; # doesn't exist in cbmrich + +DEFINE PORT GROUP "SFP_group" "SFP*" ; +IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; + + +################################################################# +# Other I/O +################################################################# +LOCATE COMP "SPARE_LINE_0" SITE "E13"; +LOCATE COMP "SPARE_LINE_1" SITE "L21"; +LOCATE COMP "SPARE_LINE_2" SITE "P5"; + +DEFINE PORT GROUP "SPARE_LINE_group" "SPARE_LINE*" ; +IOBUF GROUP "SPARE_LINE_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +LOCATE COMP "LVDS_1" SITE "J23"; +LOCATE COMP "LVDS_2" SITE "G26"; +DEFINE PORT GROUP "LVDS_group" "LVDS*" ; +IOBUF GROUP "LVDS_group" IO_TYPE=LVDS25; + +LOCATE COMP "TEMPSENS" SITE "K23"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8; + + + +################################################################# +# Test Connector +################################################################# +LOCATE COMP "TEST_LINE_0" SITE "A10"; +LOCATE COMP "TEST_LINE_1" SITE "C10"; +LOCATE COMP "TEST_LINE_2" SITE "G9"; +LOCATE COMP "TEST_LINE_3" SITE "E10"; +LOCATE COMP "TEST_LINE_4" SITE "D8"; +LOCATE COMP "TEST_LINE_5" SITE "A9"; +LOCATE COMP "TEST_LINE_6" SITE "C8"; +LOCATE COMP "TEST_LINE_7" SITE "C9"; +LOCATE COMP "TEST_LINE_8" SITE "A8"; +LOCATE COMP "TEST_LINE_9" SITE "B8"; +LOCATE COMP "TEST_LINE_10" SITE "C7"; +LOCATE COMP "TEST_LINE_11" SITE "C6"; +LOCATE COMP "TEST_LINE_12" SITE "B7"; +LOCATE COMP "TEST_LINE_13" SITE "B6"; +LOCATE COMP "TEST_LINE_14" SITE "A7"; +LOCATE COMP "TEST_LINE_15" SITE "A6"; +LOCATE COMP "TEST_LINE_16" SITE "A17"; +LOCATE COMP "TEST_LINE_17" SITE "A18"; +LOCATE COMP "TEST_LINE_18" SITE "A16"; +LOCATE COMP "TEST_LINE_19" SITE "C16"; +LOCATE COMP "TEST_LINE_20" SITE "A15"; +LOCATE COMP "TEST_LINE_21" SITE "C15"; +LOCATE COMP "TEST_LINE_22" SITE "A14"; +LOCATE COMP "TEST_LINE_23" SITE "C13"; +LOCATE COMP "TEST_LINE_24" SITE "A13"; +LOCATE COMP "TEST_LINE_25" SITE "B13"; +LOCATE COMP "TEST_LINE_26" SITE "B12"; +LOCATE COMP "TEST_LINE_27" SITE "C12"; +LOCATE COMP "TEST_LINE_28" SITE "A12"; +LOCATE COMP "TEST_LINE_29" SITE "C11"; +LOCATE COMP "TEST_LINE_30" SITE "A11"; +LOCATE COMP "TEST_LINE_31" SITE "B11"; + +DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; + + diff --git a/cbmtof/cbmtof.vhd b/cbmtof/cbmtof.vhd index 473c261..f9561cf 100644 --- a/cbmtof/cbmtof.vhd +++ b/cbmtof/cbmtof.vhd @@ -14,16 +14,18 @@ entity cbmtof is port( --Clocks CLK_OSC : in std_logic; --for tdc measurements - CLK_CM : in std_logic_vector(9 downto 0); --from clock manager + CLK_CM : in std_logic_vector(8 downto 0); --from clock manager CLK_EXT : in std_logic; --Serdes --CLK_SERDES_INT_RIGHT : in std_logic; - SERDES_TX : out std_logic_vector(1 downto 0); - SERDES_RX : in std_logic_vector(1 downto 0); - SFP_TXDIS : out std_logic; - SFP_MOD : inout std_logic_vector(2 downto 0); - SFP_LOS : in std_logic; + SERDES_TX : out std_logic_vector(1 downto 0); + SERDES_RX : in std_logic_vector(1 downto 0); + SFP_TXDIS : out std_logic; + SFP_MOD : inout std_logic_vector(2 downto 0); + SFP_LOS : in std_logic; + SFP_RATE_SEL : out std_logic; -- doesn't exist in cbmrich + SFP_TXFAULT : out std_logic; -- doesn't exist in cbmrich --Connections SPARE_LINE : inout std_logic_vector(2 downto 0); @@ -294,7 +296,7 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( - CLK => CLK_CM(0), + CLK => CLK_CM(4), CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock @@ -309,7 +311,9 @@ begin SERDES_NUM => 0, --number of serdes in quad EXT_CLOCK => c_NO, --use internal clock USE_200_MHZ => c_YES, --run on 200 MHz clock - USE_CTC => c_YES --CTC required + USE_125_MHZ => c_NO, + USE_CTC => c_YES, --CTC required + USE_SLAVE => c_NO ) port map( CLK => clk_200_i, @@ -465,7 +469,7 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 7, + PORT_NUMBER => 9, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, others => 0) ) @@ -692,8 +696,6 @@ begin PROGRAMN => PROGRAMN ); - - --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -707,12 +709,16 @@ begin --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- - TEST_LINE(15 downto 1) <= INPUT(15 downto 1); - TEST_LINE(0) <= SPARE_LINE(0); - - + TEST_LINE(0) <= OR_IN; + TEST_LINE(8 downto 1) <= CLK_CM(8 downto 1); + TEST_LINE(9) <= CLK_EXT; + TEST_LINE(11 downto 10) <= SFP_MOD(2 downto 1); + TEST_LINE(13 downto 12) <= SPARE_LINE(2 downto 1); + TEST_LINE(31 downto 14) <= time_counter(31 downto 14); + LVDS(1) <= or_all(INPUT); LVDS(2) <= SPARE_LINE(0); + CLK_MNGR_USER(3 downto 0) <= (others => '0'); --------------------------------------------------------------------------- -- Test Circuits @@ -728,14 +734,14 @@ begin ------------------------------------------------------------------------------- THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 65, -- Number of TDC channels + CHANNEL_NUMBER => 3, -- Number of TDC channels CONTROL_REG_NR => 5) -- Number of control regs port map ( RESET => reset_i, CLK_TDC => CLK_OSC, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(64 downto 1), -- Channel start signals + HIT_IN => hit_in_i(2 downto 1), -- Channel start signals TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- diff --git a/cbmtof/compile_constraints.pl b/cbmtof/compile_constraints.pl index a86e782..7dc3c84 100755 --- a/cbmtof/compile_constraints.pl +++ b/cbmtof/compile_constraints.pl @@ -7,7 +7,7 @@ my $TOPNAME = "cbmtof"; #Name of top-level entity #create full lpf file -system("cp ../base/trb3_periph_cbmtof.lpf workdir/$TOPNAME.lpf"); +system("cp ../base/cbmtof.lpf workdir/$TOPNAME.lpf"); system("cat ../tdc_releases/tdc_v1.3/trbnet_constraints.lpf >> workdir/$TOPNAME.lpf"); system("cat ../tdc_releases/tdc_v1.3/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); -- 2.43.0