From 76f72d3d1eb758e0577d9f9f671918eab1b8e384 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Fri, 6 Mar 2015 07:55:14 +0100 Subject: [PATCH] Multicycle on busy_in, maybe that produces a timing error free design --- ADC/trb3_periph_adc_constraints.lpf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index d6fccd7..6d7446d 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -92,7 +92,7 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X; - +MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X; # we define everything doubled to make it work with all lattice/synplify versions # due to _ vs . notation of generate statements args... -- 2.43.0