From 770fc2388b1cbc29fc32c0e1536d4a6f952150e1 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Sat, 20 Jun 2015 09:42:01 +0200 Subject: [PATCH] Revert to 'CTS: At least compiles', aka TDC v2.1.3, Diamond 3.4 and only 36 ADC channels --- ADC/compile_constraints.pl | 17 ----- ADC/compile_periph_gsi.pl | 4 +- ADC/config.vhd | 10 +-- ADC/tdc_release | 2 +- ADC/trb3_periph_adc.prj | 34 ++++----- ADC/trb3_periph_adc.vhd | 6 +- ADC/trb3_periph_adc_constraints.lpf | 105 ++++++---------------------- 7 files changed, 44 insertions(+), 134 deletions(-) diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl index da557c0..5c0b8c8 100755 --- a/ADC/compile_constraints.pl +++ b/ADC/compile_constraints.pl @@ -70,23 +70,6 @@ close FILE; $lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g; -# for TDC v1.6.3 -$lpf =~ s#ff_array_en#ff_array_en_i#g; -$lpf =~ s#hit_mux_ch#hit_mux_ch/hit_i_5_u#g; - -# make the LPF diamond 2.1 compatible -# we assume that generate loops are all named with "gen_" -sub replace_dot { - my @m = @_; - $m[1] =~ s/\./_/g; - return join("", @m); -} -$lpf =~ s#(BLKNAME\s+)(.+?)([;\s])#replace_dot($1,$2,$3)#eg; -$lpf =~ s#(CELL\s+")(.+?)(")#replace_dot($1,$2,$3)#eg; -$lpf =~ s#(NET\s+")(.+?)(")#replace_dot($1,$2,$3)#eg; -$lpf =~ s#(COMP\s+")(.+?)(")#replace_dot($1,$2,$3)#eg; - - open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; print FILE $lpf; close FILE; diff --git a/ADC/compile_periph_gsi.pl b/ADC/compile_periph_gsi.pl index 05fb11e..80c3d64 100755 --- a/ADC/compile_periph_gsi.pl +++ b/ADC/compile_periph_gsi.pl @@ -9,9 +9,9 @@ use FileHandle; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity -my $lattice_path = '/opt/lattice/diamond/2.1_x64'; +my $lattice_path = '/opt/lattice/diamond/3.4_x64'; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $synplify_path = '/opt/synplicity/J-2014.09-SP2'; my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de'; my $lm_license_file_for_par = '1702@hadeb05.gsi.de'; ################################################################################### diff --git a/ADC/config.vhd b/ADC/config.vhd index 1a4c7bc..b3db5e1 100644 --- a/ADC/config.vhd +++ b/ADC/config.vhd @@ -37,7 +37,7 @@ package config is constant ADC_TRIGGER_LOGIC : integer := c_YES; -- ADC channels may be 48 or 36, the latter for enabling compilation -- with TDC and lattice diamond version >2.1 - constant ADC_CHANNELS : integer := 48; + constant ADC_CHANNELS : integer := 36; --Include the TDC (only useful for CFD readout mode) constant INCLUDE_TDC : integer := c_YES; @@ -50,14 +50,10 @@ package config is constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --> change names in constraints file - --ring buffer size: 32,64,96,128,dyn - --for TDC v1.6.3, only 0,1,3 are valid - constant RING_BUFFER_SIZE : integer range 0 to 7 := 0; --ring buffer size: 0, 1, 2, 3, 7 + --ring buffer size: 32,64,96,128,dyn + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 - constant TDC_CONTROL_REG_NR : integer := 6; - - ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/ADC/tdc_release b/ADC/tdc_release index 3f0371b..043eaed 120000 --- a/ADC/tdc_release +++ b/ADC/tdc_release @@ -1 +1 @@ -../../tdc/releases/tdc_v1.6.3 \ No newline at end of file +../../tdc/releases/tdc_v2.1.3/ \ No newline at end of file diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj index d6b7365..40cb090 100644 --- a/ADC/trb3_periph_adc.prj +++ b/ADC/trb3_periph_adc.prj @@ -12,41 +12,30 @@ set_option -speed_grade -8 set_option -part_companion "" # compilation/mapping options -#set_option -default_enum_encoding sequential +set_option -default_enum_encoding sequential set_option -symbolic_fsm_compiler 1 set_option -top_module "trb3_periph_adc" -#set_option -resource_sharing true - - - -# Lattice XP -set_option -maxfan 100 -set_option -fix_gated_and_generated_clocks 1 -set_option -RWCheckOnRam 1 -set_option -update_models_cp 0 -set_option -syn_edif_array_rename 1 - +set_option -resource_sharing true # map options set_option -frequency 200 -set_option -fanout_limit 1000 +set_option -fanout_limit 100 set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +#set_option -force_gsr set_option -force_gsr false +set_option -fixgatedclocks false #3 +set_option -fixgeneratedclocks false #3 set_option -compiler_compatible true -set_option -retiming 0 -set_option -pipe 1 -set_option -max_parallel_jobs 3 -#set_option -automatic_compile_point 1 -#set_option -continue_on_error 1 -set_option -resolve_multiple_driver 1 # simulation options set_option -write_verilog 0 set_option -write_vhdl 1 # automatic place and route (vendor) options -set_option -write_apr_constraint 1 +set_option -write_apr_constraint 0 # set result format/file last project -result_format "edif" @@ -204,8 +193,11 @@ if {$INCLUDE_TDC == 1} { add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd" add_file -vhdl -lib "work" "tdc_release/Readout.vhd" add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd" - add_file -vhdl -lib "work" "tdc_release/ROM_encoder_3.vhd" + add_file -vhdl -lib "work" "tdc_release/ROM_encoder_ecp3.vhd" add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher_A.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher_B.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher.vhd" add_file -vhdl -lib "work" "tdc_release/TDC.vhd" add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" add_file -vhdl -lib "work" "tdc_release/up_counter.vhd" diff --git a/ADC/trb3_periph_adc.vhd b/ADC/trb3_periph_adc.vhd index 5622b36..4d0fd22 100644 --- a/ADC/trb3_periph_adc.vhd +++ b/ADC/trb3_periph_adc.vhd @@ -182,6 +182,7 @@ architecture trb3_periph_adc_arch of trb3_periph_adc is signal tdc_inputs : std_logic_vector(TDC_CHANNEL_NUMBER-2 downto 0); + constant TDC_CONTROL_REG_NR : integer := 8; type tdc_ctrl_reg_arr_t is array (0 to TDC_CONTROL_REG_NR-1) of std_logic_vector(31 downto 0); signal tdc_ctrl_reg_arr : tdc_ctrl_reg_arr_t; signal tdc_ctrl_reg : std_logic_vector(TDC_CONTROL_REG_NR*32-1 downto 0); @@ -583,9 +584,8 @@ LED_YELLOW <= not med_stat_op(11); generic map ( CHANNEL_NUMBER => TDC_CHANNEL_NUMBER, -- Number of TDC channels STATUS_REG_NR => 21, -- Number of status regs - TDC_VERSION => TDC_VERSION, CONTROL_REG_NR => TDC_CONTROL_REG_NR, -- Number of control regs - higher than 8 check tdc_ctrl_addr - DEBUG => c_YES + DEBUG => c_NO ) port map ( RESET => reset_i, @@ -593,7 +593,7 @@ LED_YELLOW <= not med_stat_op(11); CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input HIT_IN => tdc_inputs, -- Channel start signals - HIT_CALIBRATION => osc_int, --clk_20_i, -- Hits for calibrating the TDC + HIT_CAL_IN => osc_int, --clk_20_i, -- Hits for calibrating the TDC TRG_WIN_PRE => tdc_ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => tdc_ctrl_reg(58 downto 48), -- Post-Trigger window width -- diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 0a10f09..8531664 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -19,8 +19,6 @@ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; GSR_NET NET "GSR_N"; MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; -MULTICYCLE TO CELL "THE_RESET_HANDLER/trb_reset_*" 20 ns; -MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns; ################################################################# # Locate Serdes and media interfaces @@ -94,7 +92,7 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #MULTICYCLE FROM CLKNET "gen_reallogic_THE_ADC/THE_ADC_RIGHT/clk_data" TO CLKNET "gen_reallogic_THE_ADC/adc_clk_right_c" 2 X; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X; -MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X; +MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/proc_readout*busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_q_*" TO CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_qq_*" 2 X; # left are ADCs 0-5 and 7 (counted from 0) @@ -163,9 +161,9 @@ LOCATE UGROUP "THE_ADC_PROC_cfd_11_group" REGION "THE_ADC_PROC_cfd_11_region"; UGROUP "EF_LT2" BBOX 10 51 BLKNAME THE_TDC/ReferenceChannel/Channel200 - BLKNAME THE_TDC/ReferenceChannel/Buffer_32.The_Buffer + BLKNAME THE_TDC/ReferenceChannel/Buffer_128.The_Buffer BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200 - BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_32.The_Buffer + BLKNAME THE_TDC/GEN_Channels.1.Channels/Buffer_128.The_Buffer ; LOCATE UGROUP "EF_LT2" SITE "R105C2D" ; @@ -189,108 +187,49 @@ UGROUP "ff_en_1" BBOX 1 1 BLKNAME THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en_1_i; LOCATE UGROUP "ff_en_1" SITE "R113C27D" ; -# TDC control register in top-level entity -MULTICYCLE FROM CELL "tdc_ctrl_reg*" 4x; - -# For v2.1.3 - -# ############################################################################# -# ## Unimportant Data Lines ## -# ############################################################################# -# #MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_RIGHT_c 2x; -# MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; - -# MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x; -# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; - -# MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr[*]" 4 X; -# MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/epoch_cntr[*]" 4 X; - -# MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; -# MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; - -# MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory[*]" 2.000000 X ; - -# MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x; - -# #MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ; - - -# BLOCK NET "THE_TDC/pulse[*]"; -# BLOCK NET "THE_TDC/hit_in_s*"; - -# MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; - - - - - - -# # MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; -# # MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; -# # MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; - -# ## Maybe effective - -# # MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; - - - -# PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en"; -# PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en"; - - -### For v1.6.3 - ############################################################################# ## Unimportant Data Lines ## ############################################################################# +#MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_LEFT_c 2x; MULTICYCLE FROM CELL "THE_TDC/reset_tdc*" TO CLKNET CLK_PCLK_RIGHT_c 2x; - MULTICYCLE FROM CELL "THE_TDC/reset_counters*" 4x; -# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; - -MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; -MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; - -# only relevant when TDC debug mode is c_YES -MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/sync_q*" 4 x; -MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/sync_q*" 4 x; -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; MULTICYCLE FROM CELL "THE_TDC/ReferenceChannel/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/ReferenceChannel/Channel200/ringBuffer_almost_full_sync*" 2x; +MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Channel200/RingBuffer*FIFO/FF*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/ringBuffer_almost_full_sync*" 2x; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/epoch_cntr_reg*" 3 X; -MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/epoch_cntr_reg*" 3 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/ReferenceChannel/Channel200/epoch_cntr[*]" 4 X; +MULTICYCLE FROM CELL "THE_TDC/TheEpochCounter/counter*" TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/epoch_cntr[*]" 4 X; MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_pre*" 4 x; MULTICYCLE TO CELL "THE_TDC/TheReadout/TW_post*" 4 x; +MULTICYCLE FROM CELL "THE_TDC/hit_edge[*]" TO CELL "THE_TDC/GEN_Channels.*.Channels/Channel200/memory[*]" 2.000000 X ; +MULTICYCLE TO CELL "THE_TDC/TheChannelDebugBus/data_out_reg[*]" 4 x; -# #MAXDELAY FROM GROUP "hitBuf*" TO GROUP "FC*" 0.600000 nS; -# #MAXDELAY FROM GROUP "hitBuf_ref*" TO GROUP "Ref_Ch" 0.600000 nS; +#MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "CLK_OSC_c" 4.000000 X ; -MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; +BLOCK NET "THE_TDC/pulse[*]"; +BLOCK NET "THE_TDC/hit_in_s*"; -## Maybe effective +MAXDELAY NET "THE_TDC/hit_in_i*" 0.600000 nS; #DATAPATH_ONLY ; -MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/Buffer*The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; -# # BLOCK NET "THE_TDC/reset_tdc*" ; -# # BLOCK NET "THE_TDC/reset_rdo*" ; -# # #BLOCK NET "THE_TDC/hit_in_i_*" ; -# # BLOCK NET "THE_TDC/hit_latch*" ; -# # BLOCK NET "THE_TDC/reset_counters_i*" ; +# MULTICYCLE FROM CELL "PROC_TDC_CTRL_REG*tdc_ctrl_reg*" 4x; +MULTICYCLE FROM CELL "tdc_ctrl_reg*" 4x; +# MULTICYCLE TO CELL "THE_TDC/GEN_Channels*Channels/Channel200/SimAdderNo*FC/FF*" 4x; +# MULTICYCLE TO CELL "THE_TDC/ReferenceChannel/Channel200/SimAdderNo*FC/FF*" 4x; + +## Maybe effective +# MULTICYCLE FROM CELL "THE_TDC/GEN_Channels*Channels/The_Buffer/*" TO CELL "THE_TDC/TheReadout/rd_en*" 2 X; -# # PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en_i"; -# # PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels*Channels/Channel200/ff_array_en_i"; +PROHIBIT SECONDARY NET "THE_TDC/ReferenceChannel/Channel200/ff_array_en"; +PROHIBIT SECONDARY NET "THE_TDC/GEN_Channels.1.Channels/Channel200/ff_array_en"; -- 2.43.0