From 7712af73534add6800ce2d003087bc6e4469f954 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 3 Mar 2021 14:23:09 +0100 Subject: [PATCH] small imrovements in dca_bridge and gub fix in simulation agwb handler --- src/agwb_handler_dca_sim.vhd | 4 +++- src/cri_trbnet_dca_bridge.vhd | 7 ++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/agwb_handler_dca_sim.vhd b/src/agwb_handler_dca_sim.vhd index 1059fb9..6aed9db 100644 --- a/src/agwb_handler_dca_sim.vhd +++ b/src/agwb_handler_dca_sim.vhd @@ -66,11 +66,13 @@ begin if WB_SLAVE_IN.we = '0' then WB_SLAVE_OUT.dat <= TX_DATA_IN; WB_SLAVE_OUT.ack <= '1'; + TX_READ_ACK <= '1'; end if; elsif WB_SLAVE_IN.adr = x"00000003" then if WB_SLAVE_IN.we = '0' then - WB_SLAVE_OUT.dat <= TX_DATA_IN; + WB_SLAVE_OUT.dat <= TX_SIZE_DATA; WB_SLAVE_OUT.ack <= '1'; + TX_SIZE_ACK <= '1'; end if; end if; end if; diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd index 4a34427..22cfa89 100644 --- a/src/cri_trbnet_dca_bridge.vhd +++ b/src/cri_trbnet_dca_bridge.vhd @@ -121,6 +121,8 @@ signal tx_data_size_dca : std_logic_vector(15 downto 0); signal preload_word_tx_fifo : std_logic; +signal tx_data_out : std_logic_vector(31 downto 0); + begin -- from wishbone: @@ -141,7 +143,7 @@ begin RX_DATA_RDY => rx_data_wr, TX_READ_ACK => tx_rd_ack, - TX_DATA_IN => tx_fifo_q, + TX_DATA_IN => tx_data_out, TX_DATA_SIZE => tx_data_size_dca, TX_READ_SIZE_ACK => tx_rd_size_ack, @@ -265,6 +267,9 @@ DCA_INIT_DATA_OUT <= rx_fifo_q(15 downto 0); dca_init_dataready <= '1' when (DCA_INIT_READ_IN = '1' and dissect_current_state = LOAD_TO_HUB) or (dissect_current_state = WAIT_FOR_HUB) else '0'; + +tx_data_out <= x"00000000" when (dissect_current_state = IDLE) + else tx_fifo_q; PACKET_NUM_PROC : process(CLK) begin -- 2.43.0