From 778ac2ce7f161d628de36e791760bacba70fdcdb Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Tue, 8 Oct 2013 11:18:18 +0200 Subject: [PATCH] Backup (still got 4ns issue) --- base/trb3_periph_cbmnet.lpf | 2 +- cbmnet/code/cbmnet_phy_ecp3.vhd | 31 +++++++++++++++++++++--------- cbmnet/code/cbmnet_phy_pkg.vhd | 4 ++++ cbmnet/code/cbmnet_phy_tx_gear.vhd | 9 ++++++++- cbmnet/cores/cbmnet_sfp1.txt | 2 +- cbmnet/trb3_periph_cbmnet.vhd | 2 ++ 6 files changed, 38 insertions(+), 12 deletions(-) diff --git a/base/trb3_periph_cbmnet.lpf b/base/trb3_periph_cbmnet.lpf index 177c22b..9fcf5d0 100644 --- a/base/trb3_periph_cbmnet.lpf +++ b/base/trb3_periph_cbmnet.lpf @@ -76,7 +76,7 @@ LOCATE COMP "TEST_LINE_13" SITE "C10"; LOCATE COMP "TEST_LINE_14" SITE "H10"; LOCATE COMP "TEST_LINE_15" SITE "H11"; DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN SLEWRATE=FAST DRIVE=12; ################################################################# # Connection to AddOn diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd index a105c0c..1f902cf 100644 --- a/cbmnet/code/cbmnet_phy_ecp3.vhd +++ b/cbmnet/code/cbmnet_phy_ecp3.vhd @@ -73,10 +73,15 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is signal rclk_250_i : std_logic; -- recovered word clock signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL - + + signal clk_tx_half_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL + signal rst_i : std_logic; -- High-active reset driven by external logic signal rst_n_i : std_logic; -- Low-active version of rst_i + signal clk_serdes_rx_ref : std_logic; + signal clk_serdes_tx_ref : std_logic; + -- SERDES/PCS -- status signal rx_los_low_i : std_logic; @@ -188,11 +193,15 @@ begin rst_n_i <= not rst_i; gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate - clk_125_i <= rclk_125_i; + clk_125_i <= rclk_125_i; + clk_serdes_rx_ref <= clk_125_local; + clk_serdes_tx_ref <= rclk_125_i; end generate; gen_master_clock : if IS_SYNC_SLAVE = c_NO generate - clk_125_i <= clk_125_local; + clk_125_i <= clk_tx_half_i; + clk_serdes_rx_ref <= clk_tx_half_i; + clk_serdes_tx_ref <= clk_125_local; end generate; ------------------------------------------------- @@ -207,16 +216,15 @@ begin hdoutn_ch0 => SD_TXD_N_OUT, -- CLOCKS - txiclk_ch0 => clk_125_i, - rx_full_clk_ch0 => rclk_250_i, rx_half_clk_ch0 => open, -- recovered (and correctly aligned) 125 MHz clock is generated by gear tx_full_clk_ch0 => clk_tx_full_i, tx_half_clk_ch0 => open, - fpga_rxrefclk_ch0 => clk_125_local, - fpga_txrefclk => clk_125_i, + fpga_rxrefclk_ch0 => clk_serdes_rx_ref, + fpga_txrefclk => clk_serdes_tx_ref, + txiclk_ch0 => clk_tx_full_i, -- RESETS rst_qd_c => rst_qd_i, @@ -330,9 +338,13 @@ begin rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES); - THE_TX_GEAR: CBMNET_PHY_TX_GEAR port map ( + THE_TX_GEAR: CBMNET_PHY_TX_GEAR + generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE) + port map ( CLK_250_IN => clk_tx_full_i, -- in std_logic; CLK_125_IN => clk_125_i, -- in std_logic; + CLK_125_OUT => clk_tx_half_i, + RESET_IN => tx_gear_reset_i, -- in std_logic; DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0) @@ -341,7 +353,8 @@ begin ); tx_gear_reset_i <= not tx_rst_fsm_ready_i; - process is begin + process is + begin wait until rising_edge(clk_tx_full_i); tx_data_debug_state_i <= not tx_data_debug_state_i; diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd index 6201dc0..8c1336b 100644 --- a/cbmnet/code/cbmnet_phy_pkg.vhd +++ b/cbmnet/code/cbmnet_phy_pkg.vhd @@ -71,9 +71,13 @@ package cbmnet_phy_pkg is end component; component CBMNET_PHY_TX_GEAR is + generic ( + IS_SYNC_SLAVE : integer range 0 to 1 := c_YES + ); port ( CLK_250_IN : in std_logic; CLK_125_IN : in std_logic; + CLK_125_OUT : out std_logic; RESET_IN : in std_logic; DATA_IN : in std_logic_vector(17 downto 0); diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd index def3e40..f6d0e46 100644 --- a/cbmnet/code/cbmnet_phy_tx_gear.vhd +++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd @@ -10,10 +10,15 @@ library work; use work.cbmnet_phy_pkg.all; entity CBMNET_PHY_TX_GEAR is + generic ( + IS_SYNC_SLAVE : integer range 0 to 1 := c_YES + ); port ( -- SERDES PORT CLK_250_IN : in std_logic; CLK_125_IN : in std_logic; + CLK_125_OUT : out std_logic; + RESET_IN : in std_logic; DATA_IN : in std_logic_vector(17 downto 0); @@ -40,14 +45,16 @@ begin clk_125_xfer_buf_i <= clk_125_xfer_i; clk_125_xfer_del_i <= clk_125_xfer_buf_i; + CLK_125_OUT <= '0'; case fsm_i is when FSM_WAIT => - if clk_125_xfer_buf_i /= clk_125_xfer_del_i then + if clk_125_xfer_buf_i /= clk_125_xfer_del_i or IS_SYNC_SLAVE = c_NO then fsm_i <= FSM_HIGH; end if; when FSM_HIGH => + CLK_125_OUT <= '1'; DATA_OUT <= data_in_buf125_i(17) & data_in_buf125_i(15 downto 8); low_data_i <= data_in_buf125_i(16) & data_in_buf125_i( 7 downto 0); fsm_i <= FSM_LOW; diff --git a/cbmnet/cores/cbmnet_sfp1.txt b/cbmnet/cores/cbmnet_sfp1.txt index 68a1af7..d897a97 100644 --- a/cbmnet/cores/cbmnet_sfp1.txt +++ b/cbmnet/cores/cbmnet_sfp1.txt @@ -19,7 +19,7 @@ CH0_RX_DATA_RATE "FULL" CH0_TX_DATA_RATE "FULL" CH0_TX_DATA_WIDTH "8" CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "ENABLED" +CH0_TX_FIFO "DISABLED" CH0_RX_FIFO "DISABLED" CH0_TDRV "0" #CH0_TX_FICLK_RATE 250.0 diff --git a/cbmnet/trb3_periph_cbmnet.vhd b/cbmnet/trb3_periph_cbmnet.vhd index 00fc2dd..0e99fff 100644 --- a/cbmnet/trb3_periph_cbmnet.vhd +++ b/cbmnet/trb3_periph_cbmnet.vhd @@ -376,6 +376,8 @@ begin ); cbm_res_n <= not rreset_i; + -- TEST_LINE <= phy_stat_op; + TEST_LINE(7 downto 0) <= phy_stat_debug(7 downto 0); TEST_LINE(8) <= cbm_SERDES_ready; TEST_LINE(9) <= cbm_link_active; -- 2.43.0