From 77b691b91c4606990ae90412d37b1fb8221931b6 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 7 Jul 2014 18:08:39 +0200 Subject: [PATCH] ADC: Adding many missing things to LPF files...how stupid! --- ADC/trb3_periph_adc_constraints.lpf | 19 ++++++++---- base/trb3_periph_adc.lpf | 45 +++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+), 6 deletions(-) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 8c243a8..d1099d2 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -6,12 +6,12 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; +SYSCONFIG MCCLK_FREQ = 20; - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Reset Nets @@ -20,6 +20,14 @@ GSR_NET NET "GSR_N"; MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset*" 20 ns; +################################################################# +# Locate Serdes and media interfaces +################################################################# + +LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; + ################################################################# # Clocks @@ -30,4 +38,3 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_0"; #USE PRIMARY2EDGE NET "THE_ADC/clk_adcfast_i_1"; - diff --git a/base/trb3_periph_adc.lpf b/base/trb3_periph_adc.lpf index 109757a..11fe6b2 100644 --- a/base/trb3_periph_adc.lpf +++ b/base/trb3_periph_adc.lpf @@ -198,3 +198,48 @@ LOCATE COMP "FPGA_SDO_1" SITE "T24"; DEFINE PORT GROUP "FPGA_group" "FPGA_*" ; IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; + +################################################################# +# Flash ROM and Reboot +################################################################# + +LOCATE COMP "FLASH_CLK" SITE "B12"; +LOCATE COMP "FLASH_CS" SITE "E11"; +LOCATE COMP "FLASH_DIN" SITE "E12"; +LOCATE COMP "FLASH_DOUT" SITE "A12"; + +DEFINE PORT GROUP "FLASH_group" "FLASH*" ; +IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +LOCATE COMP "PROGRAMN" SITE "B11"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + + +################################################################# +# Misc +################################################################# +LOCATE COMP "TEMPSENS" SITE "A13"; +IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ; + +#coding of FPGA number +LOCATE COMP "CODE_LINE_1" SITE "AA20"; +LOCATE COMP "CODE_LINE_0" SITE "Y21"; +IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ; +IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +#terminated differential pair to pads +#LOCATE COMP "SUPPL" SITE "C14"; +#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ; + + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_GREEN" SITE "F12"; +LOCATE COMP "LED_ORANGE" SITE "G13"; +LOCATE COMP "LED_RED" SITE "A15"; +LOCATE COMP "LED_YELLOW" SITE "A16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12; + + -- 2.43.0