From 77c9cf0a2348b5615efa4ded2e4a96a69f5c8f91 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 1 Feb 2011 16:24:39 +0000 Subject: [PATCH] *** empty log message *** --- compile_frankfurt.pl | 5 +- constraints_pexor.lpf | 2 + design/dma_adapter.vhd | 298 +++++++++++++++++++ design/pci_core.vhd | 208 ++++++------- design/wb_intf.vhd | 153 ++++++++++ design/wb_tlc.vhd | 572 +++++++++++++++++++++++++++--------- design/wb_tlc_cpld.vhd | 150 ++++++++++ design/wb_tlc_cpld_fifo.vhd | 122 ++++++++ design/wb_tlc_dec.vhd | 77 +++++ pcie_components.vhd | 227 ++++++++++---- pexor.prj | 39 ++- pexor.vhd | 471 +++++++++++++++++++++++++++++ size.txt | 97 ++++++ 13 files changed, 2113 insertions(+), 308 deletions(-) create mode 100644 design/dma_adapter.vhd create mode 100644 design/wb_intf.vhd create mode 100644 design/wb_tlc_cpld.vhd create mode 100644 design/wb_tlc_cpld_fifo.vhd create mode 100644 design/wb_tlc_dec.vhd create mode 100644 pexor.vhd diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index 9e2acd0..a496b8c 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -85,9 +85,10 @@ foreach (@a) { if(/\@E:/) { - $c="cat $TOPNAME.srr"; + print "\n"; + $c="cat $TOPNAME.srr | grep \"\@E\""; system($c); - print "bdabdhsadbhjasdhasldhbas"; + print "\n\n"; exit 129; } } diff --git a/constraints_pexor.lpf b/constraints_pexor.lpf index cf0ef87..dc15853 100644 --- a/constraints_pexor.lpf +++ b/constraints_pexor.lpf @@ -21,6 +21,7 @@ BLOCK RD_DURING_WR_PATHS ; # Serdes ######################################### LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_100_THE_SERDES/PCSA_INST" SITE "PCS36000"; +LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_serdes_0_100_THE_SERDES/PCSA_INST" SITE "PCS36100"; LOCATE COMP "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/u1_pci_exp_pcs/pcsa_inst" SITE "PCS3E100" ; LOCATE COMP "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/u1_flxmc_pcie_core/u1_phy_dll/u1_flxmc_top_ebr/flxmc_top_mib" SITE "RUMACO1" ; @@ -33,3 +34,4 @@ MULTICYCLE "M1" START CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_25 MULTICYCLE "M2" START CLKNET "THE_PCI_CORE/CLK_125_OUT_inferred_clock" END CLKNET "THE_PCI_CORE/THE_PCIE/u1_flxmc_sys_pcie/sys_clk_250_inferred_clock" 8.000000 ns ; +MULTICYCLE FROM CELL "THE_RESET_HANDLER/trb_reset_buffer" 10 ns; \ No newline at end of file diff --git a/design/dma_adapter.vhd b/design/dma_adapter.vhd new file mode 100644 index 0000000..af10c01 --- /dev/null +++ b/design/dma_adapter.vhd @@ -0,0 +1,298 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.version.all; + +entity dma_adapter is + port( + RSTN_IN : in std_logic; + CLK_125_IN : in std_logic; + ENABLE_IN : in std_logic; + + WB_CLK_IN : in std_logic; + WB_RST_IN : in std_logic; + WB_DAT_IN : in std_logic_vector(63 downto 0); + WB_ADR_IN : in std_logic_vector(31 downto 0); + WB_CYC_IN : in std_logic; + WB_LOCK_IN : in std_logic; + WB_SEL_IN : in std_logic_vector(7 downto 0); + WB_STB_IN : in std_logic; + WB_WE_IN : in std_logic; + WB_DAT_OUT : out std_logic_vector(63 downto 0); + WB_ACK_OUT : out std_logic; + WB_ERR_OUT : out std_logic; + WB_RTY_OUT : out std_logic; + + DMA_REQ_OUT : out std_logic_vector(1 downto 0); + DMA_ACK_IN : in std_logic_vector(1 downto 0); + BURST_LEN_IN : in std_logic_vector(15 downto 0); + ACTIVE_CH_IN : in std_logic_vector(1 downto 0); + REQUESTOR_ID_IN: in std_logic_vector(15 downto 0); + + TX_ST_OUT : out std_logic; + TX_END_OUT : out std_logic; + TX_DWEN_OUT : out std_logic; + TX_DATA_OUT : out std_logic_vector(63 downto 0); + TX_REQ_OUT : out std_logic; + TX_RDY_IN : in std_logic; + TX_VAL_IN : in std_logic; + TX_CA_PH_IN : in std_logic_vector(8 downto 0); + TX_CA_PD_IN : in std_logic_vector(12 downto 0); + TX_CA_NPH_IN : in std_logic_vector(8 downto 0); + + RX_CR_CPLH_OUT : out std_logic; + RX_CR_CPLD_OUT : out std_logic_vector(7 downto 0); + UNEXP_CMPL_OUT : out std_logic; + RX_ST_IN : in std_logic; + RX_END_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_DATA_IN : in std_logic_vector(63 downto 0); + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + +architecture dma_adapter_arch of dma_adapter is + + signal wb_dat_flipped : std_logic_vector(63 downto 0); + signal wb_dat_o_flip : std_logic_vector(63 downto 0); + + signal ch1_rdy : std_logic; + signal ch1_size : std_logic_vector(11 downto 0); + signal ch1_rden : std_logic; + signal ch1_pending : std_logic; + signal ch_data : std_logic_vector(63 downto 0); + signal ch_dv : std_logic; + + type ctrl_state_t is (CTRL_IDLE, CTRL_CREDIT, CTRL_SEND); + signal ctrl_state : ctrl_state_t; + signal ctrl_tx_cr_read : std_logic; + signal ctrl_tx_d_read : std_logic; + signal ctrl_tx_empty : std_logic; + signal ctrl_enable : std_logic; + + signal tx_end_i : std_logic; + + signal credit_available_np : std_logic; + signal credit_available_p : std_logic; + signal credit_available : std_logic; + + signal tx_pd : std_logic_vector(4 downto 0); + signal tx_ph : std_logic; + + signal debug_dma_rx_fifo : std_logic_vector(31 downto 0); + signal debug_dma_tx_fifo : std_logic_vector(31 downto 0); + signal debug_dma_wbs : std_logic_vector(31 downto 0); + +begin + + wb_dat_flipped <= WB_DAT_IN(7 downto 0) & WB_DAT_IN(15 downto 8) & WB_DAT_IN(23 downto 16) & WB_DAT_IN(31 downto 24) + & WB_DAT_IN(39 downto 32) & WB_DAT_IN(47 downto 40) & WB_DAT_IN(55 downto 48) & WB_DAT_IN(63 downto 56); + + WB_DAT_OUT <= wb_dat_o_flip(7 downto 0) & wb_dat_o_flip(15 downto 8) & wb_dat_o_flip(23 downto 16) & wb_dat_o_flip(31 downto 24) + & wb_dat_o_flip(39 downto 32) & wb_dat_o_flip(47 downto 40) & wb_dat_o_flip(55 downto 48) & wb_dat_o_flip(63 downto 56); + + + TX_END_OUT <= tx_end_i; + + +----------------------------------------------------------------------- +-- DMA Wishbone Interface +----------------------------------------------------------------------- + +THE_WBS_INTERFACE : dma_wbs + port map( + wb_clk_i => WB_CLK_IN, + wb_rst_i => WB_RST_IN, + wb_dat_i => WB_DAT_IN, + wb_adr_i => WB_ADR_IN, + wb_cyc_i => WB_CYC_IN, + wb_lock_i => WB_LOCK_IN, + wb_sel_i => WB_SEL_IN, + wb_stb_i => WB_STB_IN, + wb_we_i => WB_WE_IN, + wb_dat_o => WB_DAT_OUT, + wb_ack_o => WB_ACK_OUT, + wb_err_o => WB_ERR_OUT, + wb_rty_o => WB_RTY_OUT, + + dma_req => DMA_REQ_OUT, + dma_ack => DMA_ACK_IN, + burst_len => BURST_LEN_IN, + active_ch => ACTIVE_CH_IN, + requestor_id => REQUESTOR_ID_IN, + enable => ENABLE_IN, + + c_pd => tx_pd_wb, + c_nph => tx_nph_wb, + c_ph => tx_ph_wb, + tx_dwen => tx_dwen_wb, + tx_nlfy => open, + tx_end => tx_end_wb, + tx_st => tx_st_wb, + tx_dv => tx_dv_wb, + tx_cv => tx_cv_wb, + tx_full => tx_full, + tx_data => tx_data_wb, + + ch1_rdy => ch1_rdy, + ch1_size => ch1_size, + ch1_rden => ch1_rden, + ch1_pending => ch1_pending, + ch_data => ch_data, + ch_dv => ch_dv, + + debug => debug_dma_wbs + ); + + +----------------------------------------------------------------------- +-- TX Fifo +----------------------------------------------------------------------- +THE_DMA_TX_FIFO : dma_tx_fifo + port( + wb_clk_i => WB_CLK_IN, + clk_125 => CLK_125_IN, + rstn => RSTN_IN, + + tx_st_in => tx_st_wb, + tx_end_in => tx_end_wb, + tx_dwen_in => tx_dwen_wb, + tx_dv => tx_dv_wb, + tx_cv => tx_cv_wb, + tx_data_in => tx_data_wb, + tx_pd_in => tx_pd_wb, + tx_nph_in => tx_nph_wb, + tx_ph_in => tx_ph_wb, + + tx_st_out => TX_ST_OUT, + tx_end_out => tx_end_i, + tx_dwen_out => TX_DWEN_OUT, + tx_nph_out => tx_nph, + tx_ph_out => tx_ph, + tx_data_out => TX_DATA_OUT, + tx_pd_out => tx_pd, + empty => tx_empty, + full => tx_full, + + credit_read => ctrl_tx_cr_read, + data_read => ctrl_tx_d_read, + cr_avail => credit_available, + tx_rdy => TX_RDY_IN, + tx_val => TX_VAL_IN, + tx_req => TX_REQ_OUT, + + debug => debug_dma_tx_fifo(7 downto 0), + ); + + +----------------------------------------------------------------------- +-- DMA CA +----------------------------------------------------------------------- + +PROC_DMA_CA : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + if RSTN_IN = '0' then + credit_available_p <= '0'; + credit_available_np <= '0'; + else + if tx_ph = '1' then + if (TX_CA_PH_IN(8) = '1' or unsigned(TX_CA_PH_IN(7 downto 0)) > to_unsigned(1,8)) + or (TX_CA_PD_IN(12) = '1' or unsigned(TX_CA_PD_IN(11 downto 1)) >= unsigned(tx_pd(3 downto 0))) then + credit_available_p <= '1'; + else + credit_available_p <= '0'; + end if; + end if; + if TX_CA_NPH_IN = '1' then + if TX_CA_NPH_IN(8) = '1' or unsigned(TX_CA_NPH_IN(7 downto 0) > to_unsigned(1,8)) then + credit_available_np <= '1'; + else + credit_available_np <= '0'; + end if; + else + credit_available_np <= '0'; + end if; + end if; + end if; + end process; + +----------------------------------------------------------------------- +-- DMA CTRL +----------------------------------------------------------------------- + +PROC_DMA_CTRL : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + if RSTN_IN = '0' then + ctrl_state <= CTRL_IDLE; + ctrl_tx_cr_read <= '0'; + ctrl_tx_d_read <= '0'; + else + case ctrl_state is + when CTRL_IDLE => + if ctrl_enable = '1' and ctrl_tx_empty = '0' then + ctrl_state <= CTRL_CREDIT; + ctrl_tx_cr_read <= '1'; + end if; + when CTRL_CREDIT => + ctrl_tx_cr_read <= '0'; + if credit_available = '1' then + ctrl_tx_d_read <= '1'; + ctrl_state <= CTRL_SEND; + end if; + when CTRL_SEND => +-- if TX_RDY_IN = '1' then --the packet is being sent +-- ctrl_tx_d_read <= '1'; --this is only a gate to read data +-- elsif tx_end_i = '1' and ctrl_tx_empty = '0' and TX_VAL_IN = '1' then --go send next TLP +-- ctrl_tx_d_read <= '1'; +-- els + if tx_end_i = '1' and ctrl_tx_empty = '1' and TX_VAL_IN = '1' then --all TLP sent + ctrl_tx_d_read <= '0'; + ctrl_state <= IDLE; + end if; + end case; + end if; + end if; + end process; + + +----------------------------------------------------------------------- +-- RX Fifo +----------------------------------------------------------------------- + +THE_RX_FIFO : dma_rx_fifo + port( +v + + rx_st => RX_ST_IN, + rx_end => RX_END_IN, + rx_dwen => RX_DWEN_IN, + rx_data => RX_DATA_IN, + + active_ch => ACTIVE_CH_IN, + ch1_rdy => ch1_rdy, + ch1_size => ch1_size, + ch1_rden => ch1_rden, + ch1_pending=> ch1_pending, + ch_data => ch_data, + ch_dv => ch_dv, + cplh_cr => RX_CR_CPLH_OUT, + cpld_cr => RX_CR_CPLD_OUT, + unexp_cmpl => UNEXP_CMPL_OUT, + + debug => debug_dma_rx_fifo(15 downto 0) + ); + + + + + + +end architecture; \ No newline at end of file diff --git a/design/pci_core.vhd b/design/pci_core.vhd index 7e0da07..0e4d72f 100644 --- a/design/pci_core.vhd +++ b/design/pci_core.vhd @@ -25,18 +25,15 @@ entity pci_core is --single access BUS_ADDR_OUT : out std_logic_vector(31 downto 0); - BUS_WDAT_OUT : out std_logic_vector(63 downto 0); - BUS_RDAT_IN : in std_logic_vector(63 downto 0); - BUS_SEL_OUT : out std_logic_vector(7 downto 0); + BUS_WDAT_OUT : out std_logic_vector(31 downto 0); + BUS_RDAT_IN : in std_logic_vector(31 downto 0); + BUS_SEL_OUT : out std_logic_vector(3 downto 0); BUS_WE_OUT : out std_logic; BUS_CYC_OUT : out std_logic; BUS_STB_OUT : out std_logic; BUS_LOCK_OUT : out std_logic; --- BUS_CTI_OUT : out std_logic_vector(2 downto 0); BUS_ACK_IN : in std_logic; --- BUS_ERR_IN : in std_logic; --- BUS_RETRY_IN : in std_logic; --- BUS_EOD_IN : in std_logic; + --DMA DMA_ADDR : in std_logic_vector(31 downto 0); @@ -325,64 +322,64 @@ rst_n <= not RESET_IN; requestor_id_i <= bus_num_i & dev_num_i & func_num_i; --- THE_DMA_ADAPTER : dma_adapter --- port map( --- RSTN => rst_n, --- CLK_125 => clk_125_i, --- ENABLE => '1', --- --- WB_CLK_I => CLK_WB_IN, --- WB_RST_I => rst_n, --- WB_DAT_I => DMA_WDAT, --- WB_ADR_I => DMA_ADDR, --- WB_CYC_I => DMA_CYC, --- WB_LOCK_I => DMA_LOCK, --- WB_SEL_I => DMA_SEL, --- WB_STB_I => DMA_STB, --- WB_WE_I => DMA_WE, --- WB_DAT_O => DMA_RDAT, --- WB_ACK_O => DMA_ACK, --- WB_ERR_O => DMA_ERR, --- WB_RTY_O => DMA_RETRY, --- --- DMA_REQ => dma_req_adp_i, --- DMA_ACK => dma_ack_i, --- BURST_LEN => burst_len_i, --- ACTIVE_CH => active_ch_i, --- REQUESTOR_ID => requestor_id_i, --- --- TX_ST => tx_st_dma_i, --- TX_END => tx_end_dma_i, --- TX_DWEN => tx_dwen_dma_i, --- TX_DATA => tx_data_dma_i, --- TX_REQ => tx_req_dma_i, --- TX_RDY => tx_rdy_dma_i, --- TX_VAL => tx_val_i, --- TX_CA_PH => tx_ca_ph_i, --- TX_CA_PD => tx_ca_pd_i, --- TX_CA_NPH => tx_ca_nph_i, --- --- RX_CR_CPLH => open, --- RX_CR_CPLD => open, --- UNEXP_CMPL => open, --- RX_ST => rx_st_i, --- RX_END => rx_end_i, --- RX_DWEN => rx_dwen_i, --- RX_DATA => rx_data_i, --- --- DEBUG => debug_dma_apater_i --- ); - -DMA_ERR <= '0'; -DMA_ACK <= '0'; -DMA_RETRY <= '0'; -DMA_RDAT <= (others => '0'); - -tx_data_dma_i <= (others => '0'); -tx_st_dma_i <= '0'; -tx_end_dma_i <= '0'; -tx_dwen_dma_i <= '0'; -tx_req_dma_i <= '0'; +THE_DMA_ADAPTER : dma_adapter + port map( + RSTN => rst_n, + CLK_125 => clk_125_i, + ENABLE => '1', + + WB_CLK_I => CLK_WB_IN, + WB_RST_I => rst_n, + WB_DAT_I => DMA_WDAT, + WB_ADR_I => DMA_ADDR, + WB_CYC_I => DMA_CYC, + WB_LOCK_I => DMA_LOCK, + WB_SEL_I => DMA_SEL, + WB_STB_I => DMA_STB, + WB_WE_I => DMA_WE, + WB_DAT_O => DMA_RDAT, + WB_ACK_O => DMA_ACK, + WB_ERR_O => DMA_ERR, + WB_RTY_O => DMA_RETRY, + + DMA_REQ => dma_req_adp_i, + DMA_ACK => dma_ack_i, + BURST_LEN => burst_len_i, + ACTIVE_CH => active_ch_i, + REQUESTOR_ID => requestor_id_i, + + TX_ST => tx_st_dma_i, + TX_END => tx_end_dma_i, + TX_DWEN => tx_dwen_dma_i, + TX_DATA => tx_data_dma_i, + TX_REQ => tx_req_dma_i, + TX_RDY => tx_rdy_dma_i, + TX_VAL => tx_val_i, + TX_CA_PH => tx_ca_ph_i, + TX_CA_PD => tx_ca_pd_i, + TX_CA_NPH => tx_ca_nph_i, + + RX_CR_CPLH => open, + RX_CR_CPLD => open, + UNEXP_CMPL => open, + RX_ST => rx_st_i, + RX_END => rx_end_i, + RX_DWEN => rx_dwen_i, + RX_DATA => rx_data_i, + + DEBUG => debug_dma_apater_i + ); + +-- DMA_ERR <= '0'; +-- DMA_ACK <= '0'; +-- DMA_RETRY <= '0'; +-- DMA_RDAT <= (others => '0'); + +-- tx_data_dma_i <= (others => '0'); +-- tx_st_dma_i <= '0'; +-- tx_end_dma_i <= '0'; +-- tx_dwen_dma_i <= '0'; +-- tx_req_dma_i <= '0'; @@ -507,47 +504,50 @@ THE_TX_ARBITER : ip_tx_arbiter ----------------------------------------------------------------------- THE_WB_TLC : wb_tlc port map( - RSTN => rst_n, - CLK_125 => clk_125_i, - wb_clk => CLK_WB_IN, - - rx_data => rx_data_i, - rx_st => rx_st_i, - rx_end => rx_end_i, - rx_dwen => rx_dwen_i, - rx_bar_hit => rx_bar_hit_i, - - wb_adr_o => bus_addr_i, - wb_dat_o => BUS_WDAT_OUT, - wb_we_o => BUS_WE_OUT, - wb_sel_o => BUS_SEL_OUT, - wb_stb_o => BUS_STB_OUT, - wb_cyc_o => BUS_CYC_OUT, - wb_lock_o => BUS_LOCK_OUT, - wb_ack_i => BUS_ACK_IN, - wb_dat_i => BUS_RDAT_IN, - - pd_cr => pd_cr_wb_i, - ph_cr => ph_cr_wb_i, - npd_cr => npd_cr_wb_i, - nph_cr => nph_cr_wb_i, - - tx_rdy => tx_rdy_wbm_i, - tx_val => tx_val_i, - tx_req => tx_req_wbm_i, - tx_data => tx_dout_wbm_i, - tx_st => tx_sop_wbm_i, - tx_end => tx_eop_wbm_i, - tx_dwen => tx_dwen_wbm_i, - - comp_id => requestor_id_i, - - f_full => rx_f_full_i, - f_empty => rx_f_empty_i, - - debug => debug_wb_tlc_i + RSTN_IN => rst_n, + CLK_125_IN => clk_125_i, + WB_CLK_IN => CLK_WB_IN, + + RX_DATA_IN => rx_data_i, + RX_ST_IN => rx_st_i, + RX_END_IN => rx_end_i, + RX_DWEN_IN => rx_dwen_i, + RX_BAR_HIT_IN => rx_bar_hit_i, + + WB_ADR_OUT => bus_addr_i, + WB_DAT_OUT => BUS_WDAT_OUT, + WB_WE_OUT => BUS_WE_OUT, + WB_SEL_OUT => BUS_SEL_OUT, + WB_STB_OUT => BUS_STB_OUT, + WB_CYC_OUT => BUS_CYC_OUT, + WB_LOCK_OUT => BUS_LOCK_OUT, + WB_ACK_IN => BUS_ACK_IN, + WB_DAT_IN => BUS_RDAT_IN, + + PD_CR_OUT => pd_cr_wb_i, + PH_CR_OUT => ph_cr_wb_i, + NPD_CR_OUT => npd_cr_wb_i, + NPH_CR_OUT => nph_cr_wb_i, + + TX_RDY_IN => tx_rdy_wbm_i, + TX_VAL_IN => tx_val_i, + TX_REQ_OUT => tx_req_wbm_i, + TX_DATA_OUT => tx_dout_wbm_i, + TX_ST_OUT => tx_sop_wbm_i, + TX_END_OUT => tx_eop_wbm_i, + TX_DWEN_OUT => tx_dwen_wbm_i, + + COMP_ID_IN => requestor_id_i, + + F_FULL_OUT => rx_f_full_i, + F_EMPTY_OUT => rx_f_empty_i, + + DEBUG_OUT => debug_wb_tlc_i ); + + + BUS_ADDR_OUT <= "00" & bus_addr_i(31 downto 2); diff --git a/design/wb_intf.vhd b/design/wb_intf.vhd new file mode 100644 index 0000000..5b57463 --- /dev/null +++ b/design/wb_intf.vhd @@ -0,0 +1,153 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + +entity wb_intf is + port( + RSTN_IN : in std_logic; + WB_CLK_IN : in std_logic; + + DIN : in std_logic_vector(63 downto 0); + DIN_BAR : in std_logic_vector(2 downto 0); + DIN_SOP : in std_logic; + DIN_EOP : in std_logic; + DIN_DWEN : in std_logic; + DIN_WRN : in std_logic; + DIN_REN : out std_logic; + TLP_AVAIL_IN : in std_logic; + + TRAN_ID_OUT : out std_logic_vector(23 downto 0); + TRAN_LENGTH_OUT : out std_logic_vector(9 downto 0); + TRAN_BE_OUT : out std_logic_vector(7 downto 0); + TRAN_ADDR_OUT : out std_logic_vector(4 downto 0); + TRAN_TC_OUT : out std_logic_vector(2 downto 0); + TRAN_ATTR_OUT : out std_logic_vector(1 downto 0); + + WB_DAT_OUT : out std_logic_vector(31 downto 0); + WB_ADR_OUT : out std_logic_vector(31 downto 0); + WB_WE_OUT : out std_logic; + WB_SEL_OUT : out std_logic_vector(3 downto 0); + WB_STB_OUT : out std_logic; + WB_CYC_OUT : out std_logic; + WB_LOCK_OUT : out std_logic; + WB_ACK_IN : in std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture wb_intfd_arch of wb_intf is + +type state_t is (IDLE, READ, ADR, DAT); +signal state : state_t; + +signal first_be : std_logic_vector(3 downto 0); +signal last_be : std_logic_vector(3 downto 0); + +signal wb_write_i : std_logic; +signal wb_cyc_i : std_logic; +signal wb_adr_i : std_logic_vector(31 downto 0); +signal wb_dat_i : std_logic_vector(31 downto 0); +signal wb_stb_i : std_logic; + +signal din_ren_i : std_logic; + +signal tran_length_i : std_logic_vector(9 downto 0); +signal tran_attr_i : std_logic_vector(1 downto 0); +signal tran_tc_i : std_logic_vector(2 downto 0); +signal tran_id_i : std_logic_vector(23 downto 0); +signal tran_addr_i : std_logic_vector(4 downto 0); +signal tran_be_i : std_logic_vector(7 downto 0); + +begin + +WB_SEL_OUT <= last_be(0) & last_be(1) & last_be(2) & last_be(3); +WB_WE_OUT <= wb_write_i; +WB_LOCK_OUT <= wb_cyc_i; +WB_CYC_OUT <= wb_cyc_i; +WB_ADR_OUT <= wb_adr_i; +WB_DAT_OUT <= wb_dat_i; +WB_STB_OUT <= wb_stb_i; + +DIN_REN <= din_ren_i; + +TRAN_LENGTH_OUT <= tran_length_i; +TRAN_ADDR_OUT <= tran_addr_i; +TRAN_ATTR_OUT <= tran_attr_i; +TRAN_TC_OUT <= tran_tc_i; +TRAN_ID_OUT <= tran_id_i; +TRAN_BE_OUT <= tran_be_i; + + THE_FSM : process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + if RSTN_IN = '0' then + state <= IDLE; + wb_cyc_i <= '0'; + wb_stb_i <= '0'; + wb_write_i <= '0'; + wb_dat_i <= (others => '0'); + wb_adr_i <= (others => '0'); + din_ren_i <= '0'; + tran_length_i <= (others => '0'); + tran_attr_i <= (others => '0'); + tran_tc_i <= (others => '0'); + tran_id_i <= (others => '0'); + first_be <= (others => '0'); + last_be <= (others => '0'); + else + tran_be_i <= first_be & last_be; + + case state is + when IDLE => + if TLP_AVAIL_IN = '1' then + din_ren_i <= '1'; + state <= READ; + end if; + when READ => + if DIN_SOP = '1' and din_ren_i = '1' then + state <= ADR; + wb_write_i <= DIN_WRN; + tran_length_i <= DIN(41 downto 32); + tran_attr_i <= DIN(45 downto 44); + tran_tc_i <= DIN(55 downto 53); + tran_id_i <= DIN(31 downto 8); + + if DIN(41 downto 32) = "0000000001" then + first_be <= DIN(3 downto 0); + last_be <= DIN(3 downto 0); + din_ren_i <= '0'; + else + first_be <= DIN(3 downto 0); + last_be <= DIN(7 downto 4); + din_ren_i <= '1'; + end if; + end if; + when ADR => + wb_adr_i <= x"00" & DIN(55 downto 32); + tran_addr_i <= DIN(38 downto 34); + wb_dat_i <= DIN(7 downto 0) & DIN(15 downto 8) & DIN(23 downto 16) & DIN(31 downto 24); + din_ren_i <= '0'; + state <= DAT; + when DAT => + wb_cyc_i <= '1'; + wb_stb_i <= '1'; + + if WB_ACK_IN = '1' then + state <= IDLE; --CLEAR; + wb_stb_i <= '0'; + wb_cyc_i <= '0'; + wb_write_i <= '0'; + end if; + end case; + end if; + end if; + end process; + + +end architecture; diff --git a/design/wb_tlc.vhd b/design/wb_tlc.vhd index 5217525..d1c4b26 100644 --- a/design/wb_tlc.vhd +++ b/design/wb_tlc.vhd @@ -21,14 +21,14 @@ entity wb_tlc is RX_BAR_HIT_IN : in std_logic_vector(6 downto 0); WB_ADR_OUT : out std_logic_vector(31 downto 0); - WB_DAT_OUT : out std_logic_vector(63 downto 0); + WB_DAT_OUT : out std_logic_vector(31 downto 0); WB_WE_OUT : out std_logic; - WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_SEL_OUT : out std_logic_vector(3 downto 0); WB_STB_OUT : out std_logic; WB_CYC_OUT : out std_logic; WB_LOCK_OUT : out std_logic; WB_ACK_IN : in std_logic; - WB_DAT_IN : in std_logic_vector(63 downto 0); + WB_DAT_IN : in std_logic_vector(31 downto 0); PD_CR_OUT : out std_logic; PH_CR_OUT : out std_logic; @@ -55,12 +55,14 @@ end entity; architecture wb_tlc_arch of wb_tlc is +signal reset_i : std_logic; +signal req_fifo_din : std_logic_vector(71 downto 0); +signal req_fifo_dout : std_logic_vector(71 downto 0); signal to_req_fifo_dout : std_logic_vector(63 downto 0); signal to_req_fifo_sop : std_logic; signal to_req_fifo_eop : std_logic; -signal to_req_fifo_bad : std_logic; signal to_req_fifo_dwen : std_logic; signal to_req_fifo_wrn : std_logic; signal to_req_fifo_wen : std_logic; @@ -71,12 +73,12 @@ signal from_req_fifo_sop : std_logic; signal from_req_fifo_eop : std_logic; signal from_req_fifo_wrn : std_logic; signal from_req_fifo_ren : std_logic; +signal from_req_fifo_dwen : std_logic; signal from_req_fifo_bar : std_logic_vector(2 downto 0); signal tlp_avail : std_logic; signal no_tlp_avail : std_logic; -signal read_data : std_logic_vector(31 downto 0); signal tran_len : std_logic_vector(9 downto 0); signal tran_id : std_logic_vector(23 downto 0); signal tran_be : std_logic_vector(7 downto 0); @@ -91,73 +93,113 @@ signal cmpl_dwen : std_logic; signal cmpl_wen : std_logic; signal ph_cr_wb : std_logic; +signal ph_cr : std_logic; signal encoded_bar_hit : std_logic_vector(2 downto 0); -signal debug_wb_intf : std_logic_vector(31 downto 0); -signal debug_wb_tlc_cpld : std_logic_vector(31 downto 0); -signal debug_wb_tlc_cpld_fifo : std_logic_vector(31 downto 0); signal wb_adr_out_i : std_logic_vector(31 downto 0); -signal wb_dat_out_i : std_logic_vector(63 downto 0); +signal wb_dat_out_i : std_logic_vector(31 downto 0); signal wb_we_out_i : std_logic; -signal wb_sel_out_i : std_logic_vector(7 downto 0); signal wb_stb_out_i : std_logic; signal wb_cyc_out_i : std_logic; -signal wb_lock_out_i : std_logic; -signal wb_read_i : std_logic; signal tx_data_out_i : std_logic_vector(63 downto 0); signal tx_st_out_i : std_logic; signal tx_end_out_i : std_logic; signal tx_dwen_out_i : std_logic; -signal tx_req_out_i : std_logic; + +type wb_state_t is (WB_IDLE, WB_READ, WB_ADR, WB_DAT); --, CLEAR); +signal wb_state : wb_state_t; + +signal rx_eop_p : std_logic; + signal cmpl_fifo_rden : std_logic; + signal cmpl_fifo_rden_p : std_logic; + signal cmpl_fifo_eop : std_logic; + signal tx_eop_i : std_logic; + signal tx_eop_p : std_logic; + signal cmpl_fifo_empty : std_logic; + signal tx_st_p : std_logic; + signal tx_st_i : std_logic; + signal cmpl_fifo_wen : std_logic; + signal cmpl_fifo_real_rden : std_logic; + signal cmpl_fifo_in : std_logic_vector(66 downto 0); + signal cmpl_fifo_out : std_logic_vector(66 downto 0); + signal cmpl_wen_p : std_logic; + + + type cpld_state_t is (CPLD_IDLE, CPLD_ACK, CPLD_DAT); + signal cpld_state : cpld_state_t; + signal byte_cnt : unsigned(11 downto 0); + signal la : std_logic_vector( 7 downto 0); + + signal din_p : std_logic_vector(31 downto 0); + signal tran_id_p : std_logic_vector(23 downto 0); + begin + reset_i <= not RSTN_IN; + ----------------------------------------------------------------------- -- TLP Decoder ----------------------------------------------------------------------- - encoded_bar_hit <= "000" when RX_BAR_HIT_IN = "0000001" else - "001" when RX_BAR_HIT_IN = "0000010" else - "010" when RX_BAR_HIT_IN = "0000100" else - "011" when RX_BAR_HIT_IN = "0001000" else - "100" when RX_BAR_HIT_IN = "0010000" else - "101" when RX_BAR_HIT_IN = "0100000" else - "110" when RX_BAR_HIT_IN = "1000000" else + encoded_bar_hit <= "000" when RX_BAR_HIT_IN(0) = '1' else + "001" when RX_BAR_HIT_IN(1) = '1' else + "010" when RX_BAR_HIT_IN(2) = '1' else + "011" when RX_BAR_HIT_IN(3) = '1' else + "100" when RX_BAR_HIT_IN(4) = '1' else + "101" when RX_BAR_HIT_IN(5) = '1' else + "110" when RX_BAR_HIT_IN(6) = '1' else "111"; - THE_DECODER : wb_tlc_dec - port map( - RSTN_IN => RSTN_IN, - CLK_125_IN => CLK_125_IN, - - RX_DIN_IN - RX_SOP_IN => RX_DATA_IN, - RX_EOP_IN => RX_EOP_IN, - RX_DWEN_IN => RX_DWEN_IN, - RX_BAR_HIT_IN => encoded_bar_hit, - - FIFO_DOUT_OUT => to_req_fifo_dout, - FIFO_SOP_OUT => to_req_fifo_sop, - FIFO_EOP_OUT => to_req_fifo_eop, - FIFO_DWEN_OUT => to_req_fifo_dwen, - FIFO_WRN_OUT => to_req_fifo_wrn, - FIFO_WEN_OUT => to_req_fifo_wen, - FIFO_BAR_OUT => to_req_fifo_bar - ); + PROC_TLC_DECODE : process(CLK_125_IN) + variable drop_var : std_logic := '1'; + begin + if rising_edge(CLK_125_IN) then + drop_var := '1'; + to_req_fifo_bar <= encoded_bar_hit; + to_req_fifo_eop <= RX_END_IN; --rx_eop_p; + to_req_fifo_dout <= RX_DATA_IN; --rx_din_p; + to_req_fifo_sop <= RX_ST_IN; --rx_sop_p; + to_req_fifo_dwen <= RX_DWEN_IN; --rx_dwen_p; + + rx_eop_p <= RX_END_IN; + + if RX_ST_IN = '1' then + if encoded_bar_hit = "000" or encoded_bar_hit = "001" then + if RX_DATA_IN(63 downto 62) = "00" and RX_DATA_IN(60 downto 56) = "00000" then --MRd + to_req_fifo_wrn <= '0'; + drop_var := '0'; + elsif RX_DATA_IN(63 downto 62) = "01" and RX_DATA_IN(60 downto 56) = "00000" then --MWr + to_req_fifo_wrn <= '1'; + drop_var := '0'; + else + drop_var := '1'; + end if; + end if; + end if; + + if RX_ST_IN = '1' then + to_req_fifo_wen <= not drop_var; + elsif rx_eop_p = '1' then + to_req_fifo_wen <= '0'; + end if; + + end if; + end process; ----------------------------------------------------------------------- -- Request FiFo ----------------------------------------------------------------------- - req_fifo_din <= '0' & encoded_bar_hit & to_req_fifo_dwen & to_req_fifo_wrn & to_req_fifo_eop + req_fifo_din <= '0' & to_req_fifo_bar & to_req_fifo_dwen & to_req_fifo_wrn & to_req_fifo_eop & to_req_fifo_sop & to_req_fifo_dout; - tlp_avail <= no_tlp_avail; + tlp_avail <= not no_tlp_avail; from_req_fifo_dout <= req_fifo_dout(63 downto 0); from_req_fifo_sop <= req_fifo_dout(64); @@ -169,13 +211,13 @@ begin THE_REQ_FIFO : fifo_72x512 port map( - Data => req_fifo_din + Data => req_fifo_din, WrClock => CLK_125_IN, RdClock => WB_CLK_IN, WrEn => to_req_fifo_wen, RdEn => from_req_fifo_ren, - Reset => RSTN_IN, - RPReset => RSTN_IN, + Reset => reset_i, + RPReset => '0', Q => req_fifo_dout, Empty => no_tlp_avail, Full => open, @@ -188,130 +230,388 @@ begin ----------------------------------------------------------------------- ph_cr_wb <= from_req_fifo_sop and from_req_fifo_wrn; PD_CR_OUT <= ph_cr; + PH_CR_OUT <= ph_cr; - THE_TLP_CR : wb_tlc_cr + THE_TLP_CR : pulse_sync port map( - CLK_125_IN => CLK_125_IN, - WB_CLK_IN => WB_CLK_IN, - RSTN_IN => RSTN_IN, - - CR_WB_IN => ph_cr_wb, - CR_125_OUT => ph_cr + CLK_A_IN => WB_CLK_IN, + RESET_A_IN => '0', + PULSE_A_IN => ph_cr_wb, + CLK_B_IN => CLK_125_IN, + RESET_B_IN => '0', + PULSE_B_OUT => ph_cr ); ----------------------------------------------------------------------- -- Wishbone Interface ----------------------------------------------------------------------- - THE_WB_INTF : wb_intf - port map( - RSTN_IN => RSTN_IN, - WB_CLK_IN => WB_CLK_IN, - - DIN => from_req_fifo_dout, - DIN_BAR => from_req_fifo_bar, - DIN_SOP => from_req_fifo_sop, - DIN_EOP => from_req_fifo_eop, - DIN_DWEN => from_req_fifo_dwen, - DIN_WRN => from_req_fifo_wrn, - DIN_REN => from_req_fifo_ren, - TLP_AVAIL_IN => tlp_avail, - - TRAN_ID_OUT => tran_id, - TRAN_LENGTH_OUT => tran_len, - TRAN_BE_OUT => tran_be, - TRAN_ADDR_OUT => tran_addr, - TRAN_TC_OUT => tran_tc, - TRAN_ATTR_OUT => tran_attr, - - WB_DAT_OUT => wb_dat_out_i, - WB_ADR_OUT => wb_adr_out_i, - WB_WE_OUT => wb_we_out_i, - WB_SEL_OUT => wb_sel_out_i, - WB_STB_OUT => wb_stb_out_i, - WB_CYC_OUT => wb_cyc_out_i, - WB_LOCK_OUT => wb_lock_out_i, - WB_ACK_IN => WB_ACK_IN, - DEBUG_OUT => debug_wb_intf - ); + PROC_WISHBONE_INTERFACE : process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + if reset_i = '1' then + wb_state <= WB_IDLE; + wb_cyc_out_i <= '0'; + wb_stb_out_i <= '0'; + from_req_fifo_ren <= '0'; + + else + case wb_state is + when WB_IDLE => + if tlp_avail = '1' then + from_req_fifo_ren <= '1'; + wb_state <= WB_READ; + end if; + when WB_READ => + if from_req_fifo_sop = '1' and from_req_fifo_ren = '1' then + wb_state <= WB_ADR; + wb_we_out_i <= from_req_fifo_wrn; + tran_len <= from_req_fifo_dout(41 downto 32); + tran_attr <= from_req_fifo_dout(45 downto 44); + tran_tc <= from_req_fifo_dout(55 downto 53); + tran_id <= from_req_fifo_dout(31 downto 8); + + if from_req_fifo_dout(41 downto 32) = "0000000001" then + tran_be <= from_req_fifo_dout(3 downto 0) & from_req_fifo_dout(3 downto 0); + from_req_fifo_ren <= '0'; + else + tran_be <= from_req_fifo_dout(3 downto 0) & from_req_fifo_dout(7 downto 4); + from_req_fifo_ren <= '1'; + end if; + end if; + when WB_ADR => + wb_adr_out_i <= x"00" & from_req_fifo_dout(55 downto 32); + tran_addr <= from_req_fifo_dout(38 downto 34); + wb_dat_out_i <= from_req_fifo_dout(7 downto 0) & from_req_fifo_dout(15 downto 8) + & from_req_fifo_dout(23 downto 16) & from_req_fifo_dout(31 downto 24); + from_req_fifo_ren <= '0'; + + wb_state <= WB_DAT; + when WB_DAT => + wb_cyc_out_i <= '1'; + wb_stb_out_i <= '1'; + if WB_ACK_IN = '1' then + wb_state <= WB_IDLE; --CLEAR; + wb_stb_out_i <= '0'; + wb_cyc_out_i <= '0'; +-- wb_we_out_i <= '0'; + end if; + end case; + end if; + end if; + end process; + + WB_SEL_OUT <= tran_be(0) & tran_be(1) & tran_be(2) & tran_be(3); WB_DAT_OUT <= wb_dat_out_i; WB_ADR_OUT <= wb_adr_out_i; WB_WE_OUT <= wb_we_out_i; - WB_SEL_OUT <= wb_sel_out_i; WB_STB_OUT <= wb_stb_out_i; WB_CYC_OUT <= wb_cyc_out_i; - WB_LOCK_OUT<= wb_lock_out_i; + WB_LOCK_OUT<= wb_cyc_out_i; ----------------------------------------------------------------------- -- TLC Completion Generation ----------------------------------------------------------------------- - read_data <= WB_DAT_IN(7 downto 0) & WB_DAT_IN(15 downto 8) & WB_DAT_IN(23 downto 16) & WB_DAT_IN(31 downto 24); - wb_read_i <= wb_stb_out_i and not wb_we_out_i; + PROC_TLC_CPLD_WRITE_DATA : process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + if reset_i = '1' then + cpld_state <= CPLD_IDLE; + cmpl_wen <= '0'; + cmpl_eop <= '0'; + cmpl_dwen <= '0'; + else + din_p <= WB_DAT_IN(7 downto 0) & WB_DAT_IN(15 downto 8) + & WB_DAT_IN(23 downto 16) & WB_DAT_IN(31 downto 24); + tran_id_p <= tran_id; + + case cpld_state is + when CPLD_IDLE => + cmpl_d(63 downto 48) <= x"4A" & '0' & tran_tc & x"0"; + cmpl_d(47 downto 32) <= "00" & tran_attr & "00" & tran_len; + cmpl_d(31 downto 16) <= COMP_ID_IN; + cmpl_d(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + cmpl_wen <= '0'; + cmpl_eop <= '0'; + cmpl_dwen <= '0'; + if wb_stb_out_i = '1' and wb_we_out_i = '0' then + cpld_state <= CPLD_ACK; + end if; + when CPLD_ACK => + cmpl_d(63 downto 48) <= x"4A" & '0' & tran_tc & x"0"; + cmpl_d(47 downto 32) <= "00" & tran_attr & "00" & tran_len; + cmpl_d(31 downto 16) <= COMP_ID_IN; + cmpl_d(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + if WB_ACK_IN = '1' then + cmpl_sop <= '1'; + cmpl_wen <= '1'; + cpld_state <= CPLD_DAT; + end if; + when CPLD_DAT => + cmpl_d(63 downto 32) <= tran_id_p & la; + cmpl_d(31 downto 0) <= din_p; + cmpl_sop <= '0'; + cmpl_eop <= '1'; + cmpl_wen <= '0'; + cpld_state <= CPLD_IDLE; + end case; + end if; + end if; + end process; - THE_TLC_COMPLETER : wb_tlc_cpld - port( - RSTN_IN => RSTN_IN, - WB_CLK_IN => WB_CLK_IN, - - DATA_IN => read_data, - SEL_IN => WB_SEL_OUT, - READ_IN => wb_read_i, - VALID_IN => WB_ACK_IN, - - TRAN_ID_IN => tran_id, - TRAN_LENGTH_IN => tran_len, - TRAN_BE_IN => tran_be, - TRAN_ADDR_IN => tran_addr, - TRAN_TC_IN => tran_tc, - TRAN_ATTR_IN => tran_attr, - - COMP_ID_IN => COMP_ID_IN, - DOUT_DATA_OUT => cmpl_d, - DOUT_SOP_OUT => cmpl_sop, - DOUT_EOP_OUT => cmpl_eop, - DOUT_DWEN_OUT => cmpl_dwen, - DOUT_WEN_OUT => cmpl_wen, +----------------------------------------------------------------------- +-- Calculate correct byte length +----------------------------------------------------------------------- + THE_CPLD_BYTE_CNT_PROC : process(WB_CLK_IN) + variable cnt_be_leading_0 : unsigned(1 downto 0); + variable cnt_be_trailing_0 : unsigned(1 downto 0); + begin + if rising_edge(WB_CLK_IN) then + if tran_be(4) = '1' then + cnt_be_trailing_0 := to_unsigned(0,2); + elsif tran_be(5) = '1' then + cnt_be_trailing_0 := to_unsigned(1,2); + elsif tran_be(6) = '1' then + cnt_be_trailing_0 := to_unsigned(2,2); + elsif tran_be(7) = '1' then + cnt_be_trailing_0 := to_unsigned(3,2); + else --if tran_be(7 downto 4) = "0000" then + cnt_be_trailing_0 := to_unsigned(0,2); + end if; + + if tran_len(9 downto 0) = "0000000001" then + if tran_be(7) = '1' then + cnt_be_leading_0 := to_unsigned(0,2); + elsif tran_be(6) = '1' then + cnt_be_leading_0 := to_unsigned(1,2); + elsif tran_be(5) = '1' then + cnt_be_leading_0 := to_unsigned(2,2); + else --if tran_be(7 downto 4) = "0000" then + cnt_be_leading_0 := to_unsigned(3,2); + end if; + else + if tran_be(3) = '1' then + cnt_be_leading_0 := to_unsigned(0,2); + elsif tran_be(2) = '1' then + cnt_be_leading_0 := to_unsigned(1,2); + elsif tran_be(1) = '1' then + cnt_be_leading_0 := to_unsigned(2,2); + else --if tran_be(3 downto 0) = "0001" then + cnt_be_leading_0 := to_unsigned(3,2); + end if; + end if; + + byte_cnt <= unsigned(tran_len)*to_unsigned(4,2) - cnt_be_leading_0 - cnt_be_trailing_0; + la <= '0' & tran_addr & std_logic_vector(cnt_be_trailing_0); + + end if; + end process; - DEBUG_OUT => debug_wb_tlc_cpld - ); ----------------------------------------------------------------------- -- TLC Completion FiFo ----------------------------------------------------------------------- - NPH_CR_OUT <= tx_st_out_i and TX_VAL_IN; + NPH_CR_OUT <= tx_st_out_i and TX_VAL_IN; TX_DATA_OUT <= tx_data_out_i; TX_ST_OUT <= tx_st_out_i; TX_END_OUT <= tx_end_out_i; TX_DWEN_OUT <= tx_dwen_out_i; - TX_REQ_OUT <= tx_req_out_i; - - THE_TLC_CPLD_FIFO : wb_tlc_cpld_fifo - port map( - RSTN_IN => RSTN_IN, - WB_CLK_IN => WB_CLK_IN, - CLK_125_IN => CLK_125_IN, - - DIN_DATA_IN => cmpl_d, - DIN_SOP_IN => cmpl_sop, - DIN_EOP_IN => cmpl_eop, - DIN_DWEN_IN => cmpl_dwen, - DIN_WEN_IN => cmpl_wen, - - TX_DATA_OUT => tx_data_out_i, - TX_ST_OUT => tx_st_out_i, - TX_END_OUT => tx_end_out_i, - TX_DWEN_OUT => tx_dwen_out_i, - TX_REQ_OUT => tx_req_out_i, - TX_RDY_IN => TX_RDY_IN, - TX_VAL_IN => TX_VAL_IN, - - DEBUG_OUT => debug_wb_tlc_cpld_fifo + TX_REQ_OUT <= not cmpl_fifo_empty; + + + cmpl_fifo_in <= cmpl_dwen & cmpl_sop & cmpl_eop & cmpl_d; + cmpl_fifo_wen <= cmpl_wen or cmpl_wen_p; + cmpl_fifo_eop <= cmpl_fifo_out(64); + cmpl_fifo_real_rden <= cmpl_fifo_rden and TX_VAL_IN; + + tx_st_out_i <= tx_st_i and not tx_st_p; + tx_end_out_i <= tx_eop_i and not tx_eop_p; + + +--FIFO is written with 1 too many to absorb latency from eop detect to rden + process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + cmpl_wen_p <= cmpl_wen; + end if; + end process; + + THE_CPLD_FIFO : cpld_fifo + port map ( + Data => cmpl_fifo_in, + WrClock => WB_CLK_IN, + RdClock => CLK_125_IN, + WrEn => cmpl_fifo_wen, + RdEn => cmpl_fifo_real_rden, + Reset => reset_i, + RPReset => '0', + Q => cmpl_fifo_out, + Empty => open, + Full => open, + AlmostEmpty => cmpl_fifo_empty, + AlmostFull => open ); + PROC_CPLD_FIFO_READ : process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + if TX_VAL_IN = '1' then + tx_eop_p <= tx_eop_i; + tx_st_p <= tx_st_i; + tx_data_out_i <= cmpl_fifo_out(63 downto 0); + tx_eop_i <= cmpl_fifo_out(64); + tx_st_i <= cmpl_fifo_out(65); + tx_dwen_out_i <= cmpl_fifo_out(66); + end if; + + if reset_i = '1' then + cmpl_fifo_rden <= '0'; + elsif TX_RDY_IN = '1' and cmpl_fifo_rden = '0' and TX_VAL_IN = '1' then + cmpl_fifo_rden <= '1'; + elsif cmpl_fifo_eop = '1' and cmpl_fifo_rden_p = '1' and TX_VAL_IN = '1' then + cmpl_fifo_rden <= '0'; + end if; + + if reset_i = '1' then + cmpl_fifo_rden_p <= '0'; + elsif TX_VAL_IN = '1' then + cmpl_fifo_rden_p <= cmpl_fifo_rden; + end if; + end if; + end process; + + + +----------------------------------------------------------------------- +-- Debug +----------------------------------------------------------------------- +DEBUG_OUT(2 downto 0) <= to_req_fifo_bar; +DEBUG_OUT(3) <= to_req_fifo_sop; +DEBUG_OUT(4) <= to_req_fifo_eop; + + +end architecture; + + +----------------------------------------------------------------------- +-- Old Entities +----------------------------------------------------------------------- -end architecture; \ No newline at end of file +-- THE_TLC_COMPLETER : wb_tlc_cpld +-- port map( +-- RSTN_IN => RSTN_IN, +-- WB_CLK_IN => WB_CLK_IN, +-- +-- DATA_IN => read_data, +-- READ_IN => wb_read_i, +-- VALID_IN => WB_ACK_IN, +-- +-- TRAN_ID_IN => tran_id, +-- TRAN_LENGTH_IN => tran_len, +-- TRAN_BE_IN => tran_be, +-- TRAN_ADDR_IN => tran_addr, +-- TRAN_TC_IN => tran_tc, +-- TRAN_ATTR_IN => tran_attr, +-- +-- COMP_ID_IN => COMP_ID_IN, +-- DOUT_DATA_OUT => cmpl_d, +-- DOUT_SOP_OUT => cmpl_sop, +-- DOUT_EOP_OUT => cmpl_eop, +-- DOUT_DWEN_OUT => cmpl_dwen, +-- DOUT_WEN_OUT => cmpl_wen, +-- +-- DEBUG_OUT => debug_wb_tlc_cpld +-- ); + + +-- THE_TLP_CR : wb_tlc_cr +-- port map( +-- CLK_125_IN => CLK_125_IN, +-- WB_CLK_IN => WB_CLK_IN, +-- RSTN_IN => RSTN_IN, +-- +-- CR_WB_IN => ph_cr_wb, +-- CR_125_OUT => ph_cr +-- ); + + +-- THE_WB_INTF : wb_intf +-- port map( +-- RSTN_IN => RSTN_IN, +-- WB_CLK_IN => WB_CLK_IN, +-- +-- DIN => from_req_fifo_dout, +-- DIN_BAR => from_req_fifo_bar, +-- DIN_SOP => from_req_fifo_sop, +-- DIN_EOP => from_req_fifo_eop, +-- DIN_DWEN => from_req_fifo_dwen, +-- DIN_WRN => from_req_fifo_wrn, +-- DIN_REN => from_req_fifo_ren, +-- TLP_AVAIL_IN => tlp_avail, +-- +-- TRAN_ID_OUT => tran_id, +-- TRAN_LENGTH_OUT => tran_len, +-- TRAN_BE_OUT => tran_be, +-- TRAN_ADDR_OUT => tran_addr, +-- TRAN_TC_OUT => tran_tc, +-- TRAN_ATTR_OUT => tran_attr, +-- +-- WB_DAT_OUT => wb_dat_out_i, +-- WB_ADR_OUT => wb_adr_out_i, +-- WB_WE_OUT => wb_we_out_i, +-- WB_SEL_OUT => wb_sel_out_i, +-- WB_STB_OUT => wb_stb_out_i, +-- WB_CYC_OUT => wb_cyc_out_i, +-- WB_LOCK_OUT => wb_lock_out_i, +-- WB_ACK_IN => WB_ACK_IN, +-- DEBUG_OUT => debug_wb_intf +-- ); + + +-- THE_TLC_CPLD_FIFO : wb_tlc_cpld_fifo +-- port map( +-- RSTN_IN => RSTN_IN, +-- WB_CLK_IN => WB_CLK_IN, +-- CLK_125_IN => CLK_125_IN, +-- +-- DIN_DATA_IN => cmpl_d, +-- DIN_SOP_IN => cmpl_sop, +-- DIN_EOP_IN => cmpl_eop, +-- DIN_DWEN_IN => cmpl_dwen, +-- DIN_WEN_IN => cmpl_wen, +-- +-- TX_DATA_OUT => tx_data_out_i, +-- TX_ST_OUT => tx_st_out_i, +-- TX_END_OUT => tx_end_out_i, +-- TX_DWEN_OUT => tx_dwen_out_i, +-- TX_REQ_OUT => tx_req_out_i, +-- TX_RDY_IN => TX_RDY_IN, +-- TX_VAL_IN => TX_VAL_IN, +-- +-- DEBUG_OUT => debug_wb_tlc_cpld_fifo +-- ); + +-- THE_DECODER : wb_tlc_dec +-- port map( +-- RSTN_IN => RSTN_IN, +-- CLK_125_IN => CLK_125_IN, +-- +-- RX_DIN_IN => RX_DATA_IN, +-- RX_SOP_IN => RX_ST_IN, +-- RX_EOP_IN => RX_END_IN, +-- RX_DWEN_IN => RX_DWEN_IN, +-- RX_BAR_HIT_IN => encoded_bar_hit, +-- +-- FIFO_DOUT_OUT => to_req_fifo_dout, +-- FIFO_SOP_OUT => to_req_fifo_sop, +-- FIFO_EOP_OUT => to_req_fifo_eop, +-- FIFO_DWEN_OUT => to_req_fifo_dwen, +-- FIFO_WRN_OUT => to_req_fifo_wrn, +-- FIFO_WEN_OUT => to_req_fifo_wen, +-- FIFO_BAR_OUT => to_req_fifo_bar +-- ); \ No newline at end of file diff --git a/design/wb_tlc_cpld.vhd b/design/wb_tlc_cpld.vhd new file mode 100644 index 0000000..f462e4d --- /dev/null +++ b/design/wb_tlc_cpld.vhd @@ -0,0 +1,150 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + +entity wb_tlc_cpld is + port( + WB_CLK_IN : in std_logic; + RSTN_IN : in std_logic; + + DATA_IN : in std_logic_vector(31 downto 0); + READ_IN : in std_logic; + VALID_IN : in std_logic; + + TRAN_ID_IN : in std_logic_vector(23 downto 0); + TRAN_LENGTH_IN : in std_logic_vector(9 downto 0); + TRAN_BE_IN : in std_logic_vector(7 downto 0); + TRAN_ADDR_IN : in std_logic_vector(4 downto 0); + TRAN_TC_IN : in std_logic_vector(2 downto 0); + TRAN_ATTR_IN : in std_logic_vector(1 downto 0); + + COMP_ID_IN : in std_logic_vector(15 downto 0); + DOUT_DATA_OUT : out std_logic_vector(63 downto 0); + DOUT_SOP_OUT : out std_logic; + DOUT_EOP_OUT : out std_logic; + DOUT_DWEN_OUT : out std_logic; + DOUT_WEN_OUT : out std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture wb_tlc_cpld_arch of wb_tlc_cpld is + +type state_t is (IDLE, ACK, DAT); +signal state : state_t; +signal byte_cnt : unsigned(11 downto 0); +signal dout : std_logic_vector(63 downto 0); +signal din_p : std_logic_vector(31 downto 0); +signal la : std_logic_vector( 7 downto 0); +signal tran_id_p : std_logic_vector(23 downto 0); + + +begin + +----------------------------------------------------------------------- +-- State Machine +----------------------------------------------------------------------- + PROC_WRITE_DATA : process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + if RSTN_IN = '0' then + state <= IDLE; + DOUT_WEN_OUT <= '0'; + DOUT_EOP_OUT <= '0'; + DOUT_DWEN_OUT <= '0'; + else + din_p <= DATA_IN; + tran_id_p <= TRAN_ID_IN; + + case state is + when IDLE => + DOUT_DATA_OUT(63 downto 48) <= x"4A" & '0' & TRAN_TC_IN & x"0"; + DOUT_DATA_OUT(47 downto 32) <= "00" & TRAN_ATTR_IN & "00" & TRAN_LENGTH_IN; + DOUT_DATA_OUT(31 downto 16) <= COMP_ID_IN; + DOUT_DATA_OUT(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + DOUT_WEN_OUT <= '0'; + DOUT_EOP_OUT <= '0'; + DOUT_DWEN_OUT <= '0'; + if READ_IN = '1' then + state <= ACK; + end if; + when ACK => + DOUT_DATA_OUT(63 downto 48) <= x"4A" & '0' & TRAN_TC_IN & x"0"; + DOUT_DATA_OUT(47 downto 32) <= "00" & TRAN_ATTR_IN & "00" & TRAN_LENGTH_IN; + DOUT_DATA_OUT(31 downto 16) <= COMP_ID_IN; + DOUT_DATA_OUT(15 downto 0) <= x"0" & std_logic_vector(byte_cnt); + if VALID_IN = '1' then + DOUT_SOP_OUT <= '1'; + DOUT_WEN_OUT <= '1'; + state <= DAT; + end if; + when DAT => + DOUT_DATA_OUT(63 downto 32) <= tran_id_p & la; + DOUT_DATA_OUT(31 downto 0) <= din_p; + DOUT_SOP_OUT <= '0'; + DOUT_EOP_OUT <= '1'; + DOUT_DWEN_OUT <= '0'; + state <= IDLE; + end case; + end if; + end if; + end process; + + +----------------------------------------------------------------------- +-- Calculate correct byte length +----------------------------------------------------------------------- + THE_BYTE_CNT_PROC : process(WB_CLK_IN) + variable cnt_be_leading_0 : unsigned(1 downto 0); + variable cnt_be_trailing_0 : unsigned(1 downto 0); + begin + if rising_edge(WB_CLK_IN) then + if TRAN_BE_IN(4) = '1' then + cnt_be_trailing_0 := to_unsigned(0,2); + elsif TRAN_BE_IN(5) = '1' then + cnt_be_trailing_0 := to_unsigned(1,2); + elsif TRAN_BE_IN(6) = '1' then + cnt_be_trailing_0 := to_unsigned(2,2); + elsif TRAN_BE_IN(7) = '1' then + cnt_be_trailing_0 := to_unsigned(3,2); + else --if TRAN_BE_IN(7 downto 4) = "0000" then + cnt_be_trailing_0 := to_unsigned(0,2); + end if; + + if TRAN_LENGTH_IN(9 downto 0) = "0000000001" then + if TRAN_BE_IN(7) = '1' then + cnt_be_leading_0 := to_unsigned(0,2); + elsif TRAN_BE_IN(6) = '1' then + cnt_be_leading_0 := to_unsigned(1,2); + elsif TRAN_BE_IN(5) = '1' then + cnt_be_leading_0 := to_unsigned(2,2); + else --if TRAN_BE_IN(7 downto 4) = "0000" then + cnt_be_leading_0 := to_unsigned(3,2); + end if; + else + if TRAN_BE_IN(3) = '1' then + cnt_be_leading_0 := to_unsigned(0,2); + elsif TRAN_BE_IN(2) = '1' then + cnt_be_leading_0 := to_unsigned(1,2); + elsif TRAN_BE_IN(1) = '1' then + cnt_be_leading_0 := to_unsigned(2,2); + else --if TRAN_BE_IN(3 downto 0) = "0001" then + cnt_be_leading_0 := to_unsigned(3,2); + end if; + end if; + + byte_cnt <= unsigned(TRAN_LENGTH_IN)*to_unsigned(4,2) - cnt_be_leading_0 - cnt_be_trailing_0; + la <= '0' & TRAN_ADDR_IN & std_logic_vector(cnt_be_trailing_0); + + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/design/wb_tlc_cpld_fifo.vhd b/design/wb_tlc_cpld_fifo.vhd new file mode 100644 index 0000000..5fd6a41 --- /dev/null +++ b/design/wb_tlc_cpld_fifo.vhd @@ -0,0 +1,122 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + +entity wb_tlc_cpld_fifo is + port( + WB_CLK_IN : in std_logic; + CLK_125_IN : in std_logic; + RSTN_IN : in std_logic; + + DIN_DATA_IN : in std_logic_vector(63 downto 0); + DIN_SOP_IN : in std_logic; + DIN_EOP_IN : in std_logic; + DIN_DWEN_IN : in std_logic; + DIN_WEN_IN : in std_logic; + + TX_DATA_OUT : out std_logic_vector(63 downto 0); + TX_ST_OUT : out std_logic; + TX_END_OUT : out std_logic; + TX_DWEN_OUT : out std_logic; + TX_REQ_OUT : out std_logic; + TX_RDY_IN : in std_logic; + TX_VAL_IN : in std_logic; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture wb_tlc_cpld_fifo_arch of wb_tlc_cpld_fifo is + + signal fifo_in : std_logic_vector(66 downto 0); + signal fifo_out : std_logic_vector(66 downto 0); + signal din_wen_p : std_logic; + signal fifo_out_p : std_logic_vector(66 downto 0); + signal tx_eop_p : std_logic; + signal tx_st_p : std_logic; + signal rden : std_logic; + signal rden_p : std_logic; + + signal fifo_wen : std_logic; + signal fifo_eop : std_logic; + signal fifo_rden : std_logic; + signal reset_i : std_logic; + signal empty : std_logic; + signal tx_eop_i : std_logic; + signal tx_st_i : std_logic; + +begin + + fifo_in <= DIN_DWEN_IN & DIN_SOP_IN & DIN_EOP_IN & DIN_DATA_IN; + fifo_wen <= DIN_WEN_IN or din_wen_p; + fifo_eop <= fifo_out(64); + fifo_rden <= rden and TX_VAL_IN; + + reset_i <= not RSTN_IN; + + TX_DATA_OUT <= fifo_out_p(63 downto 0); + tx_eop_i <= fifo_out_p(64); + tx_st_i <= fifo_out_p(65); + TX_DWEN_OUT <= fifo_out_p(66); + TX_REQ_OUT <= not empty; + TX_ST_OUT <= tx_st_i and not tx_st_p; + TX_END_OUT <= tx_eop_i and not tx_eop_p; + + +--FIFO is written with 1 too many to absorb latency from eop detect to rden + process(WB_CLK_IN) + begin + if rising_edge(WB_CLK_IN) then + din_wen_p <= DIN_WEN_IN; + end if; + end process; + + THE_FIFO : cpld_fifo + port map ( + Data => fifo_in, + WrClock => WB_CLK_IN, + RdClock => CLK_125_IN, + WrEn => fifo_wen, + RdEn => fifo_rden, + Reset => reset_i, + RPReset => '0', + Q => fifo_out, + Empty => open, + Full => open, + AlmostEmpty => empty, + AlmostFull => open + ); + + process(CLK_125_IN) + begin + if rising_edge(CLK_125_IN) then + if TX_VAL_IN = '1' then + tx_eop_p <= tx_eop_i; + tx_st_p <= tx_st_i; + fifo_out_p <= fifo_out; + end if; + + if reset_i = '1' then + rden <= '0'; + elsif TX_RDY_IN = '1' and rden = '0' and TX_VAL_IN = '1' then + rden <= '1'; + elsif fifo_eop = '1' and rden_p = '1' and TX_VAL_IN = '1' then + rden <= '0'; + end if; + + if reset_i = '1' then + rden_p <= '0'; + elsif TX_VAL_IN = '1' then + rden_p <= rden; + end if; + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/design/wb_tlc_dec.vhd b/design/wb_tlc_dec.vhd new file mode 100644 index 0000000..d2a8f0d --- /dev/null +++ b/design/wb_tlc_dec.vhd @@ -0,0 +1,77 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + + +entity wb_tlc_dec is + port( + RSTN_IN : in std_logic; + CLK_125_IN : in std_logic; + + RX_DIN_IN : in std_logic_vector(63 downto 0); + RX_SOP_IN : in std_logic; + RX_EOP_IN : in std_logic; + RX_DWEN_IN : in std_logic; + RX_BAR_HIT_IN : in std_logic_vector(2 downto 0); + FIFO_DOUT_OUT : out std_logic_vector(63 downto 0); + FIFO_SOP_OUT : out std_logic; + FIFO_EOP_OUT : out std_logic; + FIFO_DWEN_OUT : out std_logic; + FIFO_WRN_OUT : out std_logic; + FIFO_WEN_OUT : out std_logic; + FIFO_BAR_OUT : out std_logic_vector(2 downto 0) + ); +end entity; + + +architecture wb_tlc_dec_arch of wb_tlc_dec is + + signal rx_eop_p : std_logic; + + +begin + + process(CLK_125_IN) + variable drop_var : std_logic := '1'; + begin + if rising_edge(CLK_125_IN) then + drop_var := '1'; + FIFO_BAR_OUT <= RX_BAR_HIT_IN; + FIFO_EOP_OUT <= RX_EOP_IN; --rx_eop_p; + FIFO_DOUT_OUT <= RX_DIN_IN; --rx_din_p; + FIFO_SOP_OUT <= RX_SOP_IN; --rx_sop_p; + FIFO_DWEN_OUT <= RX_DWEN_IN; --rx_dwen_p; + + rx_eop_p <= RX_EOP_IN; + + if RX_SOP_IN = '1' then + if RX_BAR_HIT_IN = "000" or RX_BAR_HIT_IN = "001" then + if RX_DIN_IN(63 downto 62) = "00" and RX_DIN_IN(60 downto 56) = "00000" then --MRd + FIFO_WRN_OUT <= '0'; + drop_var := '0'; + elsif RX_DIN_IN(63 downto 62) = "01" and RX_DIN_IN(60 downto 56) = "00000" then --MWr + FIFO_WRN_OUT <= '1'; + drop_var := '0'; + else + drop_var := '1'; + end if; + end if; + end if; + + if RX_SOP_IN = '1' then + FIFO_WEN_OUT <= not drop_var; + elsif rx_eop_p = '1' then + FIFO_WEN_OUT <= '0'; + end if; + + end if; + end process; + + +end architecture; \ No newline at end of file diff --git a/pcie_components.vhd b/pcie_components.vhd index 6e390b1..9b96aca 100644 --- a/pcie_components.vhd +++ b/pcie_components.vhd @@ -22,9 +22,9 @@ component pci_core is --single access BUS_ADDR_OUT : out std_logic_vector(31 downto 0); - BUS_WDAT_OUT : out std_logic_vector(63 downto 0); - BUS_RDAT_IN : in std_logic_vector(63 downto 0); - BUS_SEL_OUT : out std_logic_vector(7 downto 0); + BUS_WDAT_OUT : out std_logic_vector(31 downto 0); + BUS_RDAT_IN : in std_logic_vector(31 downto 0); + BUS_SEL_OUT : out std_logic_vector(3 downto 0); BUS_WE_OUT : out std_logic; BUS_CYC_OUT : out std_logic; BUS_STB_OUT : out std_logic; @@ -82,50 +82,50 @@ end component; component dma_adapter is port( - RSTN : in std_logic; - CLK_125 : in std_logic; - ENABLE : in std_logic; - - WB_CLK_I : in std_logic; - WB_RST_I : in std_logic; - WB_DAT_I : in std_logic_vector(63 downto 0); - WB_ADR_I : in std_logic_vector(31 downto 0); - WB_CYC_I : in std_logic; - WB_LOCK_I : in std_logic; - WB_SEL_I : in std_logic_vector(7 downto 0); - WB_STB_I : in std_logic; - WB_WE_I : in std_logic; - WB_DAT_O : out std_logic_vector(63 downto 0); - WB_ACK_O : out std_logic; - WB_ERR_O : out std_logic; - WB_RTY_O : out std_logic; - - DMA_REQ : out std_logic_vector(1 downto 0); - DMA_ACK : in std_logic_vector(1 downto 0); - BURST_LEN : in std_logic_vector(15 downto 0); - ACTIVE_CH : in std_logic_vector(1 downto 0); - REQUESTOR_ID : in std_logic_vector(15 downto 0); - - TX_ST : out std_logic; - TX_END : out std_logic; - TX_DWEN : out std_logic; - TX_DATA : out std_logic_vector(63 downto 0); - TX_REQ : out std_logic; - TX_RDY : in std_logic; - TX_VAL : in std_logic; - TX_CA_PH : in std_logic_vector(8 downto 0); - TX_CA_PD : in std_logic_vector(12 downto 0); - TX_CA_NPH : in std_logic_vector(8 downto 0); - - RX_CR_CPLH : out std_logic; - RX_CR_CPLD : out std_logic_vector(7 downto 0); - UNEXP_CMPL : out std_logic; - RX_ST : in std_logic; - RX_END : in std_logic; - RX_DWEN : in std_logic; - RX_DATA : in std_logic_vector(63 downto 0); - - DEBUG : out std_logic_vector(31 downto 0) + rstn : in std_logic; + clk_125 : in std_logic; + enable : in std_logic; + + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_dat_i : in std_logic_vector(63 downto 0); + wb_adr_i : in std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_lock_i : in std_logic; + wb_sel_i : in std_logic_vector(7 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_dat_o : out std_logic_vector(63 downto 0); + wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_rty_o : out std_logic; + + dma_req : out std_logic_vector(1 downto 0); + dma_ack : in std_logic_vector(1 downto 0); + burst_len : in std_logic_vector(15 downto 0); + active_ch : in std_logic_vector(1 downto 0); + requestor_id : in std_logic_vector(15 downto 0); + + tx_st : out std_logic; + tx_end : out std_logic; + tx_dwen : out std_logic; + tx_data : out std_logic_vector(63 downto 0); + tx_req : out std_logic; + tx_rdy : in std_logic; + tx_val : in std_logic; + tx_ca_ph : in std_logic_vector(8 downto 0); + tx_ca_pd : in std_logic_vector(12 downto 0); + tx_ca_nph : in std_logic_vector(8 downto 0); + + rx_cr_cplh : out std_logic; + rx_cr_cpld : out std_logic_vector(7 downto 0); + unexp_cmpl : out std_logic; + rx_st : in std_logic; + rx_end : in std_logic; + rx_dwen : in std_logic; + rx_data : in std_logic_vector(63 downto 0); + + debug : out std_logic_vector(31 downto 0) ); end component; @@ -412,14 +412,14 @@ component wb_tlc is RX_BAR_HIT_IN : in std_logic_vector(6 downto 0); WB_ADR_OUT : out std_logic_vector(31 downto 0); - WB_DAT_OUT : out std_logic_vector(63 downto 0); + WB_DAT_OUT : out std_logic_vector(31 downto 0); WB_WE_OUT : out std_logic; - WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_SEL_OUT : out std_logic_vector(3 downto 0); WB_STB_OUT : out std_logic; WB_CYC_OUT : out std_logic; WB_LOCK_OUT : out std_logic; WB_ACK_IN : in std_logic; - WB_DAT_IN : in std_logic_vector(63 downto 0); + WB_DAT_IN : in std_logic_vector(31 downto 0); PD_CR_OUT : out std_logic; PH_CR_OUT : out std_logic; @@ -460,7 +460,7 @@ component wb_tlc_dec is FIFO_DWEN_OUT : out std_logic; FIFO_WRN_OUT : out std_logic; FIFO_WEN_OUT : out std_logic; - FIFO_BAR_OUT : out std_logic_vector(6 downto 0) + FIFO_BAR_OUT : out std_logic_vector(2 downto 0) ); end component; @@ -506,7 +506,7 @@ component wb_tlc_cr is CR_WB_IN : in std_logic; CR_125 : out std_logic ); -end component +end component; component wb_intf is @@ -533,7 +533,7 @@ component wb_intf is WB_DAT_OUT : out std_logic_vector(31 downto 0); WB_ADR_OUT : out std_logic_vector(31 downto 0); WB_WE_OUT : out std_logic; - WB_SEL_OUT : out std_logic_vector(7 downto 0); + WB_SEL_OUT : out std_logic_vector(3 downto 0); WB_STB_OUT : out std_logic; WB_CYC_OUT : out std_logic; WB_LOCK_OUT : out std_logic; @@ -549,7 +549,7 @@ component wb_tlc_cpld is RSTN_IN : in std_logic; DATA_IN : in std_logic_vector(31 downto 0); - SEL_IN : in std_logic_vector(7 downto 0); +-- SEL_IN : in std_logic_vector(7 downto 0); READ_IN : in std_logic; VALID_IN : in std_logic; @@ -590,13 +590,128 @@ component wb_tlc_cpld_fifo is TX_END_OUT : out std_logic; TX_DWEN_OUT : out std_logic; TX_REQ_OUT : out std_logic; - TX_RDY_OUT : out std_logic; - TX_VAL_OUT : out std_logic; + TX_RDY_IN : in std_logic; + TX_VAL_IN : in std_logic; + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; +component dma_rx_fifo is + port( + wb_clk : in std_logic; + clk_125 : in std_logic; + rstn : in std_logic; + + rx_st : in std_logic; + rx_end : in std_logic; + rx_dwen : in std_logic; + rx_data : in std_logic_vector(63 downto 0); + + active_ch : in std_logic_vector(1 downto 0); + ch1_rdy : out std_logic; + ch1_size : in std_logic_vector(11 downto 0); + ch1_rden : in std_logic; + ch1_pending : in std_logic; + ch_data : out std_logic_vector(63 downto 0); + ch_dv : out std_logic; + cplh_cr : out std_logic; + cpld_cr : out std_logic_vector(7 downto 0); + unexp_cmpl : out std_logic; + debug : out std_logic_vector(15 downto 0) + ); +end component; + + + + +component dma_tx_fifo is + port( + wb_clk : in std_logic; + clk_125 : in std_logic; + rstn : in std_logic; + + tx_st_in : in std_logic; + tx_end_in : in std_logic; + tx_dwen_in : in std_logic; + tx_dv : in std_logic; + tx_cv : in std_logic; + tx_data_in : in std_logic_vector(63 downto 0); + tx_pd_in : in std_logic_vector(4 downto 0); + tx_nph_in : in std_logic; + tx_ph_in : in std_logic; + + tx_st_out : out std_logic; + tx_end_out : out std_logic; + tx_dwen_out : out std_logic; + tx_nph_out : out std_logic; + tx_ph_out : out std_logic; + tx_data_out : out std_logic_vector(63 downto 0); + tx_pd_out : out std_logic_vector(3 downto 0); + empty : out std_logic; + full : out std_logic; + + credit_read : in std_logic; + data_read : in std_logic; + cr_avail : in std_logic; + tx_rdy : in std_logic; + tx_val : in std_logic; + tx_req : out std_logic; + + debug : out std_logic_vector(7 downto 0) + ); +end component; + + + +component dma_wbs is + port( + wb_clk_i : in std_logic; + wb_rst_i : in std_logic; + wb_dat_i : in std_logic_vector(63 downto 0); + wb_adr_i : in std_logic_vector(31 downto 0); + wb_cyc_i : in std_logic; + wb_lock_i : in std_logic; + wb_sel_i : in std_logic_vector(7 downto 0); + wb_stb_i : in std_logic; + wb_we_i : in std_logic; + wb_dat_o : out std_logic_vector(63 downto 0); + wb_ack_o : out std_logic; + wb_err_o : out std_logic; + wb_rty_o : out std_logic; + + dma_req : out std_logic_vector(1 downto 0); + dma_ack : in std_logic_vector(1 downto 0); + burst_len : in std_logic_vector(15 downto 0); + active_ch : in std_logic_vector(1 downto 0); + requestor_id : in std_logic_vector(15 downto 0); + enable : in std_logic; + + c_pd : out std_logic_vector(4 downto 0); + c_nph : out std_logic; + c_ph : out std_logic; + tx_dwen : out std_logic; + tx_nlfy : out std_logic; + tx_end : out std_logic; + tx_st : out std_logic; + tx_dv : out std_logic; + tx_cv : out std_logic; + tx_full : in std_logic; + tx_data : out std_logic_vector(63 downto 0); + + ch1_rdy : in std_logic; + ch1_size : out std_logic_vector(11 downto 0); + ch1_rden : out std_logic; + ch1_pending : out std_logic; + ch_data : in std_logic_vector(63 downto 0); + ch_dv : in std_logic; + + debug : out std_logic_vector(31 downto 0) + ); +end component; + + end package; diff --git a/pexor.prj b/pexor.prj index 5c99309..86adfdc 100644 --- a/pexor.prj +++ b/pexor.prj @@ -3,12 +3,15 @@ add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_func.vhd" + add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd" add_file -vhdl -lib work "pcie_components.vhd" add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../trbnet/basics/pulse_sync.vhd" add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../trbnet/basics/ram.vhd" @@ -51,9 +54,14 @@ add_file -vhdl -lib work "../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_logic.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_hub_ipu_logic.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint_hub.vhd" add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_endpoint.vhd" add_file -vhdl -lib work "../trbnet/special/trb_net_bridge_pcie_apl.vhd" +add_file -vhdl -lib work "../trbnet/basics/wide_adder_17x16.vhd" #Lattice SCM files add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd" @@ -85,8 +93,16 @@ add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_100_ex add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_100_ext.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out150.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out50_250.vhd" ############################# +add_file -vhdl -lib work "design/wb_tlc.vhd" +add_file -vhdl -lib work "design/wb_tlc_cpld.vhd" +add_file -vhdl -lib work "design/cores/cpld_fifo.vhd" +add_file -vhdl -lib work "../trbnet/lattice/scm/fifo_72x512.vhd" + + add_file -verilog "/d/sugar/lattice/diamond/1.1/cae_library/synthesis/verilog/scm.v" add_file -vhdl -lib work "design/pci_core.vhd" add_file -verilog "vcode/pci_exp_ddefines.v" @@ -94,19 +110,22 @@ add_file -verilog "vcode/pci_exp_params.v" add_file -verilog "vcode/ip_crpr_arb.v" add_file -verilog "vcode/ip_rx_crpr.v" add_file -verilog "vcode/ip_tx_arbiter.v" -add_file -verilog "vcode/wb_tlc_cpld_fifo.v" -add_file -verilog "vcode/wb_tlc_cpld.v" -add_file -verilog "vcode/wb_tlc_cr.v" -add_file -verilog "vcode/wb_tlc_dec.v" -add_file -verilog "vcode/wb_tlc_req_fifo.v" -add_file -verilog "vcode/wb_tlc.v" + add_file -verilog "vcode/UR_gen.v" + +add_file -verilog "vcode/tx_fifo.v" +add_file -verilog "vcode/tx_cpld_fifo.v" +add_file -verilog "vcode/rx_ram_dp.v" +add_file -verilog "vcode/dma_rx_fifo.v" +add_file -verilog "vcode/dma_tx_fifo.v" +add_file -verilog "vcode/dma_ca.v" +add_file -verilog "vcode/dma_ctrl.v" +add_file -verilog "vcode/dma_wbs.v" add_file -verilog "vcode/dma_adapter.v" -add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out150.vhd" -add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in100_out50_250.vhd" + + add_file -verilog "vcode/tlc_fifo.v" -add_file -verilog "vcode/wb_intf.v" -add_file -verilog "vcode/cpld_fifo.v" + add_file -verilog "vcode/pciexp2_bb.v" diff --git a/pexor.vhd b/pexor.vhd new file mode 100644 index 0000000..14484c3 --- /dev/null +++ b/pexor.vhd @@ -0,0 +1,471 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +USE IEEE.numeric_std.ALL; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.pcie_components.all; +use work.version.all; + +entity pexor is + generic( + NUM_LINKS : integer range 1 to 4 := 2 + ); + port( + --Clock and Reset + CLK_100 : in std_logic; + CLK_125 : in std_logic; + CLK_FPGA : in std_logic; + PE_RFCK : in std_logic; + NRES : in std_logic; + --SFP control + SFP1_LOS : in std_logic; + SFP2_LOS : in std_logic; + SFP3_LOS : in std_logic; + SFP4_LOS : in std_logic; + SFP1_TX_DIS : out std_logic; + SFP2_TX_DIS : out std_logic; + SFP3_TX_DIS : out std_logic; + SFP4_TX_DIS : out std_logic; + SFP1_MOD : in std_logic_vector(2 downto 0); + SFP2_MOD : in std_logic_vector(2 downto 0); + SFP3_MOD : in std_logic_vector(2 downto 0); + SFP4_MOD : in std_logic_vector(2 downto 0); + --Hexswitch + SWITCH_IN : in std_logic_vector(3 downto 0); + --Flash + SPI_D_IN : in std_logic; + SPI_SCK_OUT : out std_logic; + SPI_CS_OUT : out std_logic; + SPI_SI_OUT : out std_logic; + --Tempsens + SDA_TMP : inout std_logic; + SCK_TMP : out std_logic; + --PLL + PLLUSER : inout std_logic_vector(4 downto 1); + --Bus + ANT : inout std_logic_vector(26 downto 1); + --PCIe Control + PCIE_RX : in std_logic_vector(7 downto 0); + PCIE_TX : out std_logic_vector(7 downto 0); + X1 : in std_logic; + X4 : in std_logic; + XC : in std_logic; + PE_RST_N : in std_logic; + PE_SNCLK : inout std_logic; + PE_SMDAT : inout std_logic; + PE_WAKEN : inout std_logic; + --LED + LED : out std_logic_vector(7 downto 0); + --Test connector + TEST : inout std_logic_vector(31 downto 0) + + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of SFP1_LOS : signal is false; + attribute syn_useioff of SFP2_LOS : signal is false; + attribute syn_useioff of SFP3_LOS : signal is false; + attribute syn_useioff of SFP4_LOS : signal is false; + attribute syn_useioff of SFP1_TX_DIS : signal is false; + attribute syn_useioff of SFP2_TX_DIS : signal is false; + attribute syn_useioff of SFP3_TX_DIS : signal is false; + attribute syn_useioff of SFP4_TX_DIS : signal is false; + attribute syn_useioff of SWITCH_IN : signal is false; + attribute syn_useioff of NRES : signal is true; + attribute syn_useioff of SPI_D_IN : signal is true; + attribute syn_useioff of SPI_SCK_OUT : signal is true; + attribute syn_useioff of SPI_CS_OUT : signal is true; + attribute syn_useioff of SPI_SI_OUT : signal is true; + attribute syn_useioff of SDA_TMP : signal is true; + attribute syn_useioff of SCK_TMP : signal is true; + attribute syn_useioff of PLLUSER : signal is true; + attribute syn_useioff of ANT : signal is true; + attribute syn_useioff of X1 : signal is true; + attribute syn_useioff of X4 : signal is true; + attribute syn_useioff of XC : signal is true; + attribute syn_useioff of PE_RST_N : signal is true; + attribute syn_useioff of PE_SNCLK : signal is true; + attribute syn_useioff of PE_SMDAT : signal is true; + attribute syn_useioff of PE_WAKEN : signal is true; + attribute syn_useioff of LED : signal is true; + attribute syn_useioff of TEST : signal is true; + +end entity; + + +architecture pexor_arch of pexor is + + --Clock & Reset + signal clk_100_i : std_logic; + signal clk_125_i : std_logic; + signal clk_150_i : std_logic; + signal clk_en : std_logic; + signal pll_locked : std_logic; + signal sfp_ref_clk : std_logic; + + signal reset_i : std_logic; + signal reset_async : std_logic; + + --media interface to endpoint + signal med_data_in : std_logic_vector (NUM_LINKS*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (NUM_LINKS*3-1 downto 0); + signal med_dataready_in : std_logic_vector (NUM_LINKS-1 downto 0); + signal med_read_in : std_logic_vector (NUM_LINKS-1 downto 0); + signal med_data_out : std_logic_vector (NUM_LINKS*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (NUM_LINKS*3-1 downto 0); + signal med_dataready_out : std_logic_vector (NUM_LINKS-1 downto 0); + signal med_read_out : std_logic_vector (NUM_LINKS-1 downto 0); + signal med_stat_op : std_logic_vector (NUM_LINKS*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (NUM_LINKS*16-1 downto 0); + signal buf_med_ctrl_op : std_logic_vector (NUM_LINKS*16-1 downto 0); + signal med_stat_debug : std_logic_vector (NUM_LINKS*64-1 downto 0); + + signal bus_addr : std_logic_vector(31 downto 0); + signal bus_dout : std_logic_vector(31 downto 0); + signal bus_din : std_logic_vector(31 downto 0); + signal bus_sel : std_logic_vector(3 downto 0); + signal bus_we : std_logic; + signal bus_cyc : std_logic; + signal bus_stb : std_logic; + signal bus_lock : std_logic; + signal bus_ack : std_logic; + + + signal dma_addr : std_logic_vector(31 downto 0); + signal dma_dout : std_logic_vector(63 downto 0); + signal dma_din : std_logic_vector(63 downto 0); + signal dma_sel : std_logic_vector(7 downto 0); + signal dma_we : std_logic; + signal dma_cyc : std_logic; + signal dma_stb : std_logic; + signal dma_lock : std_logic; + signal dma_cti : std_logic_vector(2 downto 0); + signal dma_ack : std_logic; + signal dma_err : std_logic; + signal dma_retry : std_logic; + signal dma_eod : std_logic; + + signal debug_pci_core : std_logic_vector(31 downto 0); + signal send_network_reset : std_logic; + signal send_network_reset_falling : std_logic; + signal reset_i_trbnet : std_logic; + signal send_network_reset_last : std_logic; + + signal res_cnt : unsigned(4 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Clock & Reset state machine +--------------------------------------------------------------------------- + clk_en <= '1'; + + + gen_med_ctrl_op : for i in 0 to NUM_LINKS-1 generate + med_ctrl_op(16*i+15 downto 16*i) <= send_network_reset & "000000000000000"; + end generate; + + + process(clk_150_i) + begin + if rising_edge(clk_150_i) then + send_network_reset_last <= send_network_reset; + send_network_reset_falling <= not send_network_reset and send_network_reset_last; + end if; + end process; + + + THE_RESET_PROC : process(CLK_100) + begin + if rising_edge(CLK_100) then + if res_cnt(4) = '0' then + res_cnt <= res_cnt + to_unsigned(1,1); + reset_i <= '1'; + else + reset_i <= '0'; + end if; + end if; + end process; + + + THE_PLL : pll_in100_out150 + port map( + CLK => CLK_100, + CLKOP => clk_150_i, + CLKOS => clk_100_i, + LOCK => pll_locked + ); + + THE_RESET_HANDLER : trb_net_reset_handler + generic map( + RESET_DELAY => x"0EEE" + ) + port map( + CLEAR_IN => '0', -- reset input (high active, async) + CLEAR_N_IN => '1', -- reset input (low active, async) + CLK_IN => CLK_100, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_150_i, -- PLL/DLL remastered clock + PLL_LOCKED_IN => pll_locked, -- master PLL lock signal (async) + RESET_IN => '0', -- general reset signal (SYSCLK) + TRB_RESET_IN => send_network_reset_falling, -- TRBnet reset signal (SYSCLK) + CLEAR_OUT => reset_async, -- async reset out, USE WITH CARE! + RESET_OUT => reset_i_trbnet, -- synchronous reset out (SYSCLK) + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- Media Interface +--------------------------------------------------------------------------- + THE_MEDIA_INTERFACE_0: trb_net16_med_scm_sfp_gbe + generic map( + SERDES_NUM => 0, + EXT_CLOCK => c_YES, + USE_200_MHZ => c_NO + ) + port map( + CLK => CLK_100, -- raw 100MHz clock + SYSCLK => clk_150_i, -- 100MHz from PLL + RESET => reset_i_trbnet, + CLEAR => reset_async, + CLK_EN => clk_en, + --Internal Connection + MED_DATA_IN => med_data_out(15 downto 0), + MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0), + MED_DATAREADY_IN => med_dataready_out(0), + MED_READ_OUT => med_read_in(0), + MED_DATA_OUT => med_data_in(15 downto 0), + MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0), + MED_DATAREADY_OUT => med_dataready_in(0), + MED_READ_IN => med_read_out(0), + REFCLK2CORE_OUT => sfp_ref_clk, + --SFP Connection + SD_RXD_P_IN => open, -- ignore + SD_RXD_N_IN => open, -- ignore + SD_TXD_P_OUT => open, -- ignore + SD_TXD_N_OUT => open, -- ignore + SD_REFCLK_P_IN => open, -- ignore + SD_REFCLK_N_IN => open, -- ignore + SD_PRSNT_N_IN => SFP1_MOD(0), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) + SD_LOS_IN => SFP1_LOS, -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT => SFP1_TX_DIS, -- SFP disable + -- Status and control port + STAT_OP => med_stat_op(15 downto 0), + CTRL_OP => med_ctrl_op(15 downto 0), + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); + +-- THE_MEDIA_INTERFACE_1: trb_net16_med_scm_sfp_gbe +-- generic map( +-- SERDES_NUM => 0, +-- EXT_CLOCK => c_YES, +-- USE_200_MHZ => c_NO +-- ) +-- port map( +-- CLK => CLK_100, -- raw 100MHz clock +-- SYSCLK => clk_150_i, -- 100MHz from PLL +-- RESET => reset_i_trbnet, +-- CLEAR => reset_async, +-- CLK_EN => clk_en, +-- --Internal Connection +-- MED_DATA_IN => med_data_out(31 downto 16), +-- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3), +-- MED_DATAREADY_IN => med_dataready_out(1), +-- MED_READ_OUT => med_read_in(1), +-- MED_DATA_OUT => med_data_in(31 downto 16), +-- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3), +-- MED_DATAREADY_OUT => med_dataready_in(1), +-- MED_READ_IN => med_read_out(1), +-- REFCLK2CORE_OUT => open, +-- --SFP Connection +-- SD_RXD_P_IN => open, -- ignore +-- SD_RXD_N_IN => open, -- ignore +-- SD_TXD_P_OUT => open, -- ignore +-- SD_TXD_N_OUT => open, -- ignore +-- SD_REFCLK_P_IN => open, -- ignore +-- SD_REFCLK_N_IN => open, -- ignore +-- SD_PRSNT_N_IN => SFP3_MOD(0), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) +-- SD_LOS_IN => SFP3_LOS, -- SFP Loss Of Signal ('0' = OK, '1' = no signal) +-- SD_TXDIS_OUT => SFP3_TX_DIS, -- SFP disable +-- -- Status and control port +-- STAT_OP => med_stat_op(31 downto 16), +-- CTRL_OP => med_ctrl_op(31 downto 16), +-- STAT_DEBUG => open, +-- CTRL_DEBUG => (others => '0') +-- ); + + +med_stat_op(31 downto 16) <= x"000" & "0111"; +--------------------------------------------------------------------------- +-- Active Endpoint +--------------------------------------------------------------------------- + + THE_ENDPOINT : trb_net_bridge_pcie_endpoint_hub + generic map( + NUM_LINKS => NUM_LINKS, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map( + RESET => reset_i_trbnet, + CLK => clk_150_i, + + BUS_ADDR_IN => bus_addr, + BUS_WDAT_IN => bus_dout, + BUS_RDAT_OUT => bus_din, + BUS_SEL_IN => bus_sel, + BUS_WE_IN => bus_we, + BUS_CYC_IN => bus_cyc, + BUS_STB_IN => bus_stb, + BUS_LOCK_IN => bus_lock, + BUS_ACK_OUT => bus_ack, + + MED_DATAREADY_IN => med_dataready_in, + MED_DATA_IN => med_data_in, + MED_PACKET_NUM_IN => med_packet_num_in, + MED_READ_OUT => med_read_out, + + MED_DATAREADY_OUT => med_dataready_out, + MED_DATA_OUT => med_data_out, + MED_PACKET_NUM_OUT => med_packet_num_out, + MED_READ_IN => med_read_in, + + + MED_STAT_OP_IN => med_stat_op, + MED_CTRL_OP_OUT => buf_med_ctrl_op, + + SEND_RESET_OUT => send_network_reset, + DEBUG_OUT => open + ); + +--------------------------------------------------------------------------- +-- PCIe +--------------------------------------------------------------------------- + THE_PCI_CORE : pci_core + port map( + CLK_PCIE_IN => PE_RFCK, + CLK_SYS_IN => clk_150_i, + CLK_WB_IN => clk_150_i, + CLK_125_OUT => clk_125_i, + RESET_IN => reset_i, + CLEAR_IN => '0', + --PCIe + -- PCIE_DINP => PCIE_RX(3 downto 0), + -- PCIE_DINN => PCIE_RX(7 downto 4), + -- PCIE_DOUTP => PCIE_TX(3 downto 0), + -- PCIE_DOUTN => PCIE_TX(7 downto 4), + PCIE_DINP => "0000", + PCIE_DINN => "0000", + PCIE_DOUTP => open, + PCIE_DOUTN => open, + --single access + BUS_ADDR_OUT => bus_addr, + BUS_WDAT_OUT => bus_dout, + BUS_RDAT_IN => bus_din, + BUS_SEL_OUT => bus_sel, + BUS_WE_OUT => bus_we, + BUS_CYC_OUT => bus_cyc, + BUS_STB_OUT => bus_stb, + BUS_LOCK_OUT => bus_lock, + BUS_ACK_IN => bus_ack, + + --DMA + DMA_ADDR => dma_addr, + DMA_WDAT => dma_din, + DMA_RDAT => dma_dout, + DMA_SEL => dma_sel, + DMA_WE => dma_we, + DMA_CYC => dma_cyc, + DMA_STB => dma_stb, + DMA_LOCK => dma_lock, + DMA_CTI => dma_cti, + DMA_ACK => dma_ack, + DMA_ERR => dma_err, + DMA_RETRY => dma_retry, + DMA_EOD => dma_eod, + + --Debug + DEBUG_OUT => debug_pci_core + ); + + + + + +--------------------------------------------------------------------------- +-- Unused IO +--------------------------------------------------------------------------- + SFP2_TX_DIS <= '1'; + SFP3_TX_DIS <= '1'; + SFP4_TX_DIS <= '1'; + SPI_SCK_OUT <= '0'; + SPI_CS_OUT <= '0'; + SPI_SI_OUT <= '0'; + SDA_TMP <= '0'; + SCK_TMP <= '0'; + plluser <= (others => '0'); + ant <= (others => '0'); + + + +--------------------------------------------------------------------------- +-- LED & Debug +--------------------------------------------------------------------------- + led(3) <= not pll_locked; + + led(0) <= not med_stat_op(9); + led(1) <= not med_stat_op(10); + led(2) <= not med_stat_op(11); + + led(4) <= not med_stat_op(16+9); + led(5) <= not med_stat_op(16+10); + led(6) <= not med_stat_op(16+11); + + led(7) <= not send_network_reset; + + test(3 downto 0) <= bus_din(3 downto 0); + test(4) <= bus_dout(0); + + + test(5) <= bus_we; + test(6) <= bus_stb; + test(7) <= bus_ack; + +-- test(15 downto 8) <= debug_pci_core(23 downto 16); + test(8) <= bus_ack; + test(9) <= bus_dout(15); + test(15 downto 10) <= debug_pci_core(21 downto 16); + +-- test(3 downto 0) <= med_stat_op(7 downto 4); --fsm state +-- test(5 downto 4) <= med_stat_debug(46 downto 45); --tx_k +-- test(7 downto 6) <= med_stat_debug(17 downto 16); --rx_k +-- test(14 downto 8) <= med_stat_debug(6 downto 0); --rx_d +-- test(15) <= send_network_reset; + +-- -- Debug output +-- stat_debug(15 downto 0) <= rx_data; +-- stat_debug(17 downto 16) <= rx_k; +-- stat_debug(18) <= link_ok(0); +-- stat_debug(19) <= quad_rst; +-- stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); +-- stat_debug(24) <= fifo_rx_rd_en; +-- stat_debug(25) <= fifo_rx_wr_en; +-- stat_debug(26) <= fifo_rx_reset; +-- stat_debug(27) <= fifo_rx_empty; +-- stat_debug(28) <= fifo_rx_full; +-- stat_debug(29) <= last_rx(8); +-- stat_debug(30) <= rx_allow_delay; +-- stat_debug(31) <= lane_rst; +-- stat_debug(41 downto 32) <= (others => '0'); +-- stat_debug(42) <= sysclk; +-- stat_debug(43) <= '0'; --tx_halfclk; +-- stat_debug(44) <= '0'; --rx_halfclk; +-- stat_debug(46 downto 45) <= tx_k; +-- stat_debug(47) <= tx_allow; +-- stat_debug(59 downto 48) <= (others => '0'); +-- stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); + + + +end architecture; \ No newline at end of file diff --git a/size.txt b/size.txt index 820a6c6..dad804c 100644 --- a/size.txt +++ b/size.txt @@ -18,4 +18,101 @@ MACO 2/10 20% used +18.01.2011 + IO 93/788 11% used + LOGIC 10288/20952 49% used + SPECIAL 57/462 12% used + PIO (prelim) 93/696 13% used + 93/562 16% bonded + + SLICE 10271/20256 50% used + IOLOGIC 17/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 48/216 22% used + PCS 2/4 50% used + MACO 2/10 20% used + + + +20.01.2011 + IO 93/788 11% used + LOGIC 9592/20952 45% used + SPECIAL 41/462 8% used + + PIO (prelim) 93/696 13% used + 93/562 16% bonded + + SLICE 9575/20256 47% used + IOLOGIC 17/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 32/216 14% used + PCS 2/4 50% used + MACO 2/10 20% used + + +20.01.2011 + IO 93/788 11% used + LOGIC 8783/20952 41% used + SPECIAL 35/462 7% used + + PIO (prelim) 93/696 13% used + 93/562 16% bonded + + SLICE 8766/20256 43% used + IOLOGIC 17/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 26/216 12% used + PCS 2/4 50% used + MACO 2/10 20% used + + +21.01.11 + IO 93/788 11% used + LOGIC 7283/20952 34% used + SPECIAL 35/462 7% used + + PIO (prelim) 93/696 13% used + 93/562 16% bonded + + SLICE 7266/20256 35% used + IOLOGIC 17/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 26/216 12% used + PCS 2/4 50% used + MACO 2/10 20% used + + + +21.01.11 + IO 93/788 11% used + LOGIC 6757/20952 32% used + SPECIAL 35/462 7% used + + PIO (prelim) 93/696 13% used + 93/562 16% bonded + + SLICE 6740/20256 33% used + IOLOGIC 17/696 2% used + + GSR 1/1 100% used + PLL 2/8 25% used + CLKDIV 2/20 10% used + EBR 26/216 12% used + PCS 2/4 50% used + MACO 2/10 20% used + + +22.01.11 -- 2.43.0