From 77e1f7aa5584579e6daea449da3543a16eb04d57 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 30 Jul 2013 18:31:41 +0200 Subject: [PATCH] started reading and rewriting slow-control part --- vhdl/code/jtag_cmd_m26c.vhd | 389 +++++++++--------------------------- vhdl/code/jtag_mvd.vhd | 21 +- 2 files changed, 102 insertions(+), 308 deletions(-) diff --git a/vhdl/code/jtag_cmd_m26c.vhd b/vhdl/code/jtag_cmd_m26c.vhd index 5cbaa1b..37ad617 100644 --- a/vhdl/code/jtag_cmd_m26c.vhd +++ b/vhdl/code/jtag_cmd_m26c.vhd @@ -48,7 +48,7 @@ entity jtag_cmd_m26c is BUS_DATA_IN : in std_logic_vector(31 downto 0); BUS_DATA_OUT : out std_logic_vector(31 downto 0); - BUS_ADDR_IN : in std_logic_vector(8 downto 0); + BUS_ADDR_IN : in std_logic_vector(9 downto 0); BUS_READ_IN : in std_logic; BUS_WRITE_IN : in std_logic; @@ -930,10 +930,10 @@ signal ram3a_dout1 : std_logic_vector(31 downto 0); -- ram3b port 1: non local flipflops, all connected to components -- see jtag_copy_ram3* signals -- ram3b port 2: local flipflops -signal ram3b_a2_base_addr, ram3b_a2_base_addr_next : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0); -signal ram3b_a2_rel_addr, ram3b_a2_rel_addr_next : std_logic_vector(3 downto 0); -signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); -signal ram3b_dout2 : std_logic_vector(31 downto 0); +signal ram3b_a2_base_addr : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-4-1 downto 0); +signal ram3b_a2_rel_addr : std_logic_vector(3 downto 0); +signal ram3b_a2 : std_logic_vector(RAM_ERROR_COUNTS_DEPTH-1 downto 0); +signal ram3b_dout2 : std_logic_vector(31 downto 0); signal ram3a_select, ram3a_select_next : std_logic; signal ram3a_rd_select, ram3a_rd_select_next : std_logic; @@ -986,7 +986,7 @@ signal numchips_configured, numchips_configured_next : unsigned(MAX_NUMCHIPS_LD- signal numchips_active, numchips_active_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); signal numchips_active_acc, numchips_active_acc_next : unsigned(MAX_NUMCHIPS_LD-1 downto 0); -signal debug_m26cs_state, debug_m26cs_state_next : std_logic_vector(7 downto 0); +signal debug_m26cs_state : std_logic_vector(7 downto 0); signal debug_test, debug_test_next : std_logic_vector(31 downto 0); signal debug_trigger_counter, debug_trigger_counter_next : unsigned(31 downto 0); @@ -1017,21 +1017,17 @@ signal bus2_status_write_ack_in, bus2_status_write_ack_in_next : std_logic; signal bus2_status_no_more_data_in, bus2_status_no_more_data_in_next : std_logic; signal bus2_status_unknown_addr_in, bus2_status_unknown_addr_in_next : std_logic; ---signal bus2_status2_addr_out : std_logic_vector(4 downto 0); signal bus2_status2_addr_out : std_logic_vector(15 downto 0); signal bus2_status2_data_out : std_logic_vector(31 downto 0); signal bus2_status2_read_enable_out : std_logic; signal bus2_status2_write_enable_out : std_logic; -signal bus2_status2_timeout_out : std_logic; -signal bus2_status2_data_in, bus2_status2_data_in_next : std_logic_vector(31 downto 0); -signal bus2_status2_dataready_in, bus2_status2_dataready_in_next : std_logic; -signal bus2_status2_write_ack_in, bus2_status2_write_ack_in_next : std_logic; -signal bus2_status2_no_more_data_in, bus2_status2_no_more_data_in_next : std_logic; -signal bus2_status2_unknown_addr_in, bus2_status2_unknown_addr_in_next : std_logic; +signal bus2_status2_data_in : std_logic_vector(31 downto 0); +signal bus2_status2_ack_in : std_logic; +signal bus2_status2_nack_in : std_logic; -signal bus2_status2_read_ram3b, bus2_status2_read_ram3b_next : std_logic; -signal buf_bus2_status2_read_ram3b, buf_bus2_status2_read_ram3b_next : std_logic; +signal bus2_status2_read_ram3b : std_logic; +signal buf_bus2_status2_read_ram3b : std_logic; signal status2_run_counter, status2_run_counter_next : unsigned(31 downto 0); @@ -1350,8 +1346,8 @@ the_bus_handler : trb_net16_regio_bus_handler port map( CLK => CLK_IN, RESET => RESET_IN, - DAT_ADDR_IN(15 downto 9) => "0000000", - DAT_ADDR_IN(8 downto 0)=> BUS_ADDR_IN, -- address bus + DAT_ADDR_IN(15 downto 10) => "000000", + DAT_ADDR_IN(9 downto 0)=> BUS_ADDR_IN, -- address bus DAT_DATA_IN => BUS_DATA_IN, -- data from TRB endpoint DAT_DATA_OUT => BUS_DATA_OUT, -- data to TRB endpoint DAT_READ_ENABLE_IN => BUS_READ_IN, -- read pulse @@ -1390,7 +1386,7 @@ the_bus_handler : trb_net16_regio_bus_handler BUS_TIMEOUT_OUT(1) => bus2_status_timeout_out, BUS_TIMEOUT_OUT(2) => bus2_control_timeout_out, BUS_TIMEOUT_OUT(3) => bus2_debug_timeout_out, - BUS_TIMEOUT_OUT(4) => bus2_status2_timeout_out, + BUS_TIMEOUT_OUT(4) => open, BUS_DATA_IN(0*32+31 downto 0*32) => bus2_ram_data_in, BUS_DATA_IN(1*32+31 downto 1*32) => bus2_status_data_in, @@ -1401,22 +1397,22 @@ the_bus_handler : trb_net16_regio_bus_handler BUS_DATAREADY_IN(1) => bus2_status_dataready_in, BUS_DATAREADY_IN(2) => bus2_control_dataready_in, BUS_DATAREADY_IN(3) => bus2_debug_dataready_in, - BUS_DATAREADY_IN(4) => bus2_status2_dataready_in, + BUS_DATAREADY_IN(4) => bus2_status2_ack_in, BUS_WRITE_ACK_IN(0) => bus2_ram_write_ack_in, BUS_WRITE_ACK_IN(1) => bus2_status_write_ack_in, BUS_WRITE_ACK_IN(2) => bus2_control_write_ack_in, BUS_WRITE_ACK_IN(3) => bus2_debug_write_ack_in, - BUS_WRITE_ACK_IN(4) => bus2_status2_write_ack_in, + BUS_WRITE_ACK_IN(4) => bus2_status2_ack_in, BUS_NO_MORE_DATA_IN(0) => bus2_ram_no_more_data_in, BUS_NO_MORE_DATA_IN(1) => bus2_status_no_more_data_in, BUS_NO_MORE_DATA_IN(2) => bus2_control_no_more_data_in, BUS_NO_MORE_DATA_IN(3) => bus2_debug_no_more_data_in, - BUS_NO_MORE_DATA_IN(4) => bus2_status2_no_more_data_in, + BUS_NO_MORE_DATA_IN(4) => '0', BUS_UNKNOWN_ADDR_IN(0) => bus2_ram_unknown_addr_in, BUS_UNKNOWN_ADDR_IN(1) => bus2_status_unknown_addr_in, BUS_UNKNOWN_ADDR_IN(2) => bus2_control_unknown_addr_in, BUS_UNKNOWN_ADDR_IN(3) => bus2_debug_unknown_addr_in, - BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_unknown_addr_in, + BUS_UNKNOWN_ADDR_IN(4) => bus2_status2_nack_in, @@ -2144,7 +2140,6 @@ begin --read_error_counter <= (others => (others => '0')); --read_error_over_threshold_counter <= (others => (others => '0')); debug_test <= (others =>'0'); - debug_m26cs_state <= (others => '0'); bus2_ram_data_in <= (others => '0'); bus2_ram_dataready_in <= '0'; bus2_ram_write_ack_in <= '0'; @@ -2167,13 +2162,6 @@ begin bus2_debug_write_ack_in <= '0'; bus2_debug_no_more_data_in <= '0'; bus2_debug_unknown_addr_in <= '0'; - bus2_status2_data_in <= (others =>'0'); - bus2_status2_dataready_in <= '0'; - bus2_status2_write_ack_in <= '0'; - bus2_status2_no_more_data_in <= '0'; - bus2_status2_unknown_addr_in <= '0'; - bus2_status2_read_ram3b <= '0'; - buf_bus2_status2_read_ram3b <= '0'; prog_jtag_finished <= '0'; --last_write_successful <= '0'; -- NEW SIGNALS @@ -2197,8 +2185,6 @@ begin jtag_sample_pulse3_d1 <= '0'; breakpoint_active <= (others => '0'); ram1b_a2 <= (others => '0'); - ram3b_a2_rel_addr <= (others => '0'); - ram3b_a2_base_addr <= (others => '0'); ram1b_copy_requested <= '0'; ram1c_run_counter <= (others => '0'); @@ -2268,7 +2254,6 @@ begin --read_error_over_threshold_counter <= read_error_over_threshold_counter_next; --m26c_state <= m26c_state_next; debug_test <= debug_test_next; - debug_m26cs_state <= debug_m26cs_state_next; bus2_ram_data_in <= bus2_ram_data_in_next; bus2_ram_dataready_in <= bus2_ram_dataready_in_next; bus2_ram_write_ack_in <= bus2_ram_write_ack_in_next; @@ -2291,13 +2276,6 @@ begin bus2_debug_write_ack_in <= bus2_debug_write_ack_in_next; bus2_debug_no_more_data_in <= bus2_debug_no_more_data_in_next; bus2_debug_unknown_addr_in <= bus2_debug_unknown_addr_in_next; - bus2_status2_data_in <= bus2_status2_data_in_next; - bus2_status2_dataready_in <= bus2_status2_dataready_in_next; - bus2_status2_write_ack_in <= bus2_status2_write_ack_in_next; - bus2_status2_no_more_data_in <= bus2_status2_no_more_data_in_next; - bus2_status2_unknown_addr_in <= bus2_status2_unknown_addr_in_next; - bus2_status2_read_ram3b <= bus2_status2_read_ram3b_next; - buf_bus2_status2_read_ram3b <= buf_bus2_status2_read_ram3b_next; prog_jtag_finished <= prog_jtag_finished_next; --last_write_successful <= last_write_successful_next; -- NEW SIGNALS @@ -2321,8 +2299,6 @@ begin jtag_sample_pulse3_d1 <= jtag_sample_pulse3_d1_next; breakpoint_active <= breakpoint_active_next; ram1b_a2 <= ram1b_a2_next; - ram3b_a2_rel_addr <= ram3b_a2_rel_addr_next; - ram3b_a2_base_addr <= ram3b_a2_base_addr_next; ram1b_copy_requested <= ram1b_copy_requested_next; ram1c_run_counter <= ram1c_run_counter_next; @@ -3067,57 +3043,6 @@ begin bus2_status_data_in_next(31 downto MAX_REGISTERS) <= (others => '0'); bus2_status_data_in_next(MAX_NUMCHIPS - 1 downto 0) <= crc_status_register(MAX_NUMCHIPS - 1 downto 0); bus2_status_dataready_in_next <= '1'; --- elsif(4*(bus_addr_int-1) < MAX_NUMCHIPS) then --- -- for i in 0 to MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3) loop --- -- bus2_status_data_in_next(8*i+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+i); --- -- bus2_status_data_in_next(8*i+7 downto 8*i+6) <= (others => '0'); --- -- end loop; --- -- bus2_status_data_in_next(31 downto 8*(MIN(MAX_NUMCHIPS-4*(bus_addr_int - 1)-1,3)+1)) <= (others => '0'); --- --- bus2_status_data_in_next <= (others => '0'); --- bus2_status_data_in_next(8*0+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+6) <= removed_chips(4*(bus_addr_int-1)+0); --- bus2_status_data_in_next(8*0+7 downto 8*0+7) <= (others => '0'); --- if(4*(bus_addr_int-1)+1 < MAX_NUMCHIPS) then --- bus2_status_data_in_next(8*1+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+6) <= removed_chips(4*(bus_addr_int-1)+1); --- bus2_status_data_in_next(8*1+7 downto 8*1+7) <= (others => '0'); --- end if; --- if(4*(bus_addr_int-1)+2 < MAX_NUMCHIPS) then --- bus2_status_data_in_next(8*2+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+6) <= removed_chips(4*(bus_addr_int-1)+2); --- bus2_status_data_in_next(8*2+7 downto 8*2+7) <= (others => '0'); --- end if; --- if(4*(bus_addr_int-1)+3 < MAX_NUMCHIPS) then --- bus2_status_data_in_next(8*3+0) <= status_register(STATUS_JTAG_ERROR + 4*(bus_addr_int-1)+3); bus2_status_data_in_next(8*3+1) <= status_register(STATUS_WRITE_ERROR + 4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+2) <= status_register(STATUS_WRITE_ERROR2 + 4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+3) <= status_register(STATUS_READ_ERROR + 4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+4) <= status_register(STATUS_READ_ERROR2 + 4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+5) <= status_register(STATUS_DATA_CHANGED + 4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+6) <= removed_chips(4*(bus_addr_int-1)+3); --- bus2_status_data_in_next(8*3+7 downto 8*3+7) <= (others => '0'); --- end if; --- bus2_status_dataready_in_next <= '1'; else bus2_status_unknown_addr_in_next <= '1'; end if; @@ -3156,13 +3081,6 @@ begin m26csoptions_next <= m26csoptions; jtag_delay_expvalues_next <= jtag_delay_expvalues; - --driver_speed_next <= driver_speed; - --deactivate_sensor_strobe_next <= (others => '0'); - --reactivate_sensor_strobe_next <= (others => '0'); - --disable_write_next <= disable_write; - --disable_writeerror_for_remove_next <= disable_writeerror_for_remove; - --disable_remove_next <= disable_remove; - --debug_one_remove_strobe_next <= '0'; if(bus2_control_write_enable_out='1') then -- CONTROL registers layout: -- ADDR_CONTROL_CMD @@ -3451,21 +3369,20 @@ begin end if; end process; -buf_bus2_status2_read_ram3b_next <= bus2_status2_read_ram3b; -BUS2_STATUS2_R : process (bus2_status2_addr_out, bus2_status2_data_out, bus2_status2_read_enable_out, bus2_status2_write_enable_out, bus2_status2_data_in, status2_copy_finished, status2_chain_status, status2_run_counter, bus2_status_addr_out, buf_bus2_status2_read_ram3b, jtag_refresh_active, ram3b_dout2, ram3b_a2_rel_addr, ram3b_a2_base_addr) -variable bus_addr_int : integer range 0 to 31; -begin - bus2_status2_data_in_next <= bus2_status2_data_in; - bus2_status2_dataready_in_next <= '0'; - bus2_status2_write_ack_in_next <= '0'; - bus2_status2_no_more_data_in_next <= '0'; - bus2_status2_unknown_addr_in_next <= '0'; - bus2_status2_read_ram3b_next <= '0'; - ram3b_a2_base_addr_next <= ram3b_a2_base_addr; - ram3b_a2_rel_addr_next <= ram3b_a2_rel_addr; + + + +BUS2_STATUS2_R : process begin + wait until rising_edge(CLK_IN); + bus2_status2_data_in <= (others => '0'); + bus2_status2_ack_in <= '0'; + bus2_status2_nack_in <= '0'; + bus2_status2_read_ram3b <= '0'; + buf_bus2_status2_read_ram3b <= bus2_status2_read_ram3b; + if(buf_bus2_status2_read_ram3b = '1') then - bus2_status2_data_in_next <= ram3b_dout2; - bus2_status2_dataready_in_next <= '1'; + bus2_status2_data_in <= ram3b_dout2; + bus2_status2_ack_in <= '1'; end if; if(bus2_status2_read_enable_out='1') then -- STATUS register layout: 8 bits/chip @@ -3473,203 +3390,85 @@ begin -- bits i*32+31 downto i*32: bits 0: JTAG_ERROR, 1: WRITE_ERROR, 2: WRITE_ERROR2, 3: READ_ERROR, 4: READ_ERROR2, -- 5: DATA_CHANGED, 6: reserved, 7: reserved if(bus2_status2_addr_out(4) = '1') then -- ram3b - ram3b_a2_rel_addr_next <= bus2_status_addr_out(3 downto 0); - bus2_status2_read_ram3b_next <= '1'; - -- dataready delayed - elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_TRIGGERCOUNTER_COPY) then - bus2_status2_data_in_next <= std_logic_vector(status2_run_counter); - bus2_status2_dataready_in_next <= '1'; - elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_CHAIN_STATUS_COPY) then - bus2_status2_data_in_next(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status; - bus2_status2_data_in_next(31 downto 8) <= (others => '0'); - bus2_status2_dataready_in_next <= '1'; - elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_UPDATING) then - bus2_status2_data_in_next(0) <= not status2_copy_finished; - bus2_status2_data_in_next(31 downto 1) <= (others => '0'); - bus2_status2_dataready_in_next <= '1'; - elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then - bus2_status2_data_in_next(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0) <= ram3b_a2_base_addr; - bus2_status2_data_in_next(31 downto RAM_ERROR_COUNTS_DEPTH-4 ) <= (others => '0'); - bus2_status2_dataready_in_next <= '1'; - elsif(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_STARTED) then - bus2_status2_data_in_next(0) <= jtag_refresh_active; - bus2_status2_data_in_next(31 downto 1) <= (others => '0'); - bus2_status2_dataready_in_next <= '1'; + ram3b_a2_rel_addr <= bus2_status_addr_out(3 downto 0); + bus2_status2_read_ram3b <= '1'; else - bus2_status2_unknown_addr_in_next <= '1'; + bus2_status2_ack_in <= '1'; + case bus2_status2_addr_out(4 downto 0) is + when ADDR_STATUS2_TRIGGERCOUNTER_COPY => + bus2_status2_data_in <= std_logic_vector(status2_run_counter); + when ADDR_STATUS2_CHAIN_STATUS_COPY => + bus2_status2_data_in(3+MAX_NUMCHIPS_PLUS_ONE_LD-1 downto 0) <= status2_chain_status; + when ADDR_STATUS2_UPDATING => + bus2_status2_data_in(0) <= not status2_copy_finished; + when ADDR_STATUS2_RAM3B_BASEADDR => + bus2_status2_data_in(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0) <= ram3b_a2_base_addr; + when ADDR_STATUS2_STARTED => + bus2_status2_data_in(0) <= jtag_refresh_active; + when others => + bus2_status2_ack_in <= '0'; + bus2_status2_nack_in <= '1'; + end case; end if; end if; if(bus2_status2_write_enable_out='1') then if(bus2_status2_addr_out(4 downto 0) = ADDR_STATUS2_RAM3B_BASEADDR) then - ram3b_a2_base_addr_next <= bus2_status2_data_out(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0); - bus2_status2_write_ack_in_next <= '1'; + ram3b_a2_base_addr <= bus2_status2_data_out(RAM_ERROR_COUNTS_DEPTH-4 -1 downto 0); + bus2_status2_ack_in <= '1'; else - bus2_status2_unknown_addr_in_next <= '1'; + bus2_status2_nack_in <= '1'; end if; end if; end process; ---trigger_process : process (trigger_counter) ---begin - --trigger_counter_next <= trigger_counter + 1; - --jtag_refresh_start_next <= '0'; - --if(trigger_counter = "00000000000") then - -- jtag_refresh_start_next <= '1'; - --end if; ---end process; - --- reactivate_sensor_wait : process (reactivate_sensor, reactivate_sensor_strobe, removed_chips) --- begin --- reactivate_sensor_next <= reactivate_sensor; --- for i in 0 to MAX_NUMCHIPS-1 loop --- if(reactivate_sensor_strobe(i) = '1') then --- reactivate_sensor_next(i) <= '1'; --- elsif(removed_chips(i) = '0') then --- reactivate_sensor_next(i) <= '0'; --- end if; --- end loop; --- end process; --- deactivate_sensor_wait : process (deactivate_sensor, deactivate_sensor_strobe, removed_chips) --- begin --- deactivate_sensor_next <= deactivate_sensor; --- for i in 0 to MAX_NUMCHIPS-1 loop --- if(deactivate_sensor_strobe(i) = '1') then --- deactivate_sensor_next(i) <= '1'; --- elsif(removed_chips(i) = '1') then --- deactivate_sensor_next(i) <= '0'; --- end if; --- end loop; --- end process; --- --- one_remove_wait : process (debug_one_remove_strobe, removed_strobe) --- begin --- debug_one_remove_next <= debug_one_remove; --- if(removed_strobe = '1') then --- debug_one_remove_next <= '0'; --- elsif(debug_one_remove_strobe = '1') then --- debug_one_remove_next <= '1'; --- end if; --- end process; - -debug_m26cs_state_process : process (m26cs_state) -begin +debug_m26cs_state_process : process begin + wait until rising_edge(CLK_IN); case m26cs_state is - when M26CSS_WAIT_FOR_TRIGGER => - debug_m26cs_state_next <= x"00"; - when M26CSS_CHECK_CRC_RAM1A_BEGIN => - debug_m26cs_state_next <= x"20"; - when M26CSS_CHECK_CRC_RAM1A_WAIT => - debug_m26cs_state_next <= x"21"; - when M26CSS_INIT_RAM1B_BEGIN => - debug_m26cs_state_next <= x"22"; - when M26CSS_INIT_RAM1B_WAIT => - debug_m26cs_state_next <= x"23"; - when M26CSS_DATA_CHANGED_BEGIN => - debug_m26cs_state_next <= x"01"; - when M26CSS_DATA_CHANGED_WAIT => - debug_m26cs_state_next <= x"02"; - when M26CSS_BLANK_RAM3A_WAIT => - debug_m26cs_state_next <= x"24"; - when M26CSS_JUEC_DATA_CHANGED_BEGIN => - debug_m26cs_state_next <= x"03"; - when M26CSS_JUEC_DATA_CHANGED_WAIT => - debug_m26cs_state_next <= x"04"; - when M26CSS_COUNT_CHIPS_BEGIN => - debug_m26cs_state_next <= x"05"; - when M26CSS_COUNT_CHIPS_WAIT => - debug_m26cs_state_next <= x"06"; - when M26CSS_BYPASSREG_BEGIN => - debug_m26cs_state_next <= x"07"; - when M26CSS_BYPASSREG_WAIT => - debug_m26cs_state_next <= x"08"; - when M26CSS_READ1_BEGIN => - debug_m26cs_state_next <= x"09"; - when M26CSS_READ1_WAIT => - debug_m26cs_state_next <= x"0a"; - when M26CSS_JUEC_READ_BEGIN => - debug_m26cs_state_next <= x"0b"; - when M26CSS_JUEC_READ_WAIT => - debug_m26cs_state_next <= x"0c"; - when M26CSS_WRITE1_BEGIN => - debug_m26cs_state_next <= x"0d"; - when M26CSS_WRITE1_WAIT => - debug_m26cs_state_next <= x"0e"; - when M26CSS_WRITE2_BEGIN => - debug_m26cs_state_next <= x"0f"; - when M26CSS_WRITE2_WAIT => - debug_m26cs_state_next <= x"10"; - when M26CSS_JUEC_WRITE_BEGIN => - debug_m26cs_state_next <= x"11"; - when M26CSS_JUEC_WRITE_WAIT => - debug_m26cs_state_next <= x"12"; - when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME => - debug_m26cs_state_next <= x"13"; - when M26CSS_STOPPED => - debug_m26cs_state_next <= x"14"; - when M26CSS_JUEC_RUN_COUNTER_BEGIN => - debug_m26cs_state_next <= x"15"; - when M26CSS_JUEC_RUN_COUNTER_WAIT => - debug_m26cs_state_next <= x"16"; - when M26CSS_REQUEST_RESET_BEGIN => - debug_m26cs_state_next <= x"17"; - when M26CSS_REQUEST_RESET_WAIT => - debug_m26cs_state_next <= x"18"; - when M26CSS_REQUESTED_RESET_WAIT => - debug_m26cs_state_next <= x"19"; - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN => - debug_m26cs_state_next <= x"1a"; - when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT => - debug_m26cs_state_next <= x"1b"; - when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN => - debug_m26cs_state_next <= x"1c"; - when M26CSS_WRITEONCE_INIT_RAM1B_WAIT => - debug_m26cs_state_next <= x"1d"; - when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN => - debug_m26cs_state_next <= x"1e"; - when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT => - debug_m26cs_state_next <= x"1f"; - when M26CSS_WRITEONCE_WRITE1_BEGIN => - debug_m26cs_state_next <= x"25"; - when M26CSS_WRITEONCE_WRITE1_WAIT => - debug_m26cs_state_next <= x"26"; - + when M26CSS_WAIT_FOR_TRIGGER => debug_m26cs_state <= x"00"; + when M26CSS_CHECK_CRC_RAM1A_BEGIN => debug_m26cs_state <= x"20"; + when M26CSS_CHECK_CRC_RAM1A_WAIT => debug_m26cs_state <= x"21"; + when M26CSS_INIT_RAM1B_BEGIN => debug_m26cs_state <= x"22"; + when M26CSS_INIT_RAM1B_WAIT => debug_m26cs_state <= x"23"; + when M26CSS_DATA_CHANGED_BEGIN => debug_m26cs_state <= x"01"; + when M26CSS_DATA_CHANGED_WAIT => debug_m26cs_state <= x"02"; + when M26CSS_BLANK_RAM3A_WAIT => debug_m26cs_state <= x"24"; + when M26CSS_JUEC_DATA_CHANGED_BEGIN => debug_m26cs_state <= x"03"; + when M26CSS_JUEC_DATA_CHANGED_WAIT => debug_m26cs_state <= x"04"; + when M26CSS_COUNT_CHIPS_BEGIN => debug_m26cs_state <= x"05"; + when M26CSS_COUNT_CHIPS_WAIT => debug_m26cs_state <= x"06"; + when M26CSS_BYPASSREG_BEGIN => debug_m26cs_state <= x"07"; + when M26CSS_BYPASSREG_WAIT => debug_m26cs_state <= x"08"; + when M26CSS_READ1_BEGIN => debug_m26cs_state <= x"09"; + when M26CSS_READ1_WAIT => debug_m26cs_state <= x"0a"; + when M26CSS_JUEC_READ_BEGIN => debug_m26cs_state <= x"0b"; + when M26CSS_JUEC_READ_WAIT => debug_m26cs_state <= x"0c"; + when M26CSS_WRITE1_BEGIN => debug_m26cs_state <= x"0d"; + when M26CSS_WRITE1_WAIT => debug_m26cs_state <= x"0e"; + when M26CSS_WRITE2_BEGIN => debug_m26cs_state <= x"0f"; + when M26CSS_WRITE2_WAIT => debug_m26cs_state <= x"10"; + when M26CSS_JUEC_WRITE_BEGIN => debug_m26cs_state <= x"11"; + when M26CSS_JUEC_WRITE_WAIT => debug_m26cs_state <= x"12"; + when M26CSS_CHECK1_WAIT_FOR_HAVE_TIME => debug_m26cs_state <= x"13"; + when M26CSS_STOPPED => debug_m26cs_state <= x"14"; + when M26CSS_JUEC_RUN_COUNTER_BEGIN => debug_m26cs_state <= x"15"; + when M26CSS_JUEC_RUN_COUNTER_WAIT => debug_m26cs_state <= x"16"; + when M26CSS_REQUEST_RESET_BEGIN => debug_m26cs_state <= x"17"; + when M26CSS_REQUEST_RESET_WAIT => debug_m26cs_state <= x"18"; + when M26CSS_REQUESTED_RESET_WAIT => debug_m26cs_state <= x"19"; + when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_BEGIN => debug_m26cs_state <= x"1a"; + when M26CSS_WRITEONCE_CHECK_CRC_RAM1A_WAIT => debug_m26cs_state <= x"1b"; + when M26CSS_WRITEONCE_INIT_RAM1B_BEGIN => debug_m26cs_state <= x"1c"; + when M26CSS_WRITEONCE_INIT_RAM1B_WAIT => debug_m26cs_state <= x"1d"; + when M26CSS_WRITEONCE_COUNT_CHIPS_BEGIN => debug_m26cs_state <= x"1e"; + when M26CSS_WRITEONCE_COUNT_CHIPS_WAIT => debug_m26cs_state <= x"1f"; + when M26CSS_WRITEONCE_WRITE1_BEGIN => debug_m26cs_state <= x"25"; + when M26CSS_WRITEONCE_WRITE1_WAIT => debug_m26cs_state <= x"26"; end case; end process; IDLE_OUT <= idle_out_signal; ---write_idle_last_next <= write_idle; ---read_idle_last_next <= read_idle; ---SEQ_have_time_COUNTER : process(CLK_IN) ---begin --- if(rising_edge(CLK_IN)) then --- if(RESET_IN ='1') then --- htcounter <= (others => '0'); --- have_time_for_write <= '0'; --- debug_trigger_counter <= (others => '0'); --- else --- htcounter <= htcounter_next; --- have_time_for_write <= have_time_for_write_next; --- debug_trigger_counter <= debug_trigger_counter_next; --- end if; --- end if; ---end process; - ----- process for counter and to decide when it's still ok to start a jtag write ---COMB_have_time_COUNTER : process(htcounter, OFF_SPILL_IN, debug_trigger_counter) ---begin --- htcounter_next <= htcounter + 1; --- debug_trigger_counter_next <= debug_trigger_counter; --- if(OFF_SPILL_IN = '1') then --- htcounter_next <= (others => '0'); --- debug_trigger_counter_next <= debug_trigger_counter + 1; --- end if; --- if(to_integer(unsigned(htcounter)) >= 8388608) then -- (about 8/100 seconds = 80ms) --- have_time_for_write_next <= '0'; --- else --- have_time_for_write_next <= '1'; --- end if; ---end process; + ALL_debugtdo : process( CLK_IN) begin diff --git a/vhdl/code/jtag_mvd.vhd b/vhdl/code/jtag_mvd.vhd index 3e20a6e..012a9aa 100644 --- a/vhdl/code/jtag_mvd.vhd +++ b/vhdl/code/jtag_mvd.vhd @@ -87,7 +87,7 @@ architecture jtag_mvd_arch of jtag_mvd is signal jtag_cmd_m26c_no_more_data_out : std_logic_vector(NUM_CHAINS-1 downto 0); signal jtag_cmd_m26c_unknown_addr_out : std_logic_vector(NUM_CHAINS-1 downto 0); - constant num_bus_handler_ports : integer := NUM_CHAINS + 2; + constant num_bus_handler_ports : integer := NUM_CHAINS + 3; type jtag_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(COUNTER_WIDTHS-1 downto 0); type jtag_long_counters_t is array(NUM_CHAINS-1 downto 0) of std_logic_vector(31 downto 0); signal jtagcmd_read_id_errors_count_out : jtag_counters_t; @@ -189,8 +189,8 @@ begin THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( PORT_NUMBER => num_bus_handler_ports, - PORT_ADDRESSES => (0 => x"1000", 1 => x"1800", 2 => x"0000", 3 => x"0200", 4 => x"0400", 5 => x"0600", 6 => x"0800", others => x"0000"), - PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 9, others => 0) + PORT_ADDRESSES => (0 => x"1000", 1 => x"1800", 2 => x"0000", 3 => x"0400", 4 => x"0800", 5 => x"0A00", others => x"0000"), + PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 10, 3 => 10, 4 => 10, 5 => 10, others => 0) ) port map( CLK => clk_sys, @@ -280,20 +280,15 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler THE_STAT_REG_MUX : process(clk_sys) + variable addr : integer; begin if rising_edge(clk_sys) then + addr := to_integer(unsigned(statreg_addr)); statreg_ack <= '0'; statreg_nack <= '0'; - case(statreg_addr(2 downto 0)) is - when "000" => statreg_data <= status_regs(31 downto 0); - when "001" => statreg_data <= status_regs(63 downto 32); - when "010" => statreg_data <= status_regs(95 downto 64); - when "011" => statreg_data <= status_regs(127 downto 96); - when "100" => statreg_data <= x"12345678"; - when others => statreg_data <= (others => '0'); - end case; if statreg_read_en = '1' then - if statreg_addr(7 downto 3) = "00000" then + if (addr < NUM_CHAINS * 8) then + statreg_data <= status_regs(addr*32+31 downto addr*32); statreg_ack <= '1'; else statreg_nack <= '1'; @@ -345,7 +340,7 @@ gen_chains : for i in 0 to NUM_CHAINS-1 generate BUS_DATA_IN => jtag_cmd_m26c_data_in(32*i+31 downto 32*i), BUS_DATA_OUT => jtag_cmd_m26c_data_out(32*i+31 downto 32*i), - BUS_ADDR_IN => jtag_cmd_m26c_addr_in(16*i+8 downto 16*i), + BUS_ADDR_IN => jtag_cmd_m26c_addr_in(16*i+9 downto 16*i), BUS_READ_IN => jtag_cmd_m26c_read_enable_in(i), BUS_WRITE_IN => jtag_cmd_m26c_write_enable_in(i), -- 2.43.0