From 78471d8bf87139fe8cc1596e5291e1d5966c002e Mon Sep 17 00:00:00 2001 From: Florian Marx Date: Fri, 20 Jul 2018 10:25:59 +0200 Subject: [PATCH] all should be running, starting to work on .xml file to load on board --- testbench/tb.vhd | 92 +++++++++++++++++---- trigger_coin.vhd | 73 ++++++++++++++--- trigger_delay.vhd | 1 + trigger_edgedetect.vhd | 62 ++++++-------- trigger_enable.vhd | 9 ++- trigger_inverter.vhd | 9 ++- trigger_logic.vhd | 180 ++++++++++++++++++++++++++++++++++------- trigger_strech.vhd | 51 +++++++++--- 8 files changed, 365 insertions(+), 112 deletions(-) diff --git a/testbench/tb.vhd b/testbench/tb.vhd index da0de20..f605ae8 100644 --- a/testbench/tb.vhd +++ b/testbench/tb.vhd @@ -13,7 +13,7 @@ architecture arch of tb is component trigger_logic generic( - INPUTS : integer := 32; + INPUTS : integer := 32; -------------------------------------------------------------HIER OUTPUTS : integer := 32 ); port( @@ -34,7 +34,7 @@ end component; signal CLK : std_logic := '1'; -- signal RESET : std_logic := '1'; -signal inputs : std_logic_vector(31 downto 0); +signal inputs : std_logic_vector(23 downto 0); signal BUS_RX : CTRLBUS_RX; signal BUS_TX : CTRLBUS_TX; @@ -43,7 +43,7 @@ signal BUS_TX : CTRLBUS_TX; begin -- RESET<= '0' after 500 ns; -CLK <= not CLK after 5 ns; +CLK <= not CLK after 5 ns; -- makes a frequency of 100MHz PROC_INIT_REGISTERS : process begin -- Define the Values for the Registers here BUS_RX.write <= '0'; @@ -62,6 +62,8 @@ PROC_INIT_REGISTERS : process begin wait until rising_edge(CLK); wait for 1 ns; --------------------------------------------------- Delay Registers-------------------------------------------------- + BUS_RX.write <= '1'; BUS_RX.addr <= x"0100"; BUS_RX.data <= x"00000000"; -- + wait until rising_edge(CLK); wait for 1 ns; BUS_RX.write <= '1'; BUS_RX.addr <= x"0101"; BUS_RX.data <= x"00000000"; -- wait until rising_edge(CLK); wait for 1 ns; BUS_RX.write <= '1'; BUS_RX.addr <= x"0102"; BUS_RX.data <= x"00000001"; -- @@ -105,6 +107,8 @@ PROC_INIT_REGISTERS : process begin --------------------------------------------------- Stretch Registers -------------------------------------------------- + BUS_RX.write <= '1'; BUS_RX.addr <= x"0200"; BUS_RX.data <= x"00010008"; -- + wait until rising_edge(CLK); wait for 1 ns; BUS_RX.write <= '1'; BUS_RX.addr <= x"0201"; BUS_RX.data <= x"00010008"; -- wait until rising_edge(CLK); wait for 1 ns; BUS_RX.write <= '1'; BUS_RX.addr <= x"0202"; BUS_RX.data <= x"00010006"; -- @@ -145,6 +149,54 @@ PROC_INIT_REGISTERS : process begin -- wait until rising_edge(CLK); wait for 1 ns; -- BUS_RX.write <= '1'; BUS_RX.addr <= x"0214"; BUS_RX.data <= x"00000005"; -- -- wait until rising_edge(CLK); wait for 1 ns; + + --------------------------------------------------- Coin Registers -------------------------------------------------- + BUS_RX.write <= '1'; BUS_RX.addr <= x"0300"; BUS_RX.data <= x"00010100"; -- 0 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0301"; BUS_RX.data <= x"00000100"; -- 1 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0302"; BUS_RX.data <= x"00030100"; -- 2 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0303"; BUS_RX.data <= x"00020100"; -- 3 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0304"; BUS_RX.data <= x"00050100"; -- 4 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0305"; BUS_RX.data <= x"00040100"; -- 5 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0306"; BUS_RX.data <= x"00070100"; -- 6 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0307"; BUS_RX.data <= x"00060100"; -- 7 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0308"; BUS_RX.data <= x"00090100"; -- 8 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0309"; BUS_RX.data <= x"00080100"; -- 9 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"030A"; BUS_RX.data <= x"000B0100"; -- 10 + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"030B"; BUS_RX.data <= x"000A0100"; -- 11 + wait until rising_edge(CLK); wait for 1 ns; + + + + + --------------------------------------------------- Merge Registers -------------------------------------------------- + BUS_RX.write <= '1'; BUS_RX.addr <= x"0018"; BUS_RX.data <= x"0000000F"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"0019"; BUS_RX.data <= x"000000F0"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001A"; BUS_RX.data <= x"00000F00"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001B"; BUS_RX.data <= x"0000F000"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001C"; BUS_RX.data <= x"000F0000"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001D"; BUS_RX.data <= x"00F00000"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001E"; BUS_RX.data <= x"0F000000"; + wait until rising_edge(CLK); wait for 1 ns; + BUS_RX.write <= '1'; BUS_RX.addr <= x"001F"; BUS_RX.data <= x"F0000000"; + wait until rising_edge(CLK); wait for 1 ns; + @@ -157,32 +209,40 @@ PROC_INPUTS : process begin -- Simulates the Inputs by the detector inputs <= (others => '0'); wait for 500 ns; wait for 24 ns; - inputs <= x"00000001"; + inputs <= x"000001"; wait for 27 ns; - inputs <= x"008AB400"; + inputs <= x"8AB400"; wait for 33 ns; - inputs <= x"0000F44F"; + inputs <= x"00F44F"; wait for 14 ns; - inputs <= x"0000C4CF"; + inputs <= x"00C4CF"; wait for 16 ns; -- too short to detect - inputs <= x"FFFFFFFF"; - wait for 24 ns; - inputs <= x"00000001"; + inputs <= x"FFFFFF"; + wait for 18 ns; + inputs <= x"000001"; + wait for 27 ns; + inputs <= x"FFFFFF"; + wait for 18 ns; + inputs <= x"000001"; + wait for 27 ns; + inputs <= x"FFFFFF"; + wait for 18 ns; + inputs <= x"000001"; wait for 27 ns; - inputs <= x"008AB400"; + inputs <= x"8AB400"; wait for 33 ns; - inputs <= x"0000F44F"; + inputs <= x"00F44F"; wait for 14 ns; - inputs <= x"0000C4CF"; + inputs <= x"00C4CF"; wait for 26 ns; -- too short to detect - inputs <= x"00000000"; + inputs <= x"000000"; end process; THE_LOGIC : trigger_logic generic map( - INPUTS => 32, - OUTPUTS => 32 + INPUTS => 24, + OUTPUTS => 8 ) port map( CLK => CLK, diff --git a/trigger_coin.vhd b/trigger_coin.vhd index 6a43c87..e30a655 100644 --- a/trigger_coin.vhd +++ b/trigger_coin.vhd @@ -8,16 +8,62 @@ library work; entity trg_coincidence is port( - clk_in : in std_logic; - signals : in std_logic_vector(31 downto 0); --- reg_inhalt : in std_logic_vector(31 downto 0); - processed_signals : out std_logic_vector(31 downto 0) + clk_in : in std_logic; + all_signals : in std_logic_vector(31 downto 0); + signal_in : in std_logic; + address_coin1 : in std_logic_vector(7 downto 0); + address_coin2 : in std_logic_vector(7 downto 0); + veto1_enable : in std_logic; + veto2_enable : in std_logic; + coin1_enbl : in std_logic; + coin2_enbl : in std_logic; + processed_signal : out std_logic + ); +end trg_coincidence; + - ) -end trg_coin; +architecture behave of trg_coincidence is +-- signal veto_signal : std_logic; +signal sign1_proc : std_logic; +signal sign2_proc : std_logic; +signal address1_int: integer range 0 to 255; +signal address2_int: integer range 0 to 255; + + + +begin +address1_int <= to_integer(unsigned(address_coin1)); +address2_int <= to_integer(unsigned(address_coin2)); + + +PROC_COIN: process begin +wait until rising_edge(clk_in); + + if coin1_enbl='1' then + if veto1_enable='1' then + sign1_proc<= not all_signals(address1_int); + else + sign1_proc<= all_signals(address1_int); + end if; + else + sign1_proc<='1'; + end if; +-- sign1_proc<= all_signals(address1_int); +-- else +-- sign1_proc<='1'; +-- end if; + if coin2_enbl ='1' then + if veto2_enable='1' then + sign2_proc<= not all_signals(address2_int); + else + sign2_proc<= all_signals(address2_int); + end if; + else + sign2_proc<='1'; + end if; @@ -25,12 +71,15 @@ end trg_coin; -architecture behave of trg_coincidence is + if signal_in='1' and sign1_proc='1' and sign2_proc='1' then + processed_signal<='1'; + else + processed_signal<='0'; + end if; + +end process; + + - - - - -begin end behave; diff --git a/trigger_delay.vhd b/trigger_delay.vhd index e10e777..6019637 100644 --- a/trigger_delay.vhd +++ b/trigger_delay.vhd @@ -7,6 +7,7 @@ library work; entity trg_delay is + port( clk_in : in std_logic; signal_in : in std_logic; diff --git a/trigger_edgedetect.vhd b/trigger_edgedetect.vhd index 1097bd9..b14658e 100644 --- a/trigger_edgedetect.vhd +++ b/trigger_edgedetect.vhd @@ -6,11 +6,14 @@ library work; use work.trb_net_std.all; entity trg_edgedetect is + generic( + CHANNELS : integer := 32 -- Hier erneut definiert, falls keine information + ); port( clk_in : in std_logic; - signals : in std_logic_vector(31 downto 0); --- reg_inhalt : in std_logic_vector(31 downto 0); - processed_signals : out std_logic_vector(31 downto 0) + signals : in std_logic_vector(CHANNELS-1 downto 0); + reg_inhalt : in std_logic_vector(CHANNELS-1 downto 0); + processed_signals : out std_logic_vector(CHANNELS-1 downto 0) ); end trg_edgedetect; @@ -19,22 +22,14 @@ end trg_edgedetect; architecture behave of trg_edgedetect is -signal det_signal : std_logic_vector(31 downto 0); -signal temp_save : std_logic_vector(31 downto 0); -signal temp_save_2 : std_logic_vector(31 downto 0); -signal testing : std_logic_vector(31 downto 0):=x"00001111"; +-- signal det_signal : std_logic_vector(CHANNELS-1 downto 0); +signal temp_save : std_logic_vector(CHANNELS-1 downto 0); +-- signal temp_save_2 : std_logic_vector(CHANNELS-1 downto 0); +-- signal testing : std_logic_vector(CHANNELS-1 downto 0):=x"00001111"; begin --- detect_synchronize: process is --- begin --- wait until rising_edge(clk_in); --- for i in 0 to 31 loop --- --- --- --- end process; detect_step1: process is begin @@ -45,22 +40,15 @@ begin end process; --- detect_step1_5: process is --- begin --- wait until rising_edge(clk_in); --- for i in 0 to 31 loop --- temp_save_2(i)<=temp_save(i); --- temp_save(i)<='0'; --- end loop; --- end process; --- detect_step2: process is begin wait until rising_edge(clk_in); for i in 0 to 31 loop - if signals(i)='1' and temp_save(i)='0' then -- results in processed signal being transmitted fro 0.5 clk to 1.5 clk - processed_signals(i)<='1'; -- maybe synchronize it better ??? + if reg_inhalt(i)='0' then + processed_signals(i)<=signals(i); + elsif signals(i)='1' and temp_save(i)='0' then -- + processed_signals(i)<='1'; -- else processed_signals(i)<='0'; end if; @@ -68,21 +56,19 @@ begin end process; --- detect_step3: process is --- begin --- wait until falling_edge(clk_in); + + + + + +-- detect_step1_5: process is +-- begin +-- wait until rising_edge(clk_in); -- for i in 0 to 31 loop --- if signals(i)='1' then --- if temp_save(i)='0' then --- processed_signals(i)<='1'; --- else processed_signals(i)<='0'; --- end if; --- else processed_signals(i)<='0'; --- end if; +-- temp_save_2(i)<=temp_save(i); +-- temp_save(i)<='0'; -- end loop; -- end process; - --- processed_signals<=testing; end behave; diff --git a/trigger_enable.vhd b/trigger_enable.vhd index f951550..4b21a6c 100644 --- a/trigger_enable.vhd +++ b/trigger_enable.vhd @@ -9,11 +9,14 @@ library work; entity trg_enable is +generic( + CHANNELS : integer := 32 -- Hier erneut definiert, falls keine information + ); port( clk_in : in std_logic; - signals : in std_logic_vector(31 downto 0); - reg_inhalt : in std_logic_vector(31 downto 0); - processed_signals : out std_logic_vector(31 downto 0) + signals : in std_logic_vector(CHANNELS-1 downto 0); + reg_inhalt : in std_logic_vector(CHANNELS-1 downto 0); + processed_signals : out std_logic_vector(CHANNELS-1 downto 0) ); end trg_enable; diff --git a/trigger_inverter.vhd b/trigger_inverter.vhd index f7a23c3..4cb288a 100644 --- a/trigger_inverter.vhd +++ b/trigger_inverter.vhd @@ -9,11 +9,14 @@ library work; entity trg_inverter is +generic( + CHANNELS : integer := 32 -- Hier erneut definiert, falls keine information ueber groesse + ); port( clk_in : in std_logic; - signals : in std_logic_vector(31 downto 0); - reg_inhalt : in std_logic_vector(31 downto 0); - processed_signals : out std_logic_vector(31 downto 0) + signals : in std_logic_vector(CHANNELS-1 downto 0); + reg_inhalt : in std_logic_vector(CHANNELS-1 downto 0); + processed_signals : out std_logic_vector(CHANNELS-1 downto 0) ); end trg_inverter; diff --git a/trigger_logic.vhd b/trigger_logic.vhd index 80b6bd9..2d5ba47 100644 --- a/trigger_logic.vhd +++ b/trigger_logic.vhd @@ -28,8 +28,8 @@ end entity; architecture arch of trigger_logic is -constant CHANNELS : integer := 32; -constant NEUES : integer := 155; +signal CHANNELS : integer ; +signal CHANNELS_OUT : integer ; --Registers signal reg_enable1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0'); @@ -52,27 +52,57 @@ signal reg_stretch1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0'); -- signal reg_stretch2 : std_logic_vector(CHANNELS-1 downto 0); -- signal reg_stretch3 : std_logic_vector(CHANNELS-1 downto 0); -- signal reg_stretch4 : std_logic_vector(CHANNELS-1 downto 0); +signal reg_coin1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0'); +-- signal reg_coin2 : std_logic_vector(CHANNELS-1 downto 0); +-- signal reg_coin3 : std_logic_vector(CHANNELS-1 downto 0); +-- signal reg_coin4 : std_logic_vector(CHANNELS-1 downto 0); +signal reg_merge1 : std_logic_vector(CHANNELS-1 downto 0):=(others => '0'); +-- signal reg_merge2 : std_logic_vector(CHANNELS-1 downto 0); +-- signal reg_merge3 : std_logic_vector(CHANNELS-1 downto 0); +-- signal reg_merge4 : std_logic_vector(CHANNELS-1 downto 0); -- Registers with values type Array10bit is array(CHANNELS-1 downto 0) of std_logic_vector (9 downto 0); --stretch -type Array8bit is array(CHANNELS-1 downto 0) of std_logic_vector (7 downto 0); -- delay +type Array8bit is array(CHANNELS-1 downto 0) of std_logic_vector (7 downto 0); -- delay& coincidence type Array2bit is array(CHANNELS-1 downto 0) of std_logic_vector (1 downto 0); -- stretch_type ns us ms +type ArrayIn_OUTbit is array(CHANNELS_OUT-1 downto 0) of std_logic_vector (CHANNELS-1 downto 0); -- merge + + +------------------------- Delay and Stretch -------------------------- signal stretch_time : Array10bit:=(others => (others => '0')); -signal delay_time : Array8bit:=(others => (others => '0')); +signal delay_time : Array8bit:=(others => (others => '0')); signal stretch_type : Array2bit:=(others => (others => '0')); +------------------------- Concidence --------------------------------- +-- signal veto_enable1 : std_logic_vector (CHANNELS-1 downto 0); +signal coin_veto1 : std_logic_vector (CHANNELS-1 downto 0); +-- signal veto_enable2 : std_logic_vector (CHANNELS-1 downto 0); +signal coin_veto2 : std_logic_vector (CHANNELS-1 downto 0); +signal coin_enbl1 : std_logic_vector (CHANNELS-1 downto 0); +signal coin_enbl2 : std_logic_vector (CHANNELS-1 downto 0); +-- signal addr_coin1 : Array8bit:=(others => (others => '0')); +signal coin_addr1 : Array8bit:=(others => (others => '0')); +-- signal addr_coin2 : Array8bit:=(others => (others => '0')); +signal coin_addr2 : Array8bit:=(others => (others => '0')); + +------------------------- Merge -------------------------------------- +signal reg_merge_array : ArrayIn_OUTbit:=(others => (others => '0')); + -- hand over the signals +signal in_2_enb : std_logic_vector(CHANNELS-1 downto 0); signal enb_2_inv : std_logic_vector(CHANNELS-1 downto 0); signal inv_2_det : std_logic_vector(CHANNELS-1 downto 0); signal det_2_delay: std_logic_vector(CHANNELS-1 downto 0); signal delay_2_str: std_logic_vector(CHANNELS-1 downto 0); signal str_2_cion : std_logic_vector(CHANNELS-1 downto 0); -signal coin_2_out : std_logic_vector(CHANNELS-1 downto 0); +signal coin_2_mer : std_logic_vector(CHANNELS-1 downto 0); +signal mer_2_out : std_logic_vector(CHANNELS_OUT-1 downto 0); + signal address_i : integer range 0 to 255; -signal tester : std_logic_vector(CHANNELS-1 downto 0); --- +-- signal tester : std_logic_vector(CHANNELS-1 downto 0); + @@ -81,11 +111,14 @@ begin --------------------------------------------------------------------------- -- Registers ---------------------------------------------------------------------------- -address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0))); -tester <= str_2_cion; +--------------------------------------------------------------------------- +CHANNELS <= INPUTS + OUTPUTS; +CHANNELS_OUT <= OUTPUTS; +address_i <= to_integer(unsigned(BUS_RX.addr(7 downto 0))); +in_2_enb <= INPUT & mer_2_out; +-- in_2_enb <= INPUT(CHANNELS-1 downto 9) & mer_2_out; PROC_REGS : process begin wait until rising_edge(CLK); @@ -96,6 +129,8 @@ PROC_REGS : process begin if BUS_RX.read = '1' then -- READ BUS_TX.ack <= '1'; if BUS_RX.addr(11 downto 8) = x"0" then + + case BUS_RX.addr(7 downto 0) is when x"00" => BUS_TX.data <= reg_enable1; -- when x"01" => BUS_TX.data <= reg_enable2; @@ -116,7 +151,19 @@ PROC_REGS : process begin when x"10" => BUS_TX.data <= reg_stretch1; -- when x"11" => BUS_TX.data <= reg_stretch2; -- when x"12" => BUS_TX.data <= reg_stretch3; --- when x"13" => BUS_TX.data <= reg_stretch4; +-- when x"13" => BUS_TX.data <= reg_stretch4; + when x"14" => BUS_TX.data <= reg_coin1; +-- when x"15" => BUS_TX.data <= reg_coin2;vhd +-- when x"16" => BUS_TX.data <= reg_coin3; +-- when x"17" => BUS_TX.data <= reg_coin4; + when x"18" => BUS_TX.data <= reg_merge_array(0); + when x"19" => BUS_TX.data <= reg_merge_array(1); + when x"1A" => BUS_TX.data <= reg_merge_array(2); + when x"1B" => BUS_TX.data <= reg_merge_array(3); + when x"1C" => BUS_TX.data <= reg_merge_array(4); + when x"1D" => BUS_TX.data <= reg_merge_array(5); + when x"1E" => BUS_TX.data <= reg_merge_array(6); + when x"1F" => BUS_TX.data <= reg_merge_array(7); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr(11 downto 8) = x"1" then --special adress for delay time declaration @@ -131,11 +178,17 @@ PROC_REGS : process begin else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; + elsif BUS_RX.addr(11 downto 8) = x"3" then + if address_i < CHANNELS then + BUS_TX.data <= "000" & coin_veto2(address_i) & "000" & coin_enbl2(address_i) & coin_addr2(address_i) & "000" & coin_veto1(address_i) & "000" & coin_enbl1(address_i) & coin_addr1(address_i) ; + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end if; end if; elsif BUS_RX.write = '1' then --WRITE BUS_TX.ack <= '1'; - if BUS_RX.addr(11 downto 8) = x"0" then -- better 11 downto 8 + if BUS_RX.addr(11 downto 8) = x"0" then case BUS_RX.addr(7 downto 0) is when x"00" => reg_enable1 <= BUS_RX.data; -- when x"01" => reg_enable2 <= BUS_RX.data; @@ -156,7 +209,19 @@ PROC_REGS : process begin when x"10" => reg_stretch1 <= BUS_RX.data; -- when x"11" => reg_stretch2 <= BUS_RX.data; -- when x"12" => reg_stretch3 <= BUS_RX.data; --- when x"13" => reg_stretch4 <= BUS_RX.data; +-- when x"13" => reg_stretch4 <= BUS_RX.data; + when x"14" => reg_coin1 <= BUS_RX.data; +-- when x"15" => reg_stretch2 <= BUS_RX.data; +-- when x"16" => reg_stretch3 <= BUS_RX.data; +-- when x"17" => reg_stretch4 <= BUS_RX.data; + when x"18" => reg_merge_array(0) <= BUS_RX.data; + when x"19" => reg_merge_array(1) <= BUS_RX.data; + when x"1A" => reg_merge_array(2) <= BUS_RX.data; + when x"1B" => reg_merge_array(3) <= BUS_RX.data; + when x"1C" => reg_merge_array(4) <= BUS_RX.data; + when x"1D" => reg_merge_array(5) <= BUS_RX.data; + when x"1E" => reg_merge_array(6) <= BUS_RX.data; + when x"1F" => reg_merge_array(7) <= BUS_RX.data; when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; elsif BUS_RX.addr(11 downto 8) = x"1" then @@ -169,6 +234,17 @@ PROC_REGS : process begin if address_i < CHANNELS then stretch_type(address_i) <= BUS_RX.data(17 downto 16); stretch_time(address_i) <= BUS_RX.data(9 downto 0); + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + end if; + elsif BUS_RX.addr(11 downto 8) = x"3" then + if address_i < CHANNELS then + coin_veto1(address_i) <= BUS_RX.data(12); + coin_veto2(address_i) <= BUS_RX.data(28); + coin_enbl2(address_i) <= BUS_RX.data(24); + coin_addr2(address_i) <= BUS_RX.data(23 downto 16); + coin_enbl1(address_i) <= BUS_RX.data(8); + coin_addr1(address_i) <= BUS_RX.data(7 downto 0); else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; @@ -177,18 +253,28 @@ PROC_REGS : process begin end process; -THE_ENABLE : entity work.trg_enable + +--------------------------------------------------------------------------- +-- Entities +--------------------------------------------------------------------------- + +THE_ENABLE : entity work.trg_enable +-- generic map( +-- CHANNELS => CHANNELS +-- ) port map( clk_in => CLK, - signals => INPUT, + signals => in_2_enb, reg_inhalt => reg_enable1, processed_signals=> enb_2_inv ); THE_INVERTER : entity work.trg_inverter - +-- generic map( +-- CHANNELS => CHANNELS +-- ) port map( clk_in => CLK, signals => enb_2_inv, @@ -198,11 +284,13 @@ THE_INVERTER : entity work.trg_inverter THE_DETECT: entity work.trg_edgedetect - +generic map( + CHANNELS => CHANNELS + ) port map( clk_in => CLK, - signals => inv_2_det, --- reg_inhalt => reg_edgedetect1, + signals => inv_2_det, + reg_inhalt => reg_edgedetect1, processed_signals=> det_2_delay ); @@ -234,14 +322,48 @@ THE_STRETCH: entity work.trg_stretch ); end generate; --- THE_COIN : entity work.trg_coincidence --- --- port map( --- clk_in => CLK, --- signals => str_2_cion, --- -- reg_inhalt => reg_coin1, --- processed_signals=> coin_2_out --- ); --- - + +GEN_COIN: for i in 0 to CHANNELS-1 generate +THE_COIN : entity work.trg_coincidence + + port map( + clk_in => CLK, + all_signals => str_2_cion, + signal_in => str_2_cion(i), + address_coin1 => coin_addr1(i), + address_coin2 => coin_addr2(i), + veto1_enable => coin_veto1(i), + veto2_enable => coin_veto2(i), + coin1_enbl => coin_enbl1(i), + coin2_enbl => coin_enbl2(i), + processed_signal => coin_2_mer(i) + ); +end generate; + + +GEN_MERGE : for i in 0 to CHANNELS_OUT-1 generate +THE_MERGE: entity work.trg_merge + + port map( + clk_in => CLK, + signals => coin_2_mer, -- + reg_inhalt => reg_merge_array(i), + processed_signal=> mer_2_out(i) + ); +end generate; + + + end architecture; + + + + + + + + + + + + diff --git a/trigger_strech.vhd b/trigger_strech.vhd index bade4ca..f494780 100644 --- a/trigger_strech.vhd +++ b/trigger_strech.vhd @@ -39,47 +39,76 @@ begin stretch_time_int <= to_integer(unsigned(stretch_time(9 downto 0))); -- umschreiben passt noch nicht stretch_type_int <= to_integer(unsigned(stretch_type(1 downto 0))); -- output <= '1'; - bessererTest <= '1'; +-- bessererTest <= '1'; + +-- PROC_STRETCH_1: process begin +-- wait until rising_edge(clk_in); +-- if signal_in='1' then +-- output<='1'; +-- downcounter<=stretch_time_int; +-- elsif signal_in='0' then +-- if stretch_type_int = 0 then +-- output <= '0'; +-- end if; +-- if stretch_type_int = 1 then +-- tester<= tester +1 ; +-- if downcounter> 0 then +-- downcounter <= downcounter -1; +-- else +-- output<='0'; +-- end if; +-- end if; +-- if stretch_type_int= 2 then +-- if downcounter > 0 and pulse_10='1' then +-- downcounter<= downcounter -1 ; +-- else +-- output<='0'; +-- end if; +-- end if; +-- if stretch_type_int = 3 then +-- if downcounter>0 and pulse_11='1' then +-- downcounter<= downcounter -1 ; +-- else +-- output<='0'; +-- end if; +-- end if; +-- end if; +-- end process; PROC_STRETCH_1: process begin wait until rising_edge(clk_in); if signal_in='1' then output<='1'; downcounter<=stretch_time_int; --- elsif stretch_type=x"0" then elsif signal_in='0' then if stretch_type_int = 0 then output <= '0'; - end if; - if stretch_type_int = 1 then + elsif stretch_type_int = 1 then tester<= tester +1 ; if downcounter> 0 then downcounter <= downcounter -1; else output<='0'; end if; - end if; - if stretch_type_int= 2 then + elsif stretch_type_int= 2 then if downcounter > 0 and pulse_10='1' then downcounter<= downcounter -1 ; else output<='0'; end if; - end if; - if stretch_type_int = 3 then + elsif stretch_type_int = 3 then if downcounter>0 and pulse_11='1' then downcounter<= downcounter -1 ; else output<='0'; end if; - end if; end if; + end if; end process; PROC_PULSEGENERATOR: process begin wait until rising_edge (clk_in); - if timer_10=x"3E8" then pulse_10<='1'; timer_10<=x"000" ; @@ -96,7 +125,7 @@ PROC_PULSEGENERATOR: process begin else pulse_11<='0'; end if; - end process; +end process; -- 2.43.0