From 78f249c4f7fe6bf1401081ecbfd96566cc7a2b6a Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Mon, 25 Nov 2013 03:07:39 +0100 Subject: [PATCH] all working, hope so --- nxyter/cores/adc_ddr_generic.ipx | 8 + nxyter/cores/adc_ddr_generic.lpc | 62 ++ nxyter/cores/adc_ddr_generic.vhd | 455 +++++++++++++ nxyter/cores/fifo_adc_48to48_dc.ipx | 9 + nxyter/cores/fifo_adc_48to48_dc.lpc | 47 ++ nxyter/cores/fifo_adc_48to48_dc.vhd | 889 ++++++++++++++++++++++++++ nxyter/cores/pll_adc_sampling_clk.ipx | 8 + nxyter/cores/pll_adc_sampling_clk.lpc | 66 ++ nxyter/cores/pll_adc_sampling_clk.vhd | 121 ++++ nxyter/source/adc_ad9228.vhd | 529 +++++++++++++++ nxyter/source/nx_data_receiver.vhd | 192 ++++-- nxyter/source/nxyter_components.vhd | 78 +++ nxyter/source/nxyter_fee_board.vhd | 2 +- nxyter/trb3_periph.prj | 15 +- nxyter/trb3_periph_constraints.lpf | 10 +- 15 files changed, 2425 insertions(+), 66 deletions(-) create mode 100644 nxyter/cores/adc_ddr_generic.ipx create mode 100644 nxyter/cores/adc_ddr_generic.lpc create mode 100644 nxyter/cores/adc_ddr_generic.vhd create mode 100644 nxyter/cores/fifo_adc_48to48_dc.ipx create mode 100644 nxyter/cores/fifo_adc_48to48_dc.lpc create mode 100644 nxyter/cores/fifo_adc_48to48_dc.vhd create mode 100644 nxyter/cores/pll_adc_sampling_clk.ipx create mode 100644 nxyter/cores/pll_adc_sampling_clk.lpc create mode 100644 nxyter/cores/pll_adc_sampling_clk.vhd create mode 100644 nxyter/source/adc_ad9228.vhd diff --git a/nxyter/cores/adc_ddr_generic.ipx b/nxyter/cores/adc_ddr_generic.ipx new file mode 100644 index 0000000..ab6da25 --- /dev/null +++ b/nxyter/cores/adc_ddr_generic.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/adc_ddr_generic.lpc b/nxyter/cores/adc_ddr_generic.lpc new file mode 100644 index 0000000..ee4d7ad --- /dev/null +++ b/nxyter/cores/adc_ddr_generic.lpc @@ -0,0 +1,62 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=DDR_GENERIC +CoreRevision=5.3 +ModuleName=adc_ddr_generic +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/23/2013 +Time=14:55:41 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +mode=Receive +trioddr=0 +io_type=LVDS25 +num_int=2 +width=5 +freq_in=187.5 +bandwidth=1875.0 +aligned=Centered +pre-configuration=DISABLED +mode2=Receive +trioddr2=0 +io_type2=LVDS25 +freq_in2=187.5 +gear=2x +aligned2=Centered +num_int2=2 +width2=5 +Interface=GDDRX2_RX.DQS.Centered +Delay=Bypass +Number=2 +dqs1=5 +dqs2=5 +dqs3= +dqs4= +dqs5= +dqs6= +dqs7= +dqs8= +val= +Phase=TRDLLB/DLLDELB +Divider=CLKDIVB +Multiplier=2 +PllFreq=94 diff --git a/nxyter/cores/adc_ddr_generic.vhd b/nxyter/cores/adc_ddr_generic.vhd new file mode 100644 index 0000000..95a90c2 --- /dev/null +++ b/nxyter/cores/adc_ddr_generic.vhd @@ -0,0 +1,455 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.3 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n adc_ddr_generic -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 187.5 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e + +-- Sat Nov 23 14:55:41 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity adc_ddr_generic is + port ( + clk_0: in std_logic; + clk_1: in std_logic; + clkdiv_reset: in std_logic; + eclk: in std_logic; + reset_0: in std_logic; + reset_1: in std_logic; + sclk: out std_logic; + datain_0: in std_logic_vector(4 downto 0); + datain_1: in std_logic_vector(4 downto 0); + q_0: out std_logic_vector(19 downto 0); + q_1: out std_logic_vector(19 downto 0)); + attribute dont_touch : boolean; + attribute dont_touch of adc_ddr_generic : entity is true; +end adc_ddr_generic; + +architecture Structure of adc_ddr_generic is + + -- internal signal declarations + signal datain_1i_t4: std_logic; + signal datain_1i_t3: std_logic; + signal datain_1i_t2: std_logic; + signal datain_1i_t1: std_logic; + signal datain_1i_t0: std_logic; + signal buf_datain_1i4: std_logic; + signal buf_datain_1i3: std_logic; + signal buf_datain_1i2: std_logic; + signal buf_datain_1i1: std_logic; + signal buf_datain_1i0: std_logic; + signal datain_0i_t4: std_logic; + signal datain_0i_t3: std_logic; + signal datain_0i_t2: std_logic; + signal datain_0i_t1: std_logic; + signal datain_0i_t0: std_logic; + signal buf_datain_0i4: std_logic; + signal buf_datain_0i3: std_logic; + signal buf_datain_0i2: std_logic; + signal buf_datain_0i1: std_logic; + signal buf_datain_0i0: std_logic; + signal qb19: std_logic; + signal qa19: std_logic; + signal qb09: std_logic; + signal qa09: std_logic; + signal datain_t9: std_logic; + signal qb18: std_logic; + signal qa18: std_logic; + signal qb08: std_logic; + signal qa08: std_logic; + signal datain_t8: std_logic; + signal qb17: std_logic; + signal qa17: std_logic; + signal qb07: std_logic; + signal qa07: std_logic; + signal datain_t7: std_logic; + signal qb16: std_logic; + signal qa16: std_logic; + signal qb06: std_logic; + signal qa06: std_logic; + signal datain_t6: std_logic; + signal qb15: std_logic; + signal qa15: std_logic; + signal qb05: std_logic; + signal qa05: std_logic; + signal datain_t5: std_logic; + signal qb14: std_logic; + signal qa14: std_logic; + signal qb04: std_logic; + signal qa04: std_logic; + signal datain_t4: std_logic; + signal qb13: std_logic; + signal qa13: std_logic; + signal qb03: std_logic; + signal qa03: std_logic; + signal datain_t3: std_logic; + signal qb12: std_logic; + signal qa12: std_logic; + signal qb02: std_logic; + signal qa02: std_logic; + signal datain_t2: std_logic; + signal qb11: std_logic; + signal qa11: std_logic; + signal qb01: std_logic; + signal qa01: std_logic; + signal datain_t1: std_logic; + signal qb10: std_logic; + signal qa10: std_logic; + signal qb00: std_logic; + signal qa00: std_logic; + signal datain_t0: std_logic; + signal dqclk11: std_logic; + signal dqclk01: std_logic; + signal eclkdqsr1: std_logic; + signal ddrlat1: std_logic; + signal datavalid1: std_logic; + signal prmbdet1: std_logic; + signal ddrclkpol1: std_logic; + signal dqsw1: std_logic; + signal dqclk10: std_logic; + signal dqclk00: std_logic; + signal eclkdqsr0: std_logic; + signal ddrlat0: std_logic; + signal datavalid0: std_logic; + signal prmbdet0: std_logic; + signal ddrclkpol0: std_logic; + signal dqsw0: std_logic; + signal scuba_vlo: std_logic; + signal dqsdel: std_logic; + signal dqsdll_lock: std_logic; + signal dqsdll_uddcntln: std_logic; + signal dqsdll_reset: std_logic; + signal clkos: std_logic; + signal cdiv8: std_logic; + signal cdiv4: std_logic; + signal cdiv1: std_logic; + signal scuba_vhi: std_logic; + signal clkok: std_logic; + signal buf_clk_1: std_logic; + signal buf_clk_0: std_logic; + signal sclk_t: std_logic; + + -- local component declarations + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component IB + port (I: in std_logic; O: out std_logic); + end component; + component CLKDIVB + port (CLKI: in std_logic; RST: in std_logic; + RELEASE: in std_logic; CDIV1: out std_logic; + CDIV2: out std_logic; CDIV4: out std_logic; + CDIV8: out std_logic); + end component; + component IDDRX2D + generic (DELAYMODE : in String; SCLKLATENCY : in Integer); + port (D: in std_logic; SCLK: in std_logic; ECLK: in std_logic; + ECLKDQSR: in std_logic; DDRLAT: in std_logic; + DDRCLKPOL: in std_logic; QA0: out std_logic; + QB0: out std_logic; QA1: out std_logic; + QB1: out std_logic); + end component; + component DQSBUFD + generic (NRZMODE : in String; DYNDEL_CNTL : in String; + DYNDEL_VAL : in Integer; DYNDEL_TYPE : in String); + port (DQSI: in std_logic; SCLK: in std_logic; + READ: in std_logic; DQSDEL: in std_logic; + ECLK: in std_logic; ECLKW: in std_logic; + RST: in std_logic; DYNDELPOL: in std_logic; + DYNDELAY6: in std_logic; DYNDELAY5: in std_logic; + DYNDELAY4: in std_logic; DYNDELAY3: in std_logic; + DYNDELAY2: in std_logic; DYNDELAY1: in std_logic; + DYNDELAY0: in std_logic; DQSW: out std_logic; + DDRCLKPOL: out std_logic; PRMBDET: out std_logic; + DATAVALID: out std_logic; DDRLAT: out std_logic; + ECLKDQSR: out std_logic; DQCLK0: out std_logic; + DQCLK1: out std_logic); + end component; + component DQSDLLB + generic (LOCK_SENSITIVITY : in String); + port (CLK: in std_logic; RST: in std_logic; + UDDCNTLN: in std_logic; LOCK: out std_logic; + DQSDEL: out std_logic); + end component; + component DELAYC + port (A: in std_logic; Z: out std_logic); + end component; + attribute IDDRAPPS : string; + attribute IO_TYPE : string; + attribute IO_TYPE of Inst6_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst6_IB0 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB4 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB3 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB2 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst5_IB0 : label is "LVDS25"; + attribute IDDRAPPS of Inst_IDDRX2D_1_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_1_0 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_4 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_3 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_2 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_1 : label is "DQS_CENTERED"; + attribute IDDRAPPS of Inst_IDDRX2D_0_0 : label is "DQS_CENTERED"; + attribute IO_TYPE of Inst1_IB1 : label is "LVDS25"; + attribute IO_TYPE of Inst1_IB0 : label is "LVDS25"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + udel_datain_1i4: DELAYC + port map (A=>buf_datain_1i4, Z=>datain_1i_t4); + + udel_datain_1i3: DELAYC + port map (A=>buf_datain_1i3, Z=>datain_1i_t3); + + udel_datain_1i2: DELAYC + port map (A=>buf_datain_1i2, Z=>datain_1i_t2); + + udel_datain_1i1: DELAYC + port map (A=>buf_datain_1i1, Z=>datain_1i_t1); + + udel_datain_1i0: DELAYC + port map (A=>buf_datain_1i0, Z=>datain_1i_t0); + + Inst6_IB4: IB + port map (I=>datain_1(4), O=>buf_datain_1i4); + + Inst6_IB3: IB + port map (I=>datain_1(3), O=>buf_datain_1i3); + + Inst6_IB2: IB + port map (I=>datain_1(2), O=>buf_datain_1i2); + + Inst6_IB1: IB + port map (I=>datain_1(1), O=>buf_datain_1i1); + + Inst6_IB0: IB + port map (I=>datain_1(0), O=>buf_datain_1i0); + + udel_datain_0i4: DELAYC + port map (A=>buf_datain_0i4, Z=>datain_0i_t4); + + udel_datain_0i3: DELAYC + port map (A=>buf_datain_0i3, Z=>datain_0i_t3); + + udel_datain_0i2: DELAYC + port map (A=>buf_datain_0i2, Z=>datain_0i_t2); + + udel_datain_0i1: DELAYC + port map (A=>buf_datain_0i1, Z=>datain_0i_t1); + + udel_datain_0i0: DELAYC + port map (A=>buf_datain_0i0, Z=>datain_0i_t0); + + Inst5_IB4: IB + port map (I=>datain_0(4), O=>buf_datain_0i4); + + Inst5_IB3: IB + port map (I=>datain_0(3), O=>buf_datain_0i3); + + Inst5_IB2: IB + port map (I=>datain_0(2), O=>buf_datain_0i2); + + Inst5_IB1: IB + port map (I=>datain_0(1), O=>buf_datain_0i1); + + Inst5_IB0: IB + port map (I=>datain_0(0), O=>buf_datain_0i0); + + Inst_IDDRX2D_1_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t9, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa09, QB0=>qb09, QA1=>qa19, QB1=>qb19); + + Inst_IDDRX2D_1_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t8, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa08, QB0=>qb08, QA1=>qa18, QB1=>qb18); + + Inst_IDDRX2D_1_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t7, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa07, QB0=>qb07, QA1=>qa17, QB1=>qb17); + + Inst_IDDRX2D_1_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t6, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa06, QB0=>qb06, QA1=>qa16, QB1=>qb16); + + Inst_IDDRX2D_1_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t5, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr1, DDRLAT=>ddrlat1, DDRCLKPOL=>ddrclkpol1, + QA0=>qa05, QB0=>qb05, QA1=>qa15, QB1=>qb15); + + Inst_IDDRX2D_0_4: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t4, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa04, QB0=>qb04, QA1=>qa14, QB1=>qb14); + + Inst_IDDRX2D_0_3: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t3, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa03, QB0=>qb03, QA1=>qa13, QB1=>qb13); + + Inst_IDDRX2D_0_2: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t2, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa02, QB0=>qb02, QA1=>qa12, QB1=>qb12); + + Inst_IDDRX2D_0_1: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t1, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa01, QB0=>qb01, QA1=>qa11, QB1=>qb11); + + Inst_IDDRX2D_0_0: IDDRX2D + generic map (DELAYMODE=> "CENTERED", SCLKLATENCY=> 1) + port map (D=>datain_t0, SCLK=>clkok, ECLK=>clkos, + ECLKDQSR=>eclkdqsr0, DDRLAT=>ddrlat0, DDRCLKPOL=>ddrclkpol0, + QA0=>qa00, QB0=>qb00, QA1=>qa10, QB1=>qb10); + + Inst4_DQSBUFD1: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_1, SCLK=>clkok, READ=>reset_1, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_1, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw1, + DDRCLKPOL=>ddrclkpol1, PRMBDET=>prmbdet1, + DATAVALID=>datavalid1, DDRLAT=>ddrlat1, ECLKDQSR=>eclkdqsr1, + DQCLK0=>dqclk01, DQCLK1=>dqclk11); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + Inst4_DQSBUFD0: DQSBUFD + generic map (NRZMODE=> "DISABLED", DYNDEL_VAL=> 0, DYNDEL_CNTL=> "DYNAMIC", + DYNDEL_TYPE=> "NORMAL") + port map (DQSI=>buf_clk_0, SCLK=>clkok, READ=>reset_0, + DQSDEL=>dqsdel, ECLK=>clkos, ECLKW=>clkos, RST=>reset_0, + DYNDELPOL=>scuba_vlo, DYNDELAY6=>scuba_vlo, + DYNDELAY5=>scuba_vlo, DYNDELAY4=>scuba_vlo, + DYNDELAY3=>scuba_vlo, DYNDELAY2=>scuba_vlo, + DYNDELAY1=>scuba_vlo, DYNDELAY0=>scuba_vlo, DQSW=>dqsw0, + DDRCLKPOL=>ddrclkpol0, PRMBDET=>prmbdet0, + DATAVALID=>datavalid0, DDRLAT=>ddrlat0, ECLKDQSR=>eclkdqsr0, + DQCLK0=>dqclk00, DQCLK1=>dqclk10); + + Inst3_DQSDLLB: DQSDLLB + generic map (LOCK_SENSITIVITY=> "LOW") + port map (CLK=>clkos, RST=>dqsdll_reset, + UDDCNTLN=>dqsdll_uddcntln, LOCK=>dqsdll_lock, DQSDEL=>dqsdel); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + Inst2_CLKDIVB: CLKDIVB + port map (CLKI=>eclk, RST=>clkdiv_reset, RELEASE=>scuba_vhi, + CDIV1=>cdiv1, CDIV2=>clkok, CDIV4=>cdiv4, CDIV8=>cdiv8); + + Inst1_IB1: IB + port map (I=>clk_1, O=>buf_clk_1); + + Inst1_IB0: IB + port map (I=>clk_0, O=>buf_clk_0); + + q_1(19) <= qb19; + q_1(18) <= qb18; + q_1(17) <= qb17; + q_1(16) <= qb16; + q_1(15) <= qb15; + q_1(14) <= qa19; + q_1(13) <= qa18; + q_1(12) <= qa17; + q_1(11) <= qa16; + q_1(10) <= qa15; + q_1(9) <= qb09; + q_1(8) <= qb08; + q_1(7) <= qb07; + q_1(6) <= qb06; + q_1(5) <= qb05; + q_1(4) <= qa09; + q_1(3) <= qa08; + q_1(2) <= qa07; + q_1(1) <= qa06; + q_1(0) <= qa05; + datain_t9 <= datain_1i_t4; + datain_t8 <= datain_1i_t3; + datain_t7 <= datain_1i_t2; + datain_t6 <= datain_1i_t1; + datain_t5 <= datain_1i_t0; + q_0(19) <= qb14; + q_0(18) <= qb13; + q_0(17) <= qb12; + q_0(16) <= qb11; + q_0(15) <= qb10; + q_0(14) <= qa14; + q_0(13) <= qa13; + q_0(12) <= qa12; + q_0(11) <= qa11; + q_0(10) <= qa10; + q_0(9) <= qb04; + q_0(8) <= qb03; + q_0(7) <= qb02; + q_0(6) <= qb01; + q_0(5) <= qb00; + q_0(4) <= qa04; + q_0(3) <= qa03; + q_0(2) <= qa02; + q_0(1) <= qa01; + q_0(0) <= qa00; + datain_t4 <= datain_0i_t4; + datain_t3 <= datain_0i_t3; + datain_t2 <= datain_0i_t2; + datain_t1 <= datain_0i_t1; + datain_t0 <= datain_0i_t0; + dqsdll_uddcntln <= scuba_vhi; + dqsdll_reset <= scuba_vhi; + clkos <= eclk; + sclk_t <= clkok; + sclk <= sclk_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of adc_ddr_generic is + for Structure + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:IB use entity ecp3.IB(V); end for; + for all:CLKDIVB use entity ecp3.CLKDIVB(V); end for; + for all:IDDRX2D use entity ecp3.IDDRX2D(V); end for; + for all:DQSBUFD use entity ecp3.DQSBUFD(V); end for; + for all:DQSDLLB use entity ecp3.DQSDLLB(V); end for; + for all:DELAYC use entity ecp3.DELAYC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/fifo_adc_48to48_dc.ipx b/nxyter/cores/fifo_adc_48to48_dc.ipx new file mode 100644 index 0000000..aef5a3b --- /dev/null +++ b/nxyter/cores/fifo_adc_48to48_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_adc_48to48_dc.lpc b/nxyter/cores/fifo_adc_48to48_dc.lpc new file mode 100644 index 0000000..b41f15b --- /dev/null +++ b/nxyter/cores/fifo_adc_48to48_dc.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=fifo_adc_48to48_dc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=11/24/2013 +Time=18:14:05 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=4 +Width=48 +RDepth=4 +RWidth=48 +regout=1 +CtrlByRdEn=1 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/nxyter/cores/fifo_adc_48to48_dc.vhd b/nxyter/cores/fifo_adc_48to48_dc.vhd new file mode 100644 index 0000000..d6823b9 --- /dev/null +++ b/nxyter/cores/fifo_adc_48to48_dc.vhd @@ -0,0 +1,889 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.4 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 48 -depth 4 -rdata_width 48 -regout -pe -1 -pf -1 -e + +-- Sun Nov 24 18:14:05 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_adc_48to48_dc is + port ( + Data: in std_logic_vector(47 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(47 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_adc_48to48_dc; + +architecture Structure of fifo_adc_48to48_dc is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal ffidata_0: std_logic; + signal ffidata_1: std_logic; + signal ffidata_2: std_logic; + signal ffidata_3: std_logic; + signal ffidata_4: std_logic; + signal ffidata_5: std_logic; + signal ffidata_6: std_logic; + signal ffidata_7: std_logic; + signal ffidata_8: std_logic; + signal ffidata_9: std_logic; + signal ffidata_10: std_logic; + signal ffidata_11: std_logic; + signal ffidata_12: std_logic; + signal ffidata_13: std_logic; + signal ffidata_14: std_logic; + signal ffidata_15: std_logic; + signal ffidata_16: std_logic; + signal ffidata_17: std_logic; + signal ffidata_18: std_logic; + signal ffidata_19: std_logic; + signal ffidata_20: std_logic; + signal ffidata_21: std_logic; + signal ffidata_22: std_logic; + signal ffidata_23: std_logic; + signal ffidata_24: std_logic; + signal ffidata_25: std_logic; + signal ffidata_26: std_logic; + signal ffidata_27: std_logic; + signal ffidata_28: std_logic; + signal ffidata_29: std_logic; + signal ffidata_30: std_logic; + signal ffidata_31: std_logic; + signal ffidata_32: std_logic; + signal ffidata_33: std_logic; + signal ffidata_34: std_logic; + signal ffidata_35: std_logic; + signal ffidata_36: std_logic; + signal ffidata_37: std_logic; + signal ffidata_38: std_logic; + signal ffidata_39: std_logic; + signal ffidata_40: std_logic; + signal ffidata_41: std_logic; + signal ffidata_42: std_logic; + signal ffidata_43: std_logic; + signal ffidata_44: std_logic; + signal ffidata_45: std_logic; + signal ffidata_46: std_logic; + signal ffidata_47: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal co1: std_logic; + signal wcount_2: std_logic; + signal co0: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal co1_1: std_logic; + signal rcount_2: std_logic; + signal co0_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); + end component; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute RESETMODE : string; + attribute GSR : string; + attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_adc_48to48_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; + attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_adc_48to48_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; + attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t6: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t5: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t4: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t3: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t2: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t0: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r1); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0); + + LUT4_5: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w1); + + LUT4_4: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0); + + LUT4_3: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_1: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>Data(32), + DI33=>Data(33), DI34=>Data(34), DI35=>Data(35), ADW0=>wptr_0, + ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo, + ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo, + ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi, + BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, + CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo, + CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo, + ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, + ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, + ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, + CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, + DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, + DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24, + DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27, + DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30, + DO13=>ffidata_31, DO14=>ffidata_32, DO15=>ffidata_33, + DO16=>ffidata_34, DO17=>ffidata_35, DO18=>ffidata_0, + DO19=>ffidata_1, DO20=>ffidata_2, DO21=>ffidata_3, + DO22=>ffidata_4, DO23=>ffidata_5, DO24=>ffidata_6, + DO25=>ffidata_7, DO26=>ffidata_8, DO27=>ffidata_9, + DO28=>ffidata_10, DO29=>ffidata_11, DO30=>ffidata_12, + DO31=>ffidata_13, DO32=>ffidata_14, DO33=>ffidata_15, + DO34=>ffidata_16, DO35=>ffidata_17); + + pdp_ram_0_1_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), + DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), + DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), + DI11=>Data(47), DI12=>scuba_vlo, DI13=>scuba_vlo, + DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo, + DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo, + DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo, + DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo, + DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo, + DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo, + DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, + DI35=>scuba_vlo, ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo, + ADW3=>scuba_vlo, ADW4=>scuba_vlo, ADW5=>scuba_vlo, + ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo, + BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi, + BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi, + CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo, + ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo, + ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, + ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open, + DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open, + DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, + DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, + DO18=>ffidata_36, DO19=>ffidata_37, DO20=>ffidata_38, + DO21=>ffidata_39, DO22=>ffidata_40, DO23=>ffidata_41, + DO24=>ffidata_42, DO25=>ffidata_43, DO26=>ffidata_44, + DO27=>ffidata_45, DO28=>ffidata_46, DO29=>ffidata_47, + DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, + DO35=>open); + + FF_79: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_78: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_77: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_76: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_75: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_74: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_73: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_72: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_71: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_70: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_69: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_68: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_67: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_66: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_65: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_64: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_63: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_62: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_61: FD1P3DX + port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0)); + + FF_60: FD1P3DX + port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1)); + + FF_59: FD1P3DX + port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2)); + + FF_58: FD1P3DX + port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3)); + + FF_57: FD1P3DX + port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4)); + + FF_56: FD1P3DX + port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5)); + + FF_55: FD1P3DX + port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6)); + + FF_54: FD1P3DX + port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7)); + + FF_53: FD1P3DX + port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8)); + + FF_52: FD1P3DX + port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9)); + + FF_51: FD1P3DX + port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_50: FD1P3DX + port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_49: FD1P3DX + port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_48: FD1P3DX + port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_47: FD1P3DX + port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_46: FD1P3DX + port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_45: FD1P3DX + port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(16)); + + FF_44: FD1P3DX + port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(17)); + + FF_43: FD1P3DX + port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(18)); + + FF_42: FD1P3DX + port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(19)); + + FF_41: FD1P3DX + port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(20)); + + FF_40: FD1P3DX + port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(21)); + + FF_39: FD1P3DX + port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(22)); + + FF_38: FD1P3DX + port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(23)); + + FF_37: FD1P3DX + port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(24)); + + FF_36: FD1P3DX + port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(25)); + + FF_35: FD1P3DX + port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(26)); + + FF_34: FD1P3DX + port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(27)); + + FF_33: FD1P3DX + port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(28)); + + FF_32: FD1P3DX + port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(29)); + + FF_31: FD1P3DX + port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(30)); + + FF_30: FD1P3DX + port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(31)); + + FF_29: FD1P3DX + port map (D=>ffidata_32, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(32)); + + FF_28: FD1P3DX + port map (D=>ffidata_33, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(33)); + + FF_27: FD1P3DX + port map (D=>ffidata_34, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(34)); + + FF_26: FD1P3DX + port map (D=>ffidata_35, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(35)); + + FF_25: FD1P3DX + port map (D=>ffidata_36, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(36)); + + FF_24: FD1P3DX + port map (D=>ffidata_37, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(37)); + + FF_23: FD1P3DX + port map (D=>ffidata_38, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(38)); + + FF_22: FD1P3DX + port map (D=>ffidata_39, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(39)); + + FF_21: FD1P3DX + port map (D=>ffidata_40, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(40)); + + FF_20: FD1P3DX + port map (D=>ffidata_41, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(41)); + + FF_19: FD1P3DX + port map (D=>ffidata_42, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(42)); + + FF_18: FD1P3DX + port map (D=>ffidata_43, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(43)); + + FF_17: FD1P3DX + port map (D=>ffidata_44, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(44)); + + FF_16: FD1P3DX + port map (D=>ffidata_45, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(45)); + + FF_15: FD1P3DX + port map (D=>ffidata_46, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(46)); + + FF_14: FD1P3DX + port map (D=>ffidata_47, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(47)); + + FF_13: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_12: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_11: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_10: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_9: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_8: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_7: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_6: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_5: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_4: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_3: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_2: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_1: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1, + NC0=>iwcount_2, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1, + NC0=>ircount_2, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_adc_48to48_dc is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/cores/pll_adc_sampling_clk.ipx b/nxyter/cores/pll_adc_sampling_clk.ipx new file mode 100644 index 0000000..d4b6461 --- /dev/null +++ b/nxyter/cores/pll_adc_sampling_clk.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/nxyter/cores/pll_adc_sampling_clk.lpc b/nxyter/cores/pll_adc_sampling_clk.lpc new file mode 100644 index 0000000..40369a6 --- /dev/null +++ b/nxyter/cores/pll_adc_sampling_clk.lpc @@ -0,0 +1,66 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.3 +ModuleName=pll_adc_sampling_clk +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=10/19/2013 +Time=21:31:09 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=31.25 +Div=1 +ClkOPBp=0 +Post=32 +U_OFrq=31.25 +OP_Tol=0.0 +OFrq=31.250000 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=Internal +Mult=1 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Dynamic +CLKOK_INPUT=CLKOS +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=1 +FINDELA=0 +VcoRate= +Bandwidth=3.424318 +;DelayControl=No +EnCLKOS=1 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 diff --git a/nxyter/cores/pll_adc_sampling_clk.vhd b/nxyter/cores/pll_adc_sampling_clk.vhd new file mode 100644 index 0000000..12fb25d --- /dev/null +++ b/nxyter/cores/pll_adc_sampling_clk.vhd @@ -0,0 +1,121 @@ +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.3 +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -n pll_adc_sampling_clk -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 31.25 -phase_cntl DYNAMIC -fclkop 31.25 -fclkop_tol 0.0 -fb_mode INTERNAL -duty50 -noclkok -use_rst -noclkok2 -bw -e + +-- Sat Oct 19 21:31:09 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_adc_sampling_clk is + port ( + CLK: in std_logic; + RESET: in std_logic; + FINEDELB0: in std_logic; + FINEDELB1: in std_logic; + FINEDELB2: in std_logic; + FINEDELB3: in std_logic; + DPHASE0: in std_logic; + DPHASE1: in std_logic; + DPHASE2: in std_logic; + DPHASE3: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_adc_sampling_clk : entity is true; +end pll_adc_sampling_clk; + +architecture Structure of pll_adc_sampling_clk is + + -- internal signal declarations + signal CLKOS_t: std_logic; + signal CLKOP_t: std_logic; + signal DPHASE3_inv: std_logic; + signal CLKFB_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKOS : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "31.250000"; + attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "31.250000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "31.250000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + INV_0: INV + port map (A=>DPHASE3, Z=>DPHASE3_inv); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "DYNAMIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 32, CLKFB_DIV=> 1, CLKI_DIV=> 1, + FIN=> "31.250000") + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, + WRDEL=>scuba_vlo, DRPAI3=>DPHASE3, DRPAI2=>DPHASE2, + DRPAI1=>DPHASE1, DRPAI0=>DPHASE0, DFPAI3=>DPHASE3_inv, + DFPAI2=>DPHASE2, DFPAI1=>DPHASE1, DFPAI0=>DPHASE0, + FDA3=>FINEDELB3, FDA2=>FINEDELB2, FDA1=>FINEDELB1, + FDA0=>FINEDELB0, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, CLKOK=>open, + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t); + + CLKOS <= CLKOS_t; + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_adc_sampling_clk is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd new file mode 100644 index 0000000..b83ea7b --- /dev/null +++ b/nxyter/source/adc_ad9228.vhd @@ -0,0 +1,529 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.nxyter_components.all; + +entity adc_ad9228 is + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_ADCDAT_IN : in std_logic; + RESTART_IN : in std_logic; + + ADC0_SCLK_IN : in std_logic; -- Sampling Clock ADC0 + ADC0_SCLK_OUT : out std_logic; + ADC0_DATA_A_IN : in std_logic; + ADC0_DATA_B_IN : in std_logic; + ADC0_DATA_C_IN : in std_logic; + ADC0_DATA_D_IN : in std_logic; + ADC0_DCLK_IN : in std_logic; -- Data Clock from ADC0 + ADC0_FCLK_IN : in std_logic; -- Frame Clock from ADC0 + + ADC1_SCLK_IN : in std_logic; -- Sampling Clock ADC1 + ADC1_SCLK_OUT : out std_logic; + ADC1_DATA_A_IN : in std_logic; + ADC1_DATA_B_IN : in std_logic; + ADC1_DATA_C_IN : in std_logic; + ADC1_DATA_D_IN : in std_logic; + ADC1_DCLK_IN : in std_logic; -- Data Clock from ADC1 + ADC1_FCLK_IN : in std_logic; -- Frame Clock from ADC1 + + ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_VALID_OUT : out std_logic; + + ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_VALID_OUT : out std_logic; + ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0); + ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end adc_ad9228; + +architecture Behavioral of adc_ad9228 is + + -- DDR Generic Handler + signal DDR_DATA_CLK : std_logic; + signal reset_0 : std_logic; + signal reset_1 : std_logic; + signal clkdiv_reset : std_logic; + signal q_0 : std_logic_vector(19 downto 0); + signal q_1 : std_logic_vector(19 downto 0); + + -- NotLock Counters + signal adc0_frame_notlocked_p : std_logic; + signal adc0_frame_notlocked : std_logic; + signal adc0_notlock_ctr : unsigned(7 downto 0); + signal adc0_bit_shift : unsigned(1 downto 0); + signal adc0_bit_shift_last : unsigned(1 downto 0); + signal adc0_bit_shift_change : std_logic; + + signal adc1_frame_notlocked_p : std_logic; + signal adc1_frame_notlocked : std_logic; + signal adc1_notlock_ctr : unsigned(7 downto 0); + signal adc1_bit_shift : unsigned(1 downto 0); + signal adc1_bit_shift_last : unsigned(1 downto 0); + signal adc1_bit_shift_change : std_logic; + + -- Merge Data + type q_map_t is array(0 to 4) of std_logic_vector(3 downto 0); + type adc_data_buf_t is array(0 to 4) of std_logic_vector(15 downto 0); + type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); + + signal adc0_data_buf : adc_data_buf_t; + signal adc0_frame_ctr : unsigned(3 downto 0); + signal adc0_frame_locked : std_logic; + + signal adc0_new_data_t : std_logic; + signal adc0_data_t : adc_data_t; + + signal adc1_data_buf : adc_data_buf_t; + signal adc1_frame_ctr : unsigned(3 downto 0); + signal adc1_frame_locked : std_logic; + + signal adc1_new_data_t : std_logic; + signal adc1_data_t : adc_data_t; + + -- Clock Transfer + signal adc0_fifo_empty : std_logic; + signal adc0_fifo_full : std_logic; + signal adc0_write_enable : std_logic; + signal adc0_read_enable : std_logic; + signal adc0_read_enable_t : std_logic; + signal adc0_read_enable_tt : std_logic; + signal adc0_fifo_reset : std_logic; + + signal adc1_fifo_empty : std_logic; + signal adc1_fifo_full : std_logic; + signal adc1_write_enable : std_logic; + signal adc1_read_enable : std_logic; + signal adc1_read_enable_t : std_logic; + signal adc1_read_enable_tt : std_logic; + signal adc1_fifo_reset : std_logic; + + -- Output + signal adc0_data_valid_o : std_logic; + signal adc0_data_f : adc_data_t; + signal adc0_data_o : adc_data_t; + + signal adc1_data_valid_o : std_logic; + signal adc1_data_f : adc_data_t; + signal adc1_data_o : adc_data_t; + +begin + + -- DEBUG + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= DDR_DATA_CLK; + DEBUG_OUT(2) <= adc0_bit_shift_change; + DEBUG_OUT(3) <= adc0_write_enable; + DEBUG_OUT(4) <= adc0_fifo_full; + DEBUG_OUT(5) <= adc0_fifo_empty; + DEBUG_OUT(6) <= adc0_frame_locked; + DEBUG_OUT(7) <= adc0_new_data_t; + DEBUG_OUT(8) <= adc0_read_enable; + DEBUG_OUT(9) <= adc0_read_enable_t; + DEBUG_OUT(10) <= adc0_read_enable_tt; + DEBUG_OUT(11) <= adc0_data_valid_o; + DEBUG_OUT(15 downto 12) <= adc0_data_f(0)(3 downto 0); + + reset_0 <= RESET_IN or RESTART_IN; + reset_1 <= RESET_IN or RESTART_IN; + clkdiv_reset <= RESET_IN; + + ----------------------------------------------------------------------------- + + adc_ddr_generic_1: adc_ddr_generic + port map ( + clk_0 => ADC0_DCLK_IN, + clk_1 => ADC1_DCLK_IN, + clkdiv_reset => clkdiv_reset, + eclk => CLK_ADCDAT_IN, + reset_0 => reset_0, + reset_1 => reset_1, + sclk => DDR_DATA_CLK, + + datain_0(0) => ADC0_DATA_A_IN, + datain_0(1) => ADC0_DATA_B_IN, + datain_0(2) => ADC0_DATA_C_IN, + datain_0(3) => ADC0_DATA_D_IN, + datain_0(4) => ADC0_FCLK_IN, + + datain_1(0) => ADC1_DATA_A_IN, + datain_1(1) => ADC1_DATA_B_IN, + datain_1(2) => ADC1_DATA_C_IN, + datain_1(3) => ADC1_DATA_D_IN, + datain_1(4) => ADC1_FCLK_IN, + + q_0 => q_0, + q_1 => q_1 + ); + + ----------------------------------------------------------------------------- + + PROC_MERGE_DATA0: process(DDR_DATA_CLK) + variable q_0_map : q_map_t; + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_IN = '1' or RESTART_IN = '1') then + for I in 0 to 3 loop + adc0_data_buf(I) <= (others => '0'); + end loop; + adc0_new_data_t <= '0'; + adc0_frame_ctr <= (others => '0'); + adc0_frame_locked <= '0'; + adc0_bit_shift <= "00"; + adc0_bit_shift_last <= "00"; + adc0_bit_shift_change <= '0'; + else + -- Remap DDR Output q_value + for I in 0 to 4 loop + q_0_map(I) := q_0(I + 0) & q_0(I + 5) & q_0(I + 10) & q_0(I + 15); + end loop; + + for I in 0 to 4 loop + adc0_data_buf(I)(3 downto 0) <= q_0_map(I); + adc0_data_buf(I)(15 downto 4) <= adc0_data_buf(I)(11 downto 0); + end loop; + + -- Test Frame Clock Pattern + adc0_new_data_t <= '0'; + case adc0_data_buf(4) is -- adc0_data_buf(4) is frame clock + when "0000111111000000" => + for I in 0 to 3 loop + adc0_data_t(I) <= adc0_data_buf(I)(11 downto 0); + end loop; + adc0_new_data_t <= '1'; + adc0_bit_shift <= "00"; + + when "0001111110000001" => + for I in 0 to 3 loop + adc0_data_t(I) <= adc0_data_buf(I)(12 downto 1); + end loop; + adc0_new_data_t <= '1'; + adc0_bit_shift <= "01"; + + when "0011111100000011" => + for I in 0 to 3 loop + adc0_data_t(I) <= adc0_data_buf(I)(13 downto 2); + end loop; + adc0_new_data_t <= '1'; + adc0_bit_shift <= "10"; + + when "0111111000000111" => + for I in 0 to 3 loop + adc0_data_t(I) <= adc0_data_buf(I)(14 downto 3); + end loop; + adc0_new_data_t <= '1'; + adc0_bit_shift <= "11"; + + when others => null; + + end case; + + -- ADC Lock Status + if (adc0_new_data_t = '1') then + adc0_frame_ctr <= (others => '0'); + adc0_frame_locked <= '1'; + elsif (adc0_frame_ctr < x"4") then + adc0_frame_ctr <= adc0_frame_ctr + 1; + adc0_frame_locked <= adc0_frame_locked; + else + adc0_frame_locked <= '0'; + end if; + + adc0_bit_shift_last <= adc0_bit_shift; + if (adc0_bit_shift /= adc0_bit_shift_last) then + adc0_bit_shift_change <= '1'; + else + adc0_bit_shift_change <= '0'; + end if; + + end if; + end if; + end process PROC_MERGE_DATA0; + + ----------------------------------------------------------------------------- + + PROC_MERGE_DATA1: process(DDR_DATA_CLK) + variable q_1_map : q_map_t; + begin + if (rising_edge(DDR_DATA_CLK)) then + if (RESET_IN = '1' or RESTART_IN = '1') then + for I in 0 to 3 loop + adc1_data_buf(I) <= (others => '0'); + end loop; + adc1_new_data_t <= '0'; + adc1_frame_ctr <= (others => '0'); + adc1_frame_locked <= '0'; + adc1_bit_shift <= "00"; + adc1_bit_shift_last <= "00"; + adc1_bit_shift_change <= '0'; + else + -- Remap DDR Output q_value + for I in 0 to 4 loop + q_1_map(I) := q_1(I + 0) & q_1(I + 5) & q_1(I + 10) & q_1(I + 15); + end loop; + + for I in 0 to 4 loop + adc1_data_buf(I)(3 downto 0) <= q_1_map(I); + adc1_data_buf(I)(15 downto 4) <= adc1_data_buf(I)(11 downto 0); + end loop; + + -- Test Frame Clock Pattern + adc1_new_data_t <= '0'; + case adc1_data_buf(4) is -- adc1_data_buf(4) is frame clock + when "0000111111000000" => + for I in 0 to 3 loop + adc1_data_t(I) <= adc1_data_buf(I)(11 downto 0); + end loop; + adc1_new_data_t <= '1'; + adc1_bit_shift <= "00"; + + when "0001111110000001" => + for I in 0 to 3 loop + adc1_data_t(I) <= adc1_data_buf(I)(12 downto 1); + end loop; + adc1_new_data_t <= '1'; + adc1_bit_shift <= "01"; + + when "0011111100000011" => + for I in 0 to 3 loop + adc1_data_t(I) <= adc1_data_buf(I)(13 downto 2); + end loop; + adc1_new_data_t <= '1'; + adc1_bit_shift <= "10"; + + when "0111111000000111" => + for I in 0 to 3 loop + adc1_data_t(I) <= adc1_data_buf(I)(14 downto 3); + end loop; + adc1_new_data_t <= '1'; + adc1_bit_shift <= "11"; + + when others => null; + + end case; + + -- ADC Lock Status + if (adc1_new_data_t = '1') then + adc1_frame_ctr <= (others => '0'); + adc1_frame_locked <= '1'; + elsif (adc1_frame_ctr < x"4") then + adc1_frame_ctr <= adc1_frame_ctr + 1; + adc1_frame_locked <= adc1_frame_locked; + else + adc1_frame_locked <= '0'; + end if; + + adc1_bit_shift_last <= adc1_bit_shift; + if (adc1_bit_shift /= adc1_bit_shift_last) then + adc1_bit_shift_change <= '1'; + else + adc1_bit_shift_change <= '0'; + end if; + + end if; + end if; + end process PROC_MERGE_DATA1; + + ----------------------------------------------------------------------------- + -- Tansfer to CLK_IN + ----------------------------------------------------------------------------- + + fifo_adc_48to48_dc_1: fifo_adc_48to48_dc + port map ( + Data(11 downto 0) => adc0_data_t(0), + Data(23 downto 12) => adc0_data_t(1), + Data(35 downto 24) => adc0_data_t(2), + Data(47 downto 36) => adc0_data_t(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc0_new_data_t, + RdEn => adc0_read_enable, + Reset => RESET_IN, + RPReset => adc0_fifo_reset, + Q(11 downto 0) => adc0_data_f(0), + Q(23 downto 12) => adc0_data_f(1), + Q(35 downto 24) => adc0_data_f(2), + Q(47 downto 36) => adc0_data_f(3), + Empty => adc0_fifo_empty, + Full => adc0_fifo_full + ); + adc0_fifo_reset <= RESTART_IN; + adc0_write_enable <= adc0_new_data_t and not adc0_fifo_full; + adc0_read_enable <= not adc0_fifo_empty; + + PROC_ADC0_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1' or RESTART_IN = '1') then + adc0_read_enable_t <= '0'; + adc0_read_enable_tt <= '0'; + for I in 0 to 3 loop + adc0_data_o(I) <= (others => '0'); + end loop; + adc0_data_valid_o <= '0'; + else + -- Read enable + adc0_read_enable_t <= adc0_read_enable; + adc0_read_enable_tt <= adc0_read_enable_t; + + if (adc0_read_enable_tt = '1') then + for I in 0 to 3 loop + adc0_data_o(I) <= adc0_data_f(I); + end loop; + adc0_data_valid_o <= '1'; + else + adc0_data_valid_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC0_FIFO_READ; + + ----------------------------------------------------------------------------- + + fifo_adc_48to48_dc_2: fifo_adc_48to48_dc + port map ( + Data(11 downto 0) => adc1_data_t(0), + Data(23 downto 12) => adc1_data_t(1), + Data(35 downto 24) => adc1_data_t(2), + Data(47 downto 36) => adc1_data_t(3), + WrClock => DDR_DATA_CLK, + RdClock => CLK_IN, + WrEn => adc1_new_data_t, + RdEn => adc1_read_enable, + Reset => RESET_IN, + RPReset => adc1_fifo_reset, + Q(11 downto 0) => adc1_data_f(0), + Q(23 downto 12) => adc1_data_f(1), + Q(35 downto 24) => adc1_data_f(2), + Q(47 downto 36) => adc1_data_f(3), + Empty => adc1_fifo_empty, + Full => adc1_fifo_full + ); + adc1_fifo_reset <= RESTART_IN; + adc1_write_enable <= adc1_new_data_t and not adc1_fifo_full; + adc1_read_enable <= not adc1_fifo_empty; + + PROC_ADC1_FIFO_READ: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1' or RESTART_IN = '1') then + adc1_read_enable_t <= '0'; + adc1_read_enable_tt <= '0'; + for I in 0 to 3 loop + adc1_data_o(I) <= (others => '0'); + end loop; + adc1_data_valid_o <= '0'; + else + -- Read enable + adc1_read_enable_t <= adc1_read_enable; + adc1_read_enable_tt <= adc1_read_enable_t; + + if (adc1_read_enable_tt = '1') then + for I in 0 to 3 loop + adc1_data_o(I) <= adc1_data_f(I); + end loop; + adc1_data_valid_o <= '1'; + else + adc1_data_valid_o <= '0'; + end if; + end if; + end if; + end process PROC_ADC1_FIFO_READ; + + ----------------------------------------------------------------------------- + -- Lock Monitor + ----------------------------------------------------------------------------- + + level_to_pulse_1: level_to_pulse + port map ( + CLK_IN => DDR_DATA_CLK, + RESET_IN => RESET_IN, + LEVEL_IN => not adc0_frame_locked, + PULSE_OUT => adc0_frame_notlocked_p + ); + + level_to_pulse_2: level_to_pulse + port map ( + CLK_IN => DDR_DATA_CLK, + RESET_IN => RESET_IN, + LEVEL_IN => not adc1_frame_locked, + PULSE_OUT => adc1_frame_notlocked_p + ); + + pulse_dtrans_1: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => RESET_IN, + PULSE_A_IN => adc0_frame_notlocked_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc0_frame_notlocked + ); + + pulse_dtrans_2: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => RESET_IN, + PULSE_A_IN => adc1_frame_notlocked_p, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc1_frame_notlocked + ); + + PROC_NOTLOCK_COUNTER: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + adc0_notlock_ctr <= (others => '0'); + adc1_notlock_ctr <= (others => '0'); + else + if (adc0_frame_notlocked = '1') then + adc0_notlock_ctr <= adc0_notlock_ctr + 1; + end if; + + if (adc1_frame_notlocked = '1') then + adc1_notlock_ctr <= adc1_notlock_ctr + 1; + end if; + end if; + end if; + end process PROC_NOTLOCK_COUNTER; + + -- Output + + ADC0_SCLK_OUT <= ADC0_SCLK_IN; + ADC1_SCLK_OUT <= ADC1_SCLK_IN; + + ADC0_DATA_A_OUT <= adc0_data_o(0); + ADC0_DATA_B_OUT <= adc0_data_o(1); + ADC0_DATA_C_OUT <= adc0_data_o(2); + ADC0_DATA_D_OUT <= adc0_data_o(3); + ADC0_DATA_VALID_OUT <= adc0_data_valid_o; + + ADC1_DATA_A_OUT <= adc1_data_o(0); + ADC1_DATA_B_OUT <= adc1_data_o(1); + ADC1_DATA_C_OUT <= adc1_data_o(2); + ADC1_DATA_D_OUT <= adc1_data_o(3); + ADC1_DATA_VALID_OUT <= adc1_data_valid_o; + + ADC0_NOTLOCK_COUNTER <= adc0_notlock_ctr; + ADC1_NOTLOCK_COUNTER <= adc1_notlock_ctr; + +end architecture; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 01ea1e1..569151d 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -5,7 +5,6 @@ use ieee.numeric_std.all; library work; use work.trb_net_std.all; use work.trb_net_components.all; -use work.trb3_components.all; use work.nxyter_components.all; entity nx_data_receiver is @@ -115,7 +114,7 @@ architecture Behavioral of nx_data_receiver is signal adc_clk_ok_last : std_logic; signal adc_reset_s : std_logic; signal adc_reset_ctr : unsigned(11 downto 0); - + -- Reset Handler signal r_wait_timer_init : unsigned(27 downto 0); signal r_wait_timer_done : std_logic; @@ -135,10 +134,11 @@ architecture Behavioral of nx_data_receiver is signal sampling_clk_reset : std_logic; signal adc_reset_p : std_logic; signal adc_reset : std_logic; + signal adc_reset_h : std_logic; signal data_handler_reset_p : std_logic; signal data_handler_reset : std_logic; signal reset_handler_counter : unsigned(15 downto 0); - + ----------------------------------------------------------------------------- -- CLK_IN Domain ----------------------------------------------------------------------------- @@ -181,6 +181,8 @@ architecture Behavioral of nx_data_receiver is signal adc_data_t : std_logic_vector(11 downto 0); signal adc_new_data : std_logic; signal adc_new_data_ctr : unsigned(3 downto 0); + signal adc_notlock_ctr : unsigned(7 downto 0); + signal ADC_DEBUG : std_logic_vector(15 downto 0); -- ADC TEST INPUT DATA signal adc_input_error_enable : std_logic; @@ -208,6 +210,13 @@ architecture Behavioral of nx_data_receiver is signal pll_adc_sample_clk_dphase : std_logic_vector(3 downto 0); signal pll_adc_sample_clk_finedelb : std_logic_vector(3 downto 0); + + -- Rate Calculations + signal nx_frame_rate_ctr : unsigned(27 downto 0); + signal nx_frame_rate : unsigned(27 downto 0); + signal adc_frame_rate_ctr : unsigned(27 downto 0); + signal adc_frame_rate : unsigned(27 downto 0); + signal rate_timer_ctr : unsigned(27 downto 0); -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -222,6 +231,8 @@ architecture Behavioral of nx_data_receiver is signal reset_adc_handler_r : std_logic; signal reset_handler_counter_clear : std_logic; signal adc_bit_shift : unsigned(3 downto 0); + signal johnson_counter_sync_r : unsigned(1 downto 0); + signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0); begin @@ -251,18 +262,14 @@ begin begin case debug_adc is when "01" => - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= nx_new_frame; - DEBUG_OUT(2) <= TRIGGER_IN; - DEBUG_OUT(3) <= adc_data_valid; - DEBUG_OUT(15 downto 4) <= adc_data; + DEBUG_OUT <= ADC_DEBUG; when "10" => DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= '0'; + DEBUG_OUT(1) <= nx_new_frame; DEBUG_OUT(2) <= TRIGGER_IN; DEBUG_OUT(3) <= adc_data_valid; - DEBUG_OUT(15 downto 4) <= test_adc_data; + DEBUG_OUT(15 downto 4) <= adc_data; when "11" => DEBUG_OUT(0) <= CLK_IN; @@ -338,7 +345,11 @@ begin ----------------------------------------------------------------------------- pll_adc_sampling_clk_reset <= sampling_clk_reset; - + + -- Shift dphase show 0 as optimal value + pll_adc_sample_clk_dphase <= + std_logic_vector(pll_adc_sample_clk_dphase_r - 1); + pll_adc_sampling_clk_2: pll_adc_sampling_clk port map ( CLK => adc_sampling_clk, @@ -377,41 +388,50 @@ begin end if; end if; end process PROC_PLL_LOCK_COUNTER; - - adc_ad9222_1: entity work.adc_ad9222 - generic map ( - CHANNELS => 4, - DEVICES => 2, - RESOLUTION => 12 - ) + + + adc_reset_h <= RESET_IN or adc_reset; + adc_ad9228_1: adc_ad9228 port map ( - CLK => CLK_IN, - CLK_ADCREF => pll_adc_sampling_clk_o, - CLK_ADCDAT => ADC_CLK_DAT_IN, - RESTART_IN => adc_reset, - ADCCLK_OUT => ADC_SAMPLE_CLK_OUT, - - ADC_DATA(0) => ADC_NX_IN(0), - ADC_DATA(1) => ADC_B_IN(0), - ADC_DATA(2) => ADC_A_IN(0), - ADC_DATA(3) => ADC_D_IN(0), - - ADC_DATA(4) => ADC_NX_IN(1), - ADC_DATA(5) => ADC_A_IN(1), - ADC_DATA(6) => ADC_B_IN(1), - ADC_DATA(7) => ADC_D_IN(1), - - ADC_DCO => ADC_DCLK_IN, - ADC_FCO => ADC_FCLK_IN, - - DATA_OUT(11 downto 0) => adc_data, - DATA_OUT(23 downto 12) => test_adc_data, - DATA_OUT(95 downto 24) => open, + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + CLK_ADCDAT_IN => ADC_CLK_DAT_IN, + RESTART_IN => adc_reset_h, + + ADC0_SCLK_IN => pll_adc_sampling_clk_o, + ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT, + ADC0_DATA_A_IN => ADC_NX_IN(0), + ADC0_DATA_B_IN => ADC_B_IN(0), + ADC0_DATA_C_IN => ADC_A_IN(0), + ADC0_DATA_D_IN => ADC_D_IN(0), + ADC0_DCLK_IN => ADC_DCLK_IN(0), + ADC0_FCLK_IN => ADC_FCLK_IN(0), + + ADC1_SCLK_IN => pll_adc_sampling_clk_o, + ADC1_SCLK_OUT => open, + ADC1_DATA_A_IN => ADC_NX_IN(1), + ADC1_DATA_B_IN => ADC_A_IN(1), + ADC1_DATA_C_IN => ADC_B_IN(1), + ADC1_DATA_D_IN => ADC_D_IN(1), + ADC1_DCLK_IN => ADC_DCLK_IN(1), + ADC1_FCLK_IN => ADC_FCLK_IN(1), + + ADC0_DATA_A_OUT => adc_data, + ADC0_DATA_B_OUT => test_adc_data, + ADC0_DATA_C_OUT => open, + ADC0_DATA_D_OUT => open, + ADC0_DATA_VALID_OUT => adc_data_valid, + + ADC1_DATA_A_OUT => open, + ADC1_DATA_B_OUT => open, + ADC1_DATA_C_OUT => open, + ADC1_DATA_D_OUT => open, + ADC1_DATA_VALID_OUT => open, + + ADC0_NOTLOCK_COUNTER => adc_notlock_ctr, + ADC1_NOTLOCK_COUNTER => open, - FCO_OUT => open, - DATA_VALID_OUT(0) => adc_data_valid, - DATA_VALID_OUT(1) => open, - DEBUG => open + DEBUG_OUT => ADC_DEBUG ); nx_timer_1: nx_timer @@ -732,6 +752,8 @@ begin adc_sampling_clk <= johnson_ff_0; end process PROC_ADC_SAMPLING_CLK_GENERATOR; + -- Adjust johnson_counter_sync to show optimal value at 0 + johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r + 3); PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN) variable adc_clk_state : std_logic_vector(1 downto 0); begin @@ -1031,6 +1053,50 @@ begin end if; end process PROC_OUTPUT_HANDLER; + ----------------------------------------------------------------------------- + -- Rate Counters + ----------------------------------------------------------------------------- + PROC_RATE_COUNTER: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + nx_frame_rate_ctr <= (others => '0'); + nx_frame_rate <= (others => '0'); + adc_frame_rate_ctr <= (others => '0'); + adc_frame_rate <= (others => '0'); + rate_timer_ctr <= (others => '0'); + else + if (rate_timer_ctr < x"5f5e100") then + rate_timer_ctr <= rate_timer_ctr + 1; + + if (nx_fifo_data_valid = '1') then + nx_frame_rate_ctr <= nx_frame_rate_ctr + 1; + end if; + + if (adc_data_valid = '1') then + adc_frame_rate_ctr <= adc_frame_rate_ctr + 1; + end if; + else + rate_timer_ctr <= (others => '0'); + nx_frame_rate <= nx_frame_rate_ctr; + adc_frame_rate <= adc_frame_rate_ctr; + + if (nx_fifo_data_valid = '0') then + nx_frame_rate_ctr <= (others => '0'); + else + nx_frame_rate_ctr <= x"000_0001"; + end if; + + if (adc_data_valid = '0') then + adc_frame_rate_ctr <= (others => '0'); + else + adc_frame_rate_ctr <= x"000_0001"; + end if; + end if; + end if; + end if; + end process PROC_RATE_COUNTER; + ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- @@ -1049,11 +1115,11 @@ begin fifo_reset_r <= '0'; debug_adc <= (others => '0'); adc_input_error_enable <= '0'; - johnson_counter_sync <= "01"; - pll_adc_sample_clk_dphase <= (others => '0'); + johnson_counter_sync_r <= "00"; + pll_adc_sample_clk_dphase_r <= x"0"; pll_adc_sample_clk_finedelb <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; - nx_fifo_delay <= x"7"; + nx_fifo_delay <= x"8"; reset_adc_handler_r <= '0'; reset_handler_counter_clear <= '0'; adc_bit_shift <= x"0"; @@ -1106,12 +1172,13 @@ begin slv_ack_o <= '1'; when x"0005" => - slv_data_out_o(1 downto 0) <= johnson_counter_sync; + slv_data_out_o(1 downto 0) <= johnson_counter_sync_r; slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; when x"0006" => - slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_dphase; + slv_data_out_o(3 downto 0) <= + std_logic_vector(pll_adc_sample_clk_dphase_r); slv_data_out_o(31 downto 4) <= (others => '0'); slv_ack_o <= '1'; @@ -1154,8 +1221,24 @@ begin slv_data_out_o(3 downto 0) <= std_logic_vector(adc_bit_shift); slv_data_out_o(31 downto 4) <= (others => '0'); slv_ack_o <= '1'; - + when x"000f" => + slv_data_out_o(7 downto 0) <= + std_logic_vector(adc_notlock_ctr); + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0010" => + slv_data_out_o(27 downto 0) <= std_logic_vector(nx_frame_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0011" => + slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0012" => slv_data_out_o(1 downto 0) <= debug_adc; slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; @@ -1179,12 +1262,13 @@ begin slv_ack_o <= '1'; when x"0005" => - johnson_counter_sync <= SLV_DATA_IN(1 downto 0); + johnson_counter_sync_r <= SLV_DATA_IN(1 downto 0); reset_adc_handler_r <= '1'; slv_ack_o <= '1'; when x"0006" => - pll_adc_sample_clk_dphase <= SLV_DATA_IN(3 downto 0); + pll_adc_sample_clk_dphase_r <= + unsigned(SLV_DATA_IN(3 downto 0)); reset_adc_handler_r <= '1'; slv_ack_o <= '1'; @@ -1214,8 +1298,8 @@ begin adc_bit_shift <= unsigned(SLV_DATA_IN(3 downto 0)); slv_ack_o <= '1'; - - when x"000f" => + + when x"0012" => debug_adc <= SLV_DATA_IN(1 downto 0); slv_ack_o <= '1'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 41bfb51..3984f2f 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -207,6 +207,84 @@ component adc_spi_readbyte ); end component; +------------------------------------------------------------------------------- +-- ADC Data Handler +------------------------------------------------------------------------------- + +component adc_ad9228 + port ( + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_ADCDAT_IN : in std_logic; + RESTART_IN : in std_logic; + + ADC0_SCLK_IN : in std_logic; + ADC0_SCLK_OUT : out std_logic; + ADC0_DATA_A_IN : in std_logic; + ADC0_DATA_B_IN : in std_logic; + ADC0_DATA_C_IN : in std_logic; + ADC0_DATA_D_IN : in std_logic; + ADC0_DCLK_IN : in std_logic; + ADC0_FCLK_IN : in std_logic; + + ADC1_SCLK_IN : in std_logic; + ADC1_SCLK_OUT : out std_logic; + ADC1_DATA_A_IN : in std_logic; + ADC1_DATA_B_IN : in std_logic; + ADC1_DATA_C_IN : in std_logic; + ADC1_DATA_D_IN : in std_logic; + ADC1_DCLK_IN : in std_logic; + ADC1_FCLK_IN : in std_logic; + + ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_VALID_OUT : out std_logic; + + ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_VALID_OUT : out std_logic; + + ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0); + ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); +end component; + +component adc_ddr_generic + port ( + clk_0 : in std_logic; + clk_1 : in std_logic; + clkdiv_reset : in std_logic; + eclk : in std_logic; + reset_0 : in std_logic; + reset_1 : in std_logic; + sclk : out std_logic; + datain_0 : in std_logic_vector(4 downto 0); + datain_1 : in std_logic_vector(4 downto 0); + q_0 : out std_logic_vector(19 downto 0); + q_1 : out std_logic_vector(19 downto 0) + ); +end component; + +component fifo_adc_48to48_dc + port ( + Data : in std_logic_vector(47 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(47 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end component; + ------------------------------------------------------------------------------- -- TRBNet Registers ------------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 185b23b..fc96bfb 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -238,7 +238,7 @@ begin PORT_ADDR_MASK => ( 0 => 4, -- NX Control Handler 1 => 0, -- I2C master - 2 => 4, -- Data Receiver + 2 => 5, -- Data Receiver 3 => 3, -- Data Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 2b238fc..6ca2cab 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -149,6 +149,8 @@ add_file -vhdl -lib "work" "cores/fifo_ts_32to32_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_44_data_delay.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" add_file -vhdl -lib "work" "cores/ram_dp_128x32.vhd" +add_file -vhdl -lib "work" "cores/adc_ddr_generic.vhd" +add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" @@ -183,6 +185,7 @@ add_file -vhdl -lib "work" "source/nx_i2c_readbyte.vhd" add_file -vhdl -lib "work" "source/adc_spi_master.vhd" add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd" add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd" +add_file -vhdl -lib "work" "source/adc_ad9228.vhd" add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd" add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd" @@ -190,9 +193,9 @@ add_file -vhdl -lib "work" "source/nx_trigger_handler.vhd" add_file -vhdl -lib "work" "source/nx_timestamp_sim.vhd" # Needed by ADC9222 Entity -add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" -add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd" -add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd" -add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd" -add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd" -add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd" +#add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" +#add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd" +#add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200.vhd" +#add_file -vhdl -lib "work" "../base/cores/pll_adc12bit.vhd" +#add_file -vhdl -lib "work" "../base/cores/fifo_32x512.vhd" +#add_file -vhdl -lib "work" "../base/code/adc_ad9222.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index a98ad15..e2886ba 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -39,7 +39,7 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz; - USE PRIMARY NET "nx_main_clk_*"; + USE PRIMARY NET "nx_main_clk_c"; USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; @@ -61,12 +61,12 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; # Relax some of the timing constraints ################################################################# -MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; +#MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; +#MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 20 ns; -MULTICYCLE FROM CLKNET "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; -MULTICYCLE FROM CLKNET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; +MULTICYCLE FROM CLKNET "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9228_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; +MULTICYCLE FROM CLKNET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9228_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; #MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/pulse_dtrans_2/pulse_async_trans_1/pulse_ff_1" 5 ns; MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/timestamp_sync_x" 5 ns; -- 2.43.0