From 7930f38b2dc36dc44c7d48564a19938dfb4c88a7 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Fri, 12 Feb 2021 14:41:13 +0100 Subject: [PATCH] fix for data_ready signal and resulting 50% data acceptance. additional signal init values and reset for state machine --- src/DLM_CTS_generator.vhd | 60 +++++++++++++++++++++------------------ 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/src/DLM_CTS_generator.vhd b/src/DLM_CTS_generator.vhd index a9f2779..d91194c 100644 --- a/src/DLM_CTS_generator.vhd +++ b/src/DLM_CTS_generator.vhd @@ -70,15 +70,15 @@ architecture DLM_CTS_generator_arch of DLM_CTS_generator is signal subtrigger : std_logic_vector(7 downto 0) := x"00"; signal status_reg : std_logic_vector(1 downto 0); - signal error_reg : std_logic; + signal error_reg : std_logic := '0'; - signal trg_sync_i : std_logic; - signal last_trg_sync_i : std_logic; + signal trg_sync_i : std_logic := '0'; + signal last_trg_sync_i : std_logic := '0'; signal dlm_msg_i : std_logic_vector(7 downto 0); signal last_DLM_in : std_logic_vector(7 downto 0); - signal config_rdo_disable_i : std_logic; + signal config_rdo_disable_i : std_logic := '0'; signal rec_counter_i : unsigned(31 downto 0) := (others => '0'); signal act_counter_i : unsigned(31 downto 0) := (others => '0'); @@ -108,7 +108,7 @@ begin begin wait until rising_edge(CLK); if RESET_IN = '1' then - dlm_ready <= '1'; + dlm_ready <= '0'; trg_sync_i <= '0'; last_trg_sync_i <= '0'; last_DLM_in <= (others => '0'); @@ -154,32 +154,38 @@ begin PROC_RDO : process begin wait until rising_edge(CLK); - WRITE_OUT <= '0'; - FINISHED_OUT <= config_rdo_disable_i; - case rdostate is - when RDO_IDLE => - if TRIGGER_IN = '1' and config_rdo_disable_i = '0' then - if dlm_ready = '0' then - rdostate <= RDO_WAIT; - else - rdostate <= RDO_WRITE; + WRITE_OUT <= '0'; + FINISHED_OUT <= config_rdo_disable_i; + if RESET_IN = '1' then + rdostate <= RDO_IDLE; + else + case rdostate is + when RDO_IDLE => + if TRIGGER_IN = '1' and config_rdo_disable_i = '0' then + if dlm_ready = '0' then + rdostate <= RDO_WAIT; + else + rdostate <= RDO_WRITE; + end if; end if; - end if; - when RDO_WAIT => - if dlm_ready = '1' then - rdostate <= RDO_WRITE; - end if; + when RDO_WAIT => + if dlm_ready = '1' then + rdostate <= RDO_WRITE; + end if; - when RDO_WRITE => - rdostate <= RDO_FINISH; - DATA_OUT <= error_reg & status_reg & "0000" & '0' & x"00"& number_reg & subtrigger; - WRITE_OUT <= '1'; + when RDO_WRITE => + rdostate <= RDO_FINISH; + DATA_OUT <= error_reg & status_reg & "0000" & '0' & x"00"& number_reg & subtrigger; + WRITE_OUT <= '1'; - when RDO_FINISH => - FINISHED_OUT <= '1'; - rdostate <= RDO_IDLE; - end case; + when RDO_FINISH => + FINISHED_OUT <= '1'; + if (TRIGGER_IN = '0') then + rdostate <= RDO_IDLE; + end if; + end case; + end if; end process; STATUSBIT_OUT(23) <= error_reg when rising_edge(CLK); -- 2.43.0