From 797068474216c779b7712577c3c19e10b742c317 Mon Sep 17 00:00:00 2001 From: Cahit Date: Tue, 18 Jun 2013 16:46:33 +0200 Subject: [PATCH] Corrections --- tdc_releases/tdc_v1.5/Channel_200.vhd | 4 ++-- tdc_releases/tdc_v1.5/Readout.vhd | 18 +++++++++--------- tdc_releases/tdc_v1.5/TDC.vhd | 2 +- tdc_releases/tdc_v1.5/tdc_constraints.lpf | 2 +- tdc_releases/tdc_v1.5/trb3_periph.vhd | 12 ++++++------ 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/tdc_releases/tdc_v1.5/Channel_200.vhd b/tdc_releases/tdc_v1.5/Channel_200.vhd index 23fe1d2..c03ffaa 100644 --- a/tdc_releases/tdc_v1.5/Channel_200.vhd +++ b/tdc_releases/tdc_v1.5/Channel_200.vhd @@ -5,7 +5,7 @@ -- File : Channel_200.vhd -- Author : c.ugur@gsi.de -- Created : 2012-08-28 --- Last update: 2013-03-19 +-- Last update: 2013-05-06 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -180,7 +180,7 @@ begin -- Channel_200 fifo_rd_en_i <= READ_EN_IN or fifo_full_i; -- Readout fsm - FSM_CLK : process (CLK_200, RESET_200) + FSM_CLK : process (CLK_200) begin if rising_edge(CLK_200) then FSM_CURRENT <= FSM_NEXT; diff --git a/tdc_releases/tdc_v1.5/Readout.vhd b/tdc_releases/tdc_v1.5/Readout.vhd index 5ea340f..77645e1 100644 --- a/tdc_releases/tdc_v1.5/Readout.vhd +++ b/tdc_releases/tdc_v1.5/Readout.vhd @@ -5,7 +5,7 @@ -- File : Readout.vhd -- Author : cugur@gsi.de -- Created : 2012-10-25 --- Last update: 2013-04-24 +-- Last update: 2013-05-06 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- @@ -160,7 +160,7 @@ architecture behavioral of Readout is signal wr_ch_data_reg : std_logic; signal wr_ch_data_2reg : std_logic; signal wr_status : std_logic; - signal wr_trailer : std_logic; +-- signal wr_trailer : std_logic; signal stop_status_i : std_logic; -- to endpoint signal data_out_reg : std_logic_vector(31 downto 0); @@ -348,7 +348,7 @@ begin -- behavioral -- Readout ------------------------------------------------------------------------------- -- Readout fsm - RD_FSM_CLK : process (CLK_100, RESET_100) + RD_FSM_CLK : process (CLK_100) begin if rising_edge(CLK_100) then RD_CURRENT <= RD_NEXT; @@ -370,7 +370,7 @@ begin -- behavioral READ_EN_OUT <= rd_en; RD_FSM_PROC : process (RD_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_100_p, - ch_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, + TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, DEBUG_MODE_EN_IN, rd_number, fifo_nr_rd, ch_wcnt_2reg) begin @@ -525,7 +525,7 @@ begin -- behavioral end if; end process WR_FSM_CLK; - WR_FSM : process (WR_CURRENT, trg_win_end_100_3reg, TRG_TYPE_IN, wr_number, ch_wcnt_2reg, fifo_nr_wr) + WR_FSM : process (WR_CURRENT, trg_win_end_100_3reg, wr_number, ch_wcnt_2reg, fifo_nr_wr, DATA_LIMIT_IN) begin @@ -642,10 +642,10 @@ begin -- behavioral end case; data_wr_reg <= '1'; i := i+1; - elsif wr_trailer = '1' then - data_out_reg <= "011" & "0000000000000" & trailer_error_bits; - data_wr_reg <= '1'; - stop_status_i <= '0'; + --elsif wr_trailer = '1' then + -- data_out_reg <= "011" & "0000000000000" & trailer_error_bits; + -- data_wr_reg <= '1'; + -- stop_status_i <= '0'; else data_out_reg <= (others => '1'); data_wr_reg <= '0'; diff --git a/tdc_releases/tdc_v1.5/TDC.vhd b/tdc_releases/tdc_v1.5/TDC.vhd index fef3f95..dc715cc 100644 --- a/tdc_releases/tdc_v1.5/TDC.vhd +++ b/tdc_releases/tdc_v1.5/TDC.vhd @@ -179,7 +179,7 @@ begin -- Channel and calibration enable signals GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate - process (ch_en_i, calibration_on, HIT_CALIBRATION, HIT_IN) + process (ch_en_i, calibration_on, HIT_CALIBRATION, hit_latch) begin if ch_en_i(i) = '1' then if calibration_on = '1' then diff --git a/tdc_releases/tdc_v1.5/tdc_constraints.lpf b/tdc_releases/tdc_v1.5/tdc_constraints.lpf index 88b8ce1..dc2a6d4 100644 --- a/tdc_releases/tdc_v1.5/tdc_constraints.lpf +++ b/tdc_releases/tdc_v1.5/tdc_constraints.lpf @@ -20,7 +20,7 @@ UGROUP "ref_hit" BBOX 1 1 BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO; LOCATE UGROUP "ref_hit" SITE "R9C133D" ; UGROUP "Ref_ff_en" BBOX 1 1 - BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i_1_i; + BLKNAME THE_TDC/The_Reference_Time/Reference_Channel_200_1/ff_array_en_i_RNO; LOCATE UGROUP "Ref_ff_en" SITE "R8C156D" ; ############################################################################## diff --git a/tdc_releases/tdc_v1.5/trb3_periph.vhd b/tdc_releases/tdc_v1.5/trb3_periph.vhd index 8d025ae..50529a8 100644 --- a/tdc_releases/tdc_v1.5/trb3_periph.vhd +++ b/tdc_releases/tdc_v1.5/trb3_periph.vhd @@ -357,7 +357,7 @@ begin BROADCAST_BITMASK => x"FF", BROADCAST_SPECIAL_ADDR => x"48", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)), - REGIO_HARDWARE_VERSION => x"91000060", -- regio_hardware_version_i, + REGIO_HARDWARE_VERSION => x"91000860", -- regio_hardware_version_i, REGIO_INIT_ADDRESS => x"f305", REGIO_USE_VAR_ENDPOINT_ID => c_YES, CLOCK_FREQUENCY => 125, @@ -794,13 +794,13 @@ begin CONTROL_REG_IN => tdc_ctrl_reg); -- For single edge measurements - hit_in_i <= INP; + --hit_in_i <= INP; -- For ToT Measurements - --Gen_Hit_In_Signals : for i in 1 to 32 generate - -- hit_in_i(i*2-1) <= INP(i-1); - -- hit_in_i(i*2) <= not INP(i-1); - --end generate Gen_Hit_In_Signals; + Gen_Hit_In_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i-1); + hit_in_i(i*2) <= not INP(i-1); + end generate Gen_Hit_In_Signals; -- !!!!! IMPORTANT !!!!! Don't forget to set the REGIO_HARDWARE_VERSION !!!!! end architecture; -- 2.43.0