From 79ca31595434c53ad22764af528c13f5ce692b01 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 6 Jul 2016 14:54:15 +0200 Subject: [PATCH] Update to ecp5 media interface --- media_interfaces/med_ecp5_sfp_sync.vhd | 111 ++++++++++++--------- media_interfaces/sync/med_sync_control.vhd | 6 +- 2 files changed, 69 insertions(+), 48 deletions(-) diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd index e17ee34..73db43e 100644 --- a/media_interfaces/med_ecp5_sfp_sync.vhd +++ b/media_interfaces/med_ecp5_sfp_sync.vhd @@ -96,11 +96,12 @@ signal stat_tx_control_i : std_logic_vector(31 downto 0); signal debug_rx_control_i : std_logic_vector(31 downto 0); signal debug_tx_control_i : std_logic_vector(31 downto 0); signal stat_fsm_reset_i : std_logic_vector(31 downto 0); - +signal rx_ready, tx_ready : std_logic; signal hdinp, hdinn, hdoutp, hdoutn : std_logic; attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; +signal stat_med : std_logic_vector(31 downto 0); begin @@ -121,57 +122,61 @@ SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches -- Serdes ------------------------------------------------- gen_pcs0 : if SERDES_NUM = 0 generate - THE_SERDES : entity work.serdes_sync_0 + THE_SERDES : entity work.pcs port map( - hdinp => hdinp, - hdinn => hdinn, - hdoutp => hdoutp, - hdoutn => hdoutn, - rxrefclk => CLK_INTERNAL_FULL, - rx_pclk => clk_rx_full, - tx_pclk => clk_tx_full, + serdes_sync_0_hdinp => hdinp, + serdes_sync_0_hdinn => hdinn, + serdes_sync_0_hdoutp => hdoutp, + serdes_sync_0_hdoutn => hdoutn, + serdes_sync_0_rxrefclk => clk_200_ref, + serdes_sync_0_rx_pclk => clk_rx_full, + serdes_sync_0_tx_pclk => clk_tx_full, - txdata => tx_data, - tx_k(0) => tx_k, - tx_force_disp(0) => '0', - tx_disp_sel(0) => '0', - rxdata => rx_data, - rx_k(0) => rx_k, - rx_disp_err(0) => open, - rx_cv_err(0) => rx_error, + serdes_sync_0_txdata => tx_data, + serdes_sync_0_tx_k(0) => tx_k, + serdes_sync_0_tx_force_disp(0) => '0', + serdes_sync_0_tx_disp_sel(0) => '0', + serdes_sync_0_rxdata => rx_data, + serdes_sync_0_rx_k(0) => rx_k, + serdes_sync_0_rx_disp_err(0) => open, + serdes_sync_0_rx_cv_err(0) => rx_error, - tx_idle_c => '0', - signal_detect_c => '0', --?force enable - rx_los_low_s => rx_los_low, - lsm_status_s => lsm_status, - rx_cdr_lol_s => rx_cdr_lol, - rx_pcs_rst_c => rx_pcs_rst, - tx_pcs_rst_c => tx_pcs_rst, - rx_serdes_rst_c => rx_serdes_rst, + serdes_sync_0_tx_idle_c => '0', + serdes_sync_0_signal_detect_c => '0', --?force enable + serdes_sync_0_rx_los_low_s => rx_los_low, + serdes_sync_0_lsm_status_s => lsm_status, + serdes_sync_0_rx_cdr_lol_s => rx_cdr_lol, + serdes_sync_0_rx_pcs_rst_c => rx_pcs_rst, + serdes_sync_0_tx_pcs_rst_c => tx_pcs_rst, + serdes_sync_0_rx_serdes_rst_c => rx_serdes_rst, - sci_wrdata => sci_data_in_i, - sci_rddata => sci_data_out_i, - sci_addr => sci_addr_i, - sci_en_dual => '1', --? - sci_sel_dual => sci_ch_i(4), - sci_en => '1', --? - sci_sel => sci_ch_i(0), - sci_rd => sci_read_i, - sci_wrn => sci_write_i, - sci_int => open, + serdes_sync_0_sci_wrdata => sci_data_in_i, + serdes_sync_0_sci_rddata => sci_data_out_i, + serdes_sync_0_sci_addr => sci_addr_i, + serdes_sync_0_sci_en_dual => sci_ch_i(4), --? + serdes_sync_0_sci_sel_dual => sci_ch_i(4), + serdes_sync_0_sci_en => sci_ch_i(0), --? + serdes_sync_0_sci_sel => sci_ch_i(0), + serdes_sync_0_sci_rd => sci_read_i, + serdes_sync_0_sci_wrn => sci_write_i, + serdes_sync_0_sci_int => open, - cyawstn => '1', --? - rst_dual_c => rst_qd, - serdes_rst_dual_c => '0', - tx_pwrup_c => '1', - rx_pwrup_c => '1', - serdes_pdb => '1', - tx_serdes_rst_c => '0', + serdes_sync_0_cyawstn => '1', --? + serdes_sync_0_rst_dual_c => rst_qd, + serdes_sync_0_serdes_rst_dual_c => '0', + serdes_sync_0_tx_pwrup_c => '1', + serdes_sync_0_rx_pwrup_c => '1', + serdes_sync_0_serdes_pdb => '1', + serdes_sync_0_tx_serdes_rst_c => '0', - pll_refclki => clk_200_ref, - sli_rst => '0', - pll_lol => tx_pll_lol + serdes_sync_0_pll_refclki => clk_200_ref, +-- sli_rst => '0', + serdes_sync_0_pll_lol => tx_pll_lol, + serdes_sync_0_rsl_disable => '0', + serdes_sync_0_rsl_rst => CLEAR, + serdes_sync_0_rsl_rx_rdy => rx_ready, + serdes_sync_0_rsl_tx_rdy => tx_ready ); end generate; @@ -191,7 +196,7 @@ THE_MED_CONTROL : entity work.med_sync_control CLK_RXI => clk_rx_full, --clk_rx_full, CLK_RXHALF => '0', CLK_TXI => clk_200_ref, --clk_200_internal, --clk_tx_full, JM150706 - CLK_REF => CLK_INTERNAL_FULL, + CLK_REF => clk_200_ref, --CLK_INTERNAL_FULL, RESET => RESET, CLEAR => CLEAR, @@ -248,7 +253,7 @@ THE_SCI_READER : entity work.sci_reader MEDIA_STATUS_REG_IN(31 downto 0) => stat_rx_control_i, MEDIA_STATUS_REG_IN(63 downto 32) => stat_tx_control_i, MEDIA_STATUS_REG_IN(95 downto 64) => stat_fsm_reset_i, - MEDIA_STATUS_REG_IN(127 downto 96) => (others => '0'), + MEDIA_STATUS_REG_IN(127 downto 96) => stat_med, DEBUG_OUT => open ); @@ -259,5 +264,17 @@ THE_SCI_READER : entity work.sci_reader -- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); STAT_DEBUG(15 downto 0) <= debug_rx_control_i(15 downto 0); +stat_med(0) <= rst_qd; +stat_med(1) <= rx_pcs_rst; +stat_med(2) <= tx_pcs_rst; +stat_med(3) <= rx_serdes_rst; +stat_med(4) <= tx_pll_lol; +stat_med(5) <= rx_cdr_lol; +stat_med(6) <= rx_los_low; +stat_med(7) <= rx_ready; +stat_med(8) <= tx_ready; +stat_med(31 downto 9) <= (others => '0'); + + end architecture; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index 04cb368..e5e9c6f 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -262,7 +262,11 @@ STAT_RESET(3 downto 0) <= rx_fsm_state; STAT_RESET(7 downto 4) <= tx_fsm_state; STAT_RESET(8) <= tx_allow; STAT_RESET(9) <= rx_allow; -STAT_RESET(31 downto 10) <= (others => '0'); +STAT_RESET(15 downto 10) <= (others => '0'); +STAT_RESET(16) <= RX_CDR_LOL; +STAT_RESET(17) <= RX_LOS; +STAT_RESET(18) <= RX_PCS_RST; +STAT_RESET(31 downto 19) <= (others => '0'); gen_link_reset : if IS_SYNC_SLAVE = 1 generate -- 2.43.0