From 79eb8f822d56ce1bfd0171c7f27fba7436dcbd78 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 26 Apr 2021 08:23:02 +0200 Subject: [PATCH] fix of a bug in reset of trbnet from trbnet bridge. The sync from AGWB is mostly getting high for a few ns after reset. A timeout of a few ns resolves this issue for now. --- src/cri_trbnet_dca_bridge.vhd | 34 +++++++++++++++++++++++++++------- 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd index e6d43c0..b0c9d9f 100644 --- a/src/cri_trbnet_dca_bridge.vhd +++ b/src/cri_trbnet_dca_bridge.vhd @@ -111,7 +111,7 @@ attribute syn_preserve of rx_fifo_wr, rx_fifo_rd, dca_init_dataready, tx_fifo_wr signal rx_cnt, tx_cnt : std_logic_vector(15 downto 0); -signal rx_data_wr, last_rx_data_wr, rx_data_wr_sync : std_logic; +signal rx_data_wr, last_rx_data_wr, rx_data_wr_sync, rx_data_wr_sync_i : std_logic; signal rx_data_dca, rx_data_dca_sync : std_logic_vector(33 downto 0); signal tx_rd_ack, last_tx_rd_ack, tx_rd_ack_sync : std_logic; @@ -129,6 +129,8 @@ signal tx_data_out : std_logic_vector(31 downto 0); signal wait_cnt : unsigned(1 downto 0) := "00"; signal wait_dca, wait_dca_sync : std_logic := '0'; +signal reset_timeout : std_logic_vector( 4 downto 0); + begin reset_dca <= not RST_N_DCA; @@ -204,9 +206,25 @@ THE_SYNC_RX_DATA : entity work.signal_sync RESET_B_IN => RESET, CLK_B_IN => CLK, - PULSE_B_OUT => rx_data_wr_sync + PULSE_B_OUT => rx_data_wr_sync_i ); + rx_data_wr_sync <= rx_data_wr_sync_i when reset_timeout(4) = '1' + else '0'; + +PROC_RESET_TIMEOUT : process(CLK) -- timeout for DCA for a few ns after reset to resolve bug with high on rx_data_wr_sync_i after reset +begin + if rising_edge(CLK) then + if (RESET = '1') then + reset_timeout <= "00000"; + elsif reset_timeout(4) = '0' then + reset_timeout <= reset_timeout + 1; + else + reset_timeout <= reset_timeout; + end if; + end if; +end process PROC_RESET_TIMEOUT; + THE_SYNC_TX_RD_ACK : entity work.pulse_sync port map( RESET_A_IN => reset_dca, @@ -541,12 +559,14 @@ begin when LOAD_TO_HUB => state <= x"4"; - if (rx_fifo_q(16) = '1') then - if (reset_detected = '1') then - dissect_next_state <= CLEANUP; - else + if (reset_detected = '1') then + dissect_next_state <= CLEANUP; + elsif (rx_fifo_q(16) = '1') then + --if (reset_detected = '1') then + -- dissect_next_state <= CLEANUP; + --else dissect_next_state <= WAIT_FOR_RESPONSE; - end if; + --end if; else dissect_next_state <= LOAD_TO_HUB; end if; -- 2.43.0