From 7a173d2477badc3d15fd5c3ac817217f97b84b0e Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Wed, 30 Sep 2020 15:21:31 +0200 Subject: [PATCH] rx_control: Use system clock for sampling rx_allow rx_allow is synchronous to the system clock. ct_fifo_reset is asynchronous and can therefore be produced with the system clock to avoid timing errors. --- media_interfaces/sync/rx_control.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 88c91fb..8e8085b 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -128,7 +128,7 @@ THE_CT_FIFO : entity work.lattice_ecp3_fifo_18x16_dualport_oreg AlmostFull => ct_fifo_afull ); -ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_200); +ct_fifo_reset <= not RX_ALLOW_IN when rising_edge(CLK_100); ---------------------------------------------------------------------- -- 2.43.0