From 7a2afc5919cfe7e81719e88fd75a3f12b6cf6d1f Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Fri, 18 Jul 2014 21:05:20 +0200 Subject: [PATCH] CBMNet: Simulation of TrbNet -> CBMNet readout path seems to work --- cbmnet/code/cbmnet_interface_pkg.vhd | 5 +- cbmnet/code/cbmnet_readout.vhd | 11 +- cbmnet/code/cbmnet_readout_event_packer.vhd | 17 +- cbmnet/code/cbmnet_readout_trbnet_decoder.vhd | 22 +- cbmnet/code/cbmnet_readout_tx_fsm.vhd | 91 ++++---- cbmnet/code/tb_cbmnet_readout.vhd | 196 ++++++++++++++++++ 6 files changed, 274 insertions(+), 68 deletions(-) create mode 100644 cbmnet/code/tb_cbmnet_readout.vhd diff --git a/cbmnet/code/cbmnet_interface_pkg.vhd b/cbmnet/code/cbmnet_interface_pkg.vhd index 8a810d6..10c15ab 100644 --- a/cbmnet/code/cbmnet_interface_pkg.vhd +++ b/cbmnet/code/cbmnet_interface_pkg.vhd @@ -437,7 +437,7 @@ package cbmnet_interface_pkg is DEC_ACTIVE_OUT : out std_logic; DEC_ERROR_OUT : out std_logic; - DEBUG_OUT : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end component; @@ -452,7 +452,7 @@ package cbmnet_interface_pkg is HUB_CTS_CODE_IN : in std_logic_vector (7 downto 0); HUB_CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); HUB_CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - HUB_FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + GBE_CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); -- connect to decoder @@ -473,7 +473,6 @@ package cbmnet_interface_pkg is WDATA_OUT : out std_logic_vector(17 downto 0); WENQUEUE_OUT : out std_logic; WPACKET_COMPLETE_OUT: out std_logic; - WALMOST_FULL_IN : in std_logic; WFULL_IN : in std_logic; DEBUG_OUT : out std_logic_vector(31 downto 0) diff --git a/cbmnet/code/cbmnet_readout.vhd b/cbmnet/code/cbmnet_readout.vhd index 370bb61..bf11e89 100644 --- a/cbmnet/code/cbmnet_readout.vhd +++ b/cbmnet/code/cbmnet_readout.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + use work.cbmnet_interface_pkg.all; entity CBMNET_READOUT is port ( @@ -82,12 +83,6 @@ architecture cbmnet_readout_arch of CBMNET_READOUT is signal dec_error_i : std_logic; signal dec_actice_i : std_logic; signal dec_data_ready_i : std_logic; - - - signal : std_logic; - signal : std_logic; - signal : std_logic; - begin GBE_CTS_NUMBER_OUT <= HUB_CTS_NUMBER_IN; @@ -143,7 +138,7 @@ begin HUB_CTS_CODE_IN => HUB_CTS_CODE_IN, -- in std_logic_vector (7 downto 0); HUB_CTS_INFORMATION_IN => HUB_CTS_INFORMATION_IN, -- in std_logic_vector (7 downto 0); HUB_CTS_READOUT_TYPE_IN => HUB_CTS_READOUT_TYPE_IN, -- in std_logic_vector (3 downto 0); - HUB_FEE_STATUS_BITS_IN => HUB_FEE_STATUS_BITS_IN, -- in std_logic_vector (31 downto 0); + GBE_CTS_STATUS_BITS_IN => GBE_CTS_STATUS_BITS_IN, -- in std_logic_vector (31 downto 0); -- connect to decoder @@ -199,7 +194,7 @@ begin RPACKET_COMPLETE_ACK_IN => fifo_rpacket_complete_ack_i -- in std_logic -- mark one event as dealt with (effectively decrease number of completed packets by one) ); - THE_TX_FSM: CBMNET_READOUT_TX_FSM is + THE_TX_FSM: CBMNET_READOUT_TX_FSM port map ( CLK_IN => CBMNET_CLK_IN, -- in std_logic; RESET_IN => CBMNET_RESET_IN, -- in std_logic; diff --git a/cbmnet/code/cbmnet_readout_event_packer.vhd b/cbmnet/code/cbmnet_readout_event_packer.vhd index 409a890..b3720d3 100644 --- a/cbmnet/code/cbmnet_readout_event_packer.vhd +++ b/cbmnet/code/cbmnet_readout_event_packer.vhd @@ -13,7 +13,7 @@ entity CBMNET_READOUT_EVENT_PACKER is HUB_CTS_CODE_IN : in std_logic_vector (7 downto 0); HUB_CTS_INFORMATION_IN : in std_logic_vector (7 downto 0); HUB_CTS_READOUT_TYPE_IN : in std_logic_vector (3 downto 0); - HUB_FEE_STATUS_BITS_IN : in std_logic_vector (31 downto 0); + GBE_CTS_STATUS_BITS_IN : in std_logic_vector (31 downto 0); -- connect to decoder @@ -34,7 +34,6 @@ entity CBMNET_READOUT_EVENT_PACKER is WDATA_OUT : out std_logic_vector(17 downto 0); WENQUEUE_OUT : out std_logic; WPACKET_COMPLETE_OUT: out std_logic; - WALMOST_FULL_IN : in std_logic; WFULL_IN : in std_logic; DEBUG_OUT : out std_logic_vector(31 downto 0) @@ -56,6 +55,7 @@ architecture cbmnet_readout_event_packer_arch of CBMNET_READOUT_EVENT_PACKER is signal fsm_i : FSM_STATES_T; signal header_data_i : std_logic_vector(15 downto 0); signal header_enqueue_i : std_logic; + signal copy_payload_i : std_logic; begin THE_PACKER: process is begin @@ -90,7 +90,7 @@ begin header_enqueue_i <= '1'; fsm_i <= HDR_SIZE_L; when HDR_SIZE_L => - header_data_i <= DEC_LENGTH_IN; + header_data_i <= STD_LOGIC_VECTOR(UNSIGNED(DEC_LENGTH_IN) + TO_UNSIGNED(16+8, 16)); -- 8 words of SE-Hdr and 4 words for SE-trailer header_enqueue_i <= '1'; fsm_i <= HDR_DECODING_H; @@ -119,7 +119,7 @@ begin when HDR_NUMBER_L => header_data_i <= HUB_CTS_NUMBER_IN(7 downto 0) & HUB_CTS_CODE_IN; header_enqueue_i <= '1'; - fsm_i <= HDR_SIZE_L; + fsm_i <= PAYLOAD; when PAYLOAD => if DEC_ACTIVE_IN = '0' then @@ -138,11 +138,11 @@ begin fsm_i <= FTR_STATUS_H; when FTR_STATUS_H => - header_data_i <= x"0001"; + header_data_i <= GBE_CTS_STATUS_BITS_IN(31 downto 16); header_enqueue_i <= '1'; fsm_i <= FTR_STATUS_L; when FTR_STATUS_L => - header_data_i <= x"5555"; + header_data_i <= GBE_CTS_STATUS_BITS_IN(15 downto 0); header_enqueue_i <= '1'; WPACKET_COMPLETE_OUT <= '1'; fsm_i <= IDLE; @@ -151,7 +151,8 @@ begin end if; end process; - WDATA_OUT <= DEC_DATA_IN when copy_payload_i='1' else header_data_i; - WENQUEUE_OUT <= header_data_i or DEC_DATA_READY_IN; + WDATA_OUT(15 downto 0) <= DEC_DATA_IN when copy_payload_i='1' else header_data_i; + WDATA_OUT(17 downto 16) <= "00"; + WENQUEUE_OUT <= header_enqueue_i or DEC_DATA_READY_IN; DEC_DATA_READ_OUT <= copy_payload_i and DEC_DATA_READY_IN; end architecture; \ No newline at end of file diff --git a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd index e2e8981..2c99ef4 100644 --- a/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd +++ b/cbmnet/code/cbmnet_readout_trbnet_decoder.vhd @@ -24,7 +24,7 @@ entity CBMNET_READOUT_TRBNET_DECODER is -- Decode DEC_EVT_INFO_OUT : out std_logic_vector(31 downto 0); - DEC_LENGTH_OUT : out std_logic_vector(15 downto 0); + DEC_LENGTH_OUT : out std_logic_vector(15 downto 0); -- bytes of payload DEC_SOURCE_OUT : out std_logic_vector(15 downto 0); DEC_DATA_OUT : out std_logic_vector(15 downto 0); DEC_DATA_READY_OUT : out std_logic; @@ -54,7 +54,7 @@ architecture cbmnet_readout_trbnet_decoder_arch of CBMNET_READOUT_TRBNET_DECODER ); end component; - type FSM_STATES_T is (WAIT_FOR_IDLE, IDLE, RECV_EVT_INFO_H, RECV_EVT_INFO_L, RECV_EVT_LENGTH, RECV_EVT_SOURCE, RECV_PAYLOAD, ERROR_COND); + type FSM_STATES_T is (WAIT_FOR_IDLE, IDLE, RECV_EVT_INFO_H, RECV_EVT_INFO_L, RECV_EVT_LENGTH, RECV_EVT_SOURCE, RECV_PAYLOAD, LAST_WORD, ERROR_COND); signal fsm_i : FSM_STATES_T; signal data_i : std_logic_vector(15 downto 0); @@ -85,7 +85,7 @@ begin fifo_active_i <= '0'; DEC_ACTIVE_OUT <= '0'; word_counter_set_i <= '0'; - dec_error_i <= dec_error_i or not HUB_CTS_START_READOUT_IN; + dec_error_i <= dec_error_i or (not HUB_CTS_START_READOUT_IN and not word_counter_done_i); if RESET_IN = '1' then fsm_i <= WAIT_FOR_IDLE; @@ -124,7 +124,7 @@ begin DEBUG_OUT(3 downto 0) <= x"4"; word_counter_set_i <= '1'; if read_word_i = '1' then - dec_length_i <= data_i; + dec_length_i <= data_i(13 downto 0) & "00"; fsm_i <= RECV_EVT_SOURCE; end if; @@ -146,6 +146,12 @@ begin end if; if fifo_empty_i = '1' and word_counter_done_i = '1' then + fsm_i <= LAST_WORD; + end if; + + when LAST_WORD => + DEC_ACTIVE_OUT <= '1'; + if DEC_DATA_READ_IN = '1' then fsm_i <= WAIT_FOR_IDLE; end if; @@ -167,7 +173,7 @@ begin if word_counter_set_i = '1' then word_counter_i <= UNSIGNED("0" & dec_length_i(15 downto 1)); - elsif word_counter_done_i = '0' and read_word_i = '1' then + elsif word_counter_done_i = '0' and fifo_enqueue_i = '1' then word_counter_i <= word_counter_i - 1; end if; @@ -175,7 +181,7 @@ begin DEBUG_OUT(31 downto 16) <= STD_LOGIC_VECTOR(word_counter_i); end process; - word_counter_done_i <= '1' when word_counter_i = x"0002" else '0'; + word_counter_done_i <= '1' when word_counter_i = x"0000" else '0'; THE_FIFO: lattice_ecp3_fifo_16x16_dualport port map ( @@ -202,9 +208,9 @@ begin DEC_LENGTH_OUT <= dec_length_i; DEC_EVT_INFO_OUT <= dec_evt_info_i; DEC_SOURCE_OUT <= dec_source_i; - DEC_DATA_READY_OUT <= not fifo_empty_i; + DEC_DATA_READY_OUT <= '1' when fifo_empty_i = '0' or fsm_i = LAST_WORD else '0'; - DEC_DATA_OUT <= x"aaaa" when fifo_empty_i = '1' else fifo_data_i; + DEC_DATA_OUT <= fifo_data_i; end architecture; diff --git a/cbmnet/code/cbmnet_readout_tx_fsm.vhd b/cbmnet/code/cbmnet_readout_tx_fsm.vhd index d1801e7..6526c5a 100644 --- a/cbmnet/code/cbmnet_readout_tx_fsm.vhd +++ b/cbmnet/code/cbmnet_readout_tx_fsm.vhd @@ -26,16 +26,22 @@ architecture cbmnet_readout_tx_fsm_arch of CBMNET_READOUT_TX_FSM is constant PAYLOAD_PER_PACKET_C : integer := 62; -- bytes - type FSM_STATES_T is (WAIT_FOR_COMPL_PACKET, READ_LENGTH_H, SETUP_TRANSACTION, SEND_HEADER, SEND_PAYLOAD, FINISH_TRANSACTION); + type FSM_STATES_T is (WAIT_FOR_COMPL_PACKET, SETUP_TRANSACTION, SEND_HEADER, SEND_PAYLOAD, SEND_PACKET_GAP, FINISH_TRANSACTION, FINISH_WAIT1, FINISH_WAIT2); signal fsm_i : FSM_STATES_T; + + signal trans_num_i : unsigned(5 downto 0); - signal trans_length_high_i : std_logic_vector(15 downto 0); - signal trans_remaining_length_i : unsigned(15 downto 0); + signal trans_bytes_length_i : unsigned(15 downto 0) := x"0000"; + signal trans_bytes_send_i : unsigned(15 downto 0); - signal pack_num_i : unsigned(10 downto 0); + signal pack_num_i : unsigned(5 downto 0); signal pack_payload_words_i : unsigned(4 downto 0); signal pack_start_i, pack_stop_i : std_logic; + + signal trans_complete_i : std_logic; + + begin PROC_TX_CNTL: process is begin @@ -50,78 +56,81 @@ begin if RESET_IN = '1' then fsm_i <= WAIT_FOR_COMPL_PACKET; + trans_num_i <= (others => '0'); + else case(fsm_i) is when WAIT_FOR_COMPL_PACKET => if FIFO_PACKET_COMPLETE_IN = '1' then - fsm_i <= READ_LENGTH_H; - FIFO_DEQUEUE_OUT <= '1'; + fsm_i <= SETUP_TRANSACTION; end if; - - when READ_LENGTH_H => - trans_length_high_i <= FIFO_DATA_IN(15 downto 0); - fsm_i <= SETUP_TRANSACTION; - + when SETUP_TRANSACTION => - trans_remaining_length_i <= UNSIGNED(FIFO_DATA_IN(15 downto 0)); - pack_start_i <= '1'; + trans_bytes_send_i <= (others => '0'); pack_num_i <= (others => '0'); + pack_start_i <= '1'; + trans_bytes_length_i(15) <= '1'; -- dont really care which value as long as it's > 2, so it ensured that the first word of the SE-Hdr is sent! + fsm_i <= SEND_HEADER; when SEND_HEADER => if CBMNET_STOP_IN = '0' then + CBMNET_DATA_OUT <= (others => '0'); CBMNET_DATA_OUT( 5 downto 0) <= STD_LOGIC_VECTOR(pack_num_i); + CBMNET_DATA_OUT(11 downto 6) <= STD_LOGIC_VECTOR(trans_num_i); CBMNET_DATA_OUT(14) <= pack_start_i; CBMNET_DATA_OUT(15) <= pack_stop_i; CBMNET_START_OUT <= '1'; - if trans_remaining_length_i < PAYLOAD_PER_PACKET_C then - -- TODO: i dont think that odd packet lengths are supported by TrbNet, but check it ! - pack_payload_words_i <= UNSIGNED(trans_remaining_length_i(pack_payload_words_i'high + 1 downto 1)); - else - pack_payload_words_i <= TO_UNSIGNED(PAYLOAD_PER_PACKET_C / 2, pack_payload_words_i'length); - end if; + pack_payload_words_i <= (others => '0'); - FIFO_DEQUEUE_OUT <= not pack_start_i; + FIFO_DEQUEUE_OUT <= '1'; fsm_i <= SEND_PAYLOAD; end if; when SEND_PAYLOAD => - if pack_start_i = '1' then - CBMNET_DATA_OUT <= trans_length_high_i; - FIFO_DEQUEUE_OUT <= '1'; + if pack_payload_words_i = 30 or trans_complete_i = '1' then + CBMNET_END_OUT <= '1'; + pack_num_i <= pack_num_i + 1; - else - if pack_payload_words_i = 1 then - CBMNET_END_OUT <= '1'; - pack_num_i <= pack_num_i + 1; - - if trans_remaining_length_i = 2 then - fsm_i <= FINISH_TRANSACTION; - else - fsm_i <= SEND_HEADER; - end if; - + if trans_complete_i = '1' then + fsm_i <= FINISH_TRANSACTION; else - FIFO_DEQUEUE_OUT <= '1'; + fsm_i <= SEND_PACKET_GAP; end if; + + else + FIFO_DEQUEUE_OUT <= '1'; + end if; + + if trans_bytes_send_i = 2 then + trans_bytes_length_i <= UNSIGNED(FIFO_DATA_IN); end if; pack_start_i <= '0'; - pack_payload_words_i <= pack_payload_words_i - 1; - trans_remaining_length_i <= trans_remaining_length_i - 2; + pack_payload_words_i <= pack_payload_words_i + 1; + trans_bytes_send_i <= trans_bytes_send_i + 2; + + + when SEND_PACKET_GAP => + fsm_i <= SEND_HEADER; when FINISH_TRANSACTION => FIFO_PACKET_COMPLETE_ACK_OUT <= '1'; + trans_num_i <= trans_num_i + 1; + fsm_i <= FINISH_WAIT1; + + when FINISH_WAIT1 => + fsm_i <= FINISH_WAIT2; + + when FINISH_WAIT2 => fsm_i <= WAIT_FOR_COMPL_PACKET; end case; end if; end process; - - - - pack_stop_i <= '1' when trans_remaining_length_i < PAYLOAD_PER_PACKET_C else '0'; + pack_stop_i <= '1' when trans_bytes_length_i - trans_bytes_send_i < PAYLOAD_PER_PACKET_C else '0'; + trans_complete_i <= '1' when trans_bytes_length_i = trans_bytes_send_i else '0'; end architecture; diff --git a/cbmnet/code/tb_cbmnet_readout.vhd b/cbmnet/code/tb_cbmnet_readout.vhd new file mode 100644 index 0000000..be4f476 --- /dev/null +++ b/cbmnet/code/tb_cbmnet_readout.vhd @@ -0,0 +1,196 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + use work.cbmnet_interface_pkg.all; + +entity tb_cbmnet_readout is +end tb_cbmnet_readout; + +architecture TB of tb_cbmnet_readout is + signal CLK_IN : std_logic := '0'; + signal RESET_IN : std_logic := '0'; + + -- connect to hub + signal HUB_CTS_NUMBER_IN : std_logic_vector (15 downto 0) := (others => '0'); + signal HUB_CTS_CODE_IN : std_logic_vector (7 downto 0) := (others => '0'); + signal HUB_CTS_INFORMATION_IN : std_logic_vector (7 downto 0) := (others => '0'); + signal HUB_CTS_READOUT_TYPE_IN : std_logic_vector (3 downto 0) := (others => '0'); + signal HUB_CTS_START_READOUT_IN : std_logic := '0'; + signal HUB_CTS_READOUT_FINISHED_OUT : std_logic := '0'; --no more data, end transfer, send TRM + signal HUB_CTS_STATUS_BITS_OUT : std_logic_vector (31 downto 0) := (others => '0'); + signal HUB_FEE_DATA_IN : std_logic_vector (15 downto 0) := (others => '0'); + signal HUB_FEE_DATAREADY_IN : std_logic := '0'; + signal HUB_FEE_READ_OUT : std_logic := '0'; --must be high when idle, otherwise you will never get a dataready + signal HUB_FEE_STATUS_BITS_IN : std_logic_vector (31 downto 0) := (others => '0'); + signal HUB_FEE_BUSY_IN : std_logic := '0'; + + -- connect to GbE + signal GBE_CTS_NUMBER_OUT : std_logic_vector (15 downto 0) := (others => '0'); + signal GBE_CTS_CODE_OUT : std_logic_vector (7 downto 0) := (others => '0'); + signal GBE_CTS_INFORMATION_OUT : std_logic_vector (7 downto 0) := (others => '0'); + signal GBE_CTS_READOUT_TYPE_OUT : std_logic_vector (3 downto 0) := (others => '0'); + signal GBE_CTS_START_READOUT_OUT : std_logic := '0'; + signal GBE_CTS_READOUT_FINISHED_IN : std_logic := '0'; --no more data, end transfer, send TRM + signal GBE_CTS_STATUS_BITS_IN : std_logic_vector (31 downto 0) := (others => '0'); + signal GBE_FEE_DATA_OUT : std_logic_vector (15 downto 0) := (others => '0'); + signal GBE_FEE_DATAREADY_OUT : std_logic := '0'; + signal GBE_FEE_READ_IN : std_logic := '0'; --must be high when idle, otherwise you will never get a dataready + signal GBE_FEE_STATUS_BITS_OUT : std_logic_vector (31 downto 0) := (others => '0'); + signal GBE_FEE_BUSY_OUT : std_logic := '0'; + + -- reg io + signal REGIO_ADDR_IN : std_logic_vector(15 downto 0) := (others => '0'); + signal REGIO_DATA_IN : std_logic_vector(31 downto 0) := (others => '0'); + signal REGIO_READ_ENABLE_IN : std_logic := '0'; + signal REGIO_WRITE_ENABLE_IN : std_logic := '0'; + signal REGIO_DATA_OUT : std_logic_vector(31 downto 0) := (others => '0'); + signal REGIO_DATAREADY_OUT : std_logic := '0'; + signal REGIO_WRITE_ACK_OUT : std_logic := '0'; + signal REGIO_UNKNOWN_ADDR_OUT : std_logic := '0'; + + -- CBMNet + signal CBMNET_CLK_IN : std_logic := '0'; + signal CBMNET_RESET_IN : std_logic := '0'; + signal CBMNET_LINK_ACTIVE_IN : std_logic := '0'; + + signal CBMNET_DATA2SEND_STOP_IN : std_logic := '0'; + signal CBMNET_DATA2SEND_START_OUT : std_logic := '0'; + signal CBMNET_DATA2SEND_END_OUT : std_logic := '0'; + signal CBMNET_DATA2SEND_DATA_OUT : std_logic_vector(15 downto 0) := (others => '0'); +begin + CLK_IN <= not CLK_IN after 5 ns; + RESET_IN <= '1', '0' after 30 ns; + + CBMNET_CLK_IN <= not CBMNET_CLK_IN after 4 ns; + CBMNET_RESET_IN <= '1', '0' after 20 ns; + CBMNET_LINK_ACTIVE_IN <= '1'; + + PROC_TRBNET: process is + variable evt_num : integer := 16#1234#; + variable trg_code : std_logic_vector(7 downto 0) := x"ab"; + variable trg_type : std_logic_vector(3 downto 0) := x"e"; + variable trg_conf : std_logic_vector(3 downto 0) := x"0"; + begin + wait for 100 ns; + + HUB_CTS_START_READOUT_IN <= '1'; + HUB_CTS_NUMBER_IN <= STD_LOGIC_VECTOR(TO_UNSIGNED(evt_num, 16)); + evt_num := evt_num + 1; + HUB_CTS_READOUT_TYPE_IN <= x"e"; + GBE_CTS_STATUS_BITS_IN <= x"12345678"; + + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + HUB_FEE_BUSY_IN <= '1'; + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + + for i in 0 to 103 loop + case i is + when 0 => HUB_FEE_DATA_IN <= trg_conf & trg_type & trg_code; + when 1 => HUB_FEE_DATA_IN <= HUB_CTS_NUMBER_IN; + when 2 => HUB_FEE_DATA_IN <= STD_LOGIC_VECTOR(TO_UNSIGNED(50, 16)); + when 3 => HUB_FEE_DATA_IN <= x"affe"; + when others => HUB_FEE_DATA_IN <= STD_LOGIC_VECTOR(TO_UNSIGNED(i-3, 16)); + end case; + + HUB_FEE_DATAREADY_IN <= '1'; + + wait until rising_edge(CLK_IN); + + while GBE_FEE_READ_IN = '0' loop + wait until rising_edge(CLK_IN); + end loop; + end loop; + + HUB_FEE_DATAREADY_IN <= '0'; + + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + + HUB_FEE_BUSY_IN <= '0'; + + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + + HUB_CTS_START_READOUT_IN <= '0'; + + wait until rising_edge(CLK_IN); + wait until rising_edge(CLK_IN); + + end process; + + PROC_CBMNET: process is + begin + CBMNET_DATA2SEND_STOP_IN <= '0'; + wait until falling_edge(CBMNET_DATA2SEND_END_OUT); + CBMNET_DATA2SEND_STOP_IN <= '1'; + wait until rising_edge(CBMNET_CLK_IN); + wait until rising_edge(CBMNET_CLK_IN); + wait until rising_edge(CBMNET_CLK_IN); + wait until rising_edge(CBMNET_CLK_IN); + end process; + + GBE_FEE_READ_IN <= HUB_FEE_DATAREADY_IN; + + DUT: cbmnet_readout + port map ( + CLK_IN => CLK_IN, -- in std_logic; + RESET_IN => RESET_IN, -- in std_logic; + + -- connect to hub + HUB_CTS_NUMBER_IN => HUB_CTS_NUMBER_IN, -- in std_logic_vector (15 downto 0); + HUB_CTS_CODE_IN => HUB_CTS_CODE_IN, -- in std_logic_vector (7 downto 0); + HUB_CTS_INFORMATION_IN => HUB_CTS_INFORMATION_IN, -- in std_logic_vector (7 downto 0); + HUB_CTS_READOUT_TYPE_IN => HUB_CTS_READOUT_TYPE_IN, -- in std_logic_vector (3 downto 0); + HUB_CTS_START_READOUT_IN => HUB_CTS_START_READOUT_IN, -- in std_logic; + HUB_CTS_READOUT_FINISHED_OUT => HUB_CTS_READOUT_FINISHED_OUT, -- out std_logic; --no more data, end transfer, send TRM + HUB_CTS_STATUS_BITS_OUT => HUB_CTS_STATUS_BITS_OUT, -- out std_logic_vector (31 downto 0); + HUB_FEE_DATA_IN => HUB_FEE_DATA_IN, -- in std_logic_vector (15 downto 0); + HUB_FEE_DATAREADY_IN => HUB_FEE_DATAREADY_IN, -- in std_logic; + HUB_FEE_READ_OUT => HUB_FEE_READ_OUT, -- out std_logic; --must be high when idle, otherwise you will never get a dataready + HUB_FEE_STATUS_BITS_IN => HUB_FEE_STATUS_BITS_IN, -- in std_logic_vector (31 downto 0); + HUB_FEE_BUSY_IN => HUB_FEE_BUSY_IN, -- in std_logic; + + -- connect to GbE + GBE_CTS_NUMBER_OUT => GBE_CTS_NUMBER_OUT, -- out std_logic_vector (15 downto 0); + GBE_CTS_CODE_OUT => GBE_CTS_CODE_OUT, -- out std_logic_vector (7 downto 0); + GBE_CTS_INFORMATION_OUT => GBE_CTS_INFORMATION_OUT, -- out std_logic_vector (7 downto 0); + GBE_CTS_READOUT_TYPE_OUT => GBE_CTS_READOUT_TYPE_OUT, -- out std_logic_vector (3 downto 0); + GBE_CTS_START_READOUT_OUT => GBE_CTS_START_READOUT_OUT, -- out std_logic; + GBE_CTS_READOUT_FINISHED_IN => GBE_CTS_READOUT_FINISHED_IN, -- in std_logic; --no more data, end transfer, send TRM + GBE_CTS_STATUS_BITS_IN => GBE_CTS_STATUS_BITS_IN, -- in std_logic_vector (31 downto 0); + GBE_FEE_DATA_OUT => GBE_FEE_DATA_OUT, -- out std_logic_vector (15 downto 0); + GBE_FEE_DATAREADY_OUT => GBE_FEE_DATAREADY_OUT, -- out std_logic; + GBE_FEE_READ_IN => GBE_FEE_READ_IN, -- in std_logic; --must be high when idle, otherwise you will never get a dataready + GBE_FEE_STATUS_BITS_OUT => GBE_FEE_STATUS_BITS_OUT, -- out std_logic_vector (31 downto 0); + GBE_FEE_BUSY_OUT => GBE_FEE_BUSY_OUT, -- out std_logic; + + -- reg io + REGIO_ADDR_IN => REGIO_ADDR_IN, -- in std_logic_vector(15 downto 0); + REGIO_DATA_IN => REGIO_DATA_IN, -- in std_logic_vector(31 downto 0); + REGIO_READ_ENABLE_IN => REGIO_READ_ENABLE_IN, -- in std_logic; + REGIO_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_IN, -- in std_logic; + REGIO_DATA_OUT => REGIO_DATA_OUT, -- out std_logic_vector(31 downto 0); + REGIO_DATAREADY_OUT => REGIO_DATAREADY_OUT, -- out std_logic; + REGIO_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, -- out std_logic; + REGIO_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, -- out std_logic; + + -- CBMNet + CBMNET_CLK_IN => CBMNET_CLK_IN, -- in std_logic; + CBMNET_RESET_IN => CBMNET_RESET_IN, -- in std_logic; + CBMNET_LINK_ACTIVE_IN => CBMNET_LINK_ACTIVE_IN, -- in std_logic; + + CBMNET_DATA2SEND_STOP_IN => CBMNET_DATA2SEND_STOP_IN, -- in std_logic; + CBMNET_DATA2SEND_START_OUT => CBMNET_DATA2SEND_START_OUT, -- out std_logic; + CBMNET_DATA2SEND_END_OUT => CBMNET_DATA2SEND_END_OUT, -- out std_logic; + CBMNET_DATA2SEND_DATA_OUT =>CBMNET_DATA2SEND_DATA_OUT -- out std_logic_vector(15 downto 0) + ); + +end architecture; \ No newline at end of file -- 2.43.0