From 7a63bfcc3e4c14e1d5a954f84c2aed387332dbf0 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 8 Apr 2022 10:00:31 +0200 Subject: [PATCH] fixed open signals --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 21 ++++++++------- media_interfaces/sync/med_sync_control_RS.vhd | 2 +- media_interfaces/sync/rx_control_RS.vhd | 3 +-- media_interfaces/sync/sci_reader_RS.vhd | 26 +++++++++++-------- media_interfaces/sync/tx_control_RS.vhd | 3 ++- 5 files changed, 30 insertions(+), 25 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 7d97efe..3bef1e5 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -638,19 +638,20 @@ gen_control : for i in 0 to 3 generate end generate; gen_not_used : if (IS_MODE(i) = c_IS_UNUSED) generate - powerup_ch(i) <= '0'; -- keep in power down - rx_serdes_rst(i) <= '1'; -- keep in reset - rx_pcs_rst(i) <= '1'; -- keep in reset - wap_req_i(i) <= '0'; - rx_dlm_i(i) <= '0'; - MEDIA_MED2INT(i).dataready <= '0'; - MEDIA_MED2INT(i).tx_read <= '1'; - MEDIA_MED2INT(i).stat_op <= x"0007"; - cv_cnt(i) <= (others => '0'); - word_sync_i(i) <= '0'; + powerup_ch(i) <= '0'; -- keep in power down + rx_serdes_rst(i) <= '1'; -- keep in reset + rx_pcs_rst(i) <= '1'; -- keep in reset + wap_req_i(i) <= '0'; + rx_dlm_i(i) <= '0'; + MEDIA_MED2INT(i).dataready <= '0'; + MEDIA_MED2INT(i).tx_read <= '1'; + MEDIA_MED2INT(i).stat_op <= x"0007"; + cv_cnt(i) <= (others => '0'); + word_sync_i(i) <= '0'; RX_DLM_WORD_OUT(i*8+7 downto i*8) <= (others => '0'); rx_rst_i(i) <= '0'; rx_rst_word_i(i*8+7 downto i*8) <= (others => '0'); + debug_i(i*32+31 downto i*32) <= (others => '0'); end generate; end generate; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 0f7c652..97c377f 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -298,7 +298,7 @@ begin media_med2int_i.stat_op(4) <= link_active_qsys; -- rx_allow media_med2int_i.stat_op(3 downto 0) <= link_status_qsys; - link_status <= x"0" when (link_active_i = '1' ) else x"7"; + link_status <= x"0" when (link_active_i = '1') else x"7"; SYNC_MEDIA_SIGS : entity work.signal_sync generic map( diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index bedea8c..7580347 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -321,8 +321,7 @@ begin STAT_REG_OUT(7) <= ct_fifo_write; STAT_REG_OUT(15 downto 8) <= reg_rx_data_in when rising_edge(CLK_SYS); STAT_REG_OUT(16) <= rx_data(16); - STAT_REG_OUT(17) <= '0'; - STAT_REG_OUT(31 downto 18) <= (others => '0'); + STAT_REG_OUT(31 downto 17) <= (others => '0'); DEBUG_OUT(31 downto 0) <= (others => '0'); diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index 53dc0f0..de4ad43 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -39,8 +39,7 @@ end entity; architecture sci_reader_arch of sci_reader_RS is type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH, - W_RL, W_RL_WAIT, W_RL_WAIT2, W_RL_FINISH, W_RLS, W_RLS_WAIT, W_RLS_WAIT2, W_RLS_FINISH); ---type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); + W_RL_DECIDE, W_RL, W_RL_WAIT, W_RL_WAIT2, W_RL_FINISH, W_RLS, W_RLS_WAIT, W_RLS_WAIT2, W_RLS_FINISH); signal sci_state : sci_ctrl; signal sci_timer : unsigned(16 downto 0) := (others => '0'); @@ -49,6 +48,8 @@ signal sci_reg_i : std_logic; signal wa_position : std_logic_vector(15 downto 0); signal next_sci_wr : std_logic; +signal lb_onoff_i : std_logic; + begin ------------------------------------------------ @@ -93,12 +94,8 @@ begin ---------------------------------------- ---------------------------------------- elsif( LB_START_IN = '1' ) then - next_sci_wr <= '1'; - if( LB_ONOFF_IN = '1' ) then - sci_state <= W_RL; - else - sci_state <= W_RLS; - end if; + lb_onoff_i <= LB_ONOFF_IN; + sci_state <= W_RL_DECIDE; ---------------------------------------- ---------------------------------------- end if; @@ -124,13 +121,20 @@ begin sci_state <= IDLE; ---------------------------------------- ---------------------------------------- + when W_RL_DECIDE => + next_sci_wr <= '1'; + if( lb_onoff_i = '1' ) then + sci_state <= W_RL; + else + sci_state <= W_RLS; + end if; when W_RL => SCI_SEL <= '0' & LB_SEL_IN; SCI_ADDR <= b"010001"; -- x"11" for ECP3 - if( LB_ONOFF_IN = '1' ) then + if( lb_onoff_i = '1' ) then SCI_WRDATA <= x"21"; -- source of TX data is feedback else - SCI_WRDATA <= x"11"; -- source of TX data is normal + SCI_WRDATA <= x"01"; -- source of TX data is normal end if; SCI_RD <= '0'; sci_state <= W_RL_WAIT; @@ -151,7 +155,7 @@ begin end if; when W_RLS => SCI_ADDR <= b"010100"; -- x"14" for ECP3 - if( LB_ONOFF_IN = '1' ) then + if( lb_onoff_i = '1' ) then SCI_WRDATA <= x"69"; -- enable feedback else SCI_WRDATA <= x"09"; -- disable feedback diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 898f846..29defa7 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -233,7 +233,7 @@ begin -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM: process( CLK_TXI, CLEAR, link_active_qtx ) + THE_DATA_CONTROL_FSM: process( CLK_TXI, CLEAR ) begin if( CLEAR = '1' ) then current_state <= IDLE; @@ -399,6 +399,7 @@ begin STAT_REG_OUT(3 downto 0) <= state_bits; STAT_REG_OUT(7 downto 4) <= (others => '0'); STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr); + STAT_REG_OUT(16) <= '0'; STAT_REG_OUT(17) <= ram_empty; STAT_REG_OUT(18) <= link_active_qsys; STAT_REG_OUT(19) <= '0'; -- 2.43.0