From 7ab94f6162efc21e6b6d9166487bd8cce44be2f7 Mon Sep 17 00:00:00 2001
From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Fri, 27 Feb 2015 15:24:52 +0100
Subject: [PATCH] writing out the epoch counter

---
 ADC/source/adc_package.vhd          |  1 +
 ADC/source/adc_processor_cfd.vhd    | 14 +++++++++++++-
 ADC/source/adc_processor_cfd_ch.vhd |  1 +
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd
index 5bb492f..a8eebf9 100644
--- a/ADC/source/adc_package.vhd
+++ b/ADC/source/adc_package.vhd
@@ -80,6 +80,7 @@ package adc_package is
     InvalidWordCount : unsigned(31 downto 0);
     Baseline         : unsigned(RESOLUTION - 1 downto 0);
     LastWord         : unsigned(RESOLUTION - 1 downto 0);
+    EpochCounter     : unsigned(23 downto 0);
     Trigger          : std_logic;
   end record;
 
diff --git a/ADC/source/adc_processor_cfd.vhd b/ADC/source/adc_processor_cfd.vhd
index 00a5876..520a1dd 100644
--- a/ADC/source/adc_processor_cfd.vhd
+++ b/ADC/source/adc_processor_cfd.vhd
@@ -64,6 +64,11 @@ architecture arch of adc_processor_cfd is
   signal readout_reset  : std_logic                     := '0';
   signal busy_in_adc, busy_in_sys : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
   signal busy_out_adc, busy_out_sys : std_logic_vector(CHANNELS-1 downto 0) := (others => '0');
+  
+  type epoch_counter_t is array(CHANNELS - 1 downto 0) of unsigned(23 downto 0);
+  signal epoch_counter : epoch_counter_t;
+  
+  --signal trigger_delay : unsigned();
 begin
   CONF_adc <= CONFIG when rising_edge(CLK_ADC);
 
@@ -74,6 +79,7 @@ begin
   busy_out_sys <= busy_out_adc when rising_edge(CLK_SYS);
   gen_cfd : for i in 0 to CHANNELS - 1 generate
     trigger_gen(i) <= debug_adc(i).Trigger;
+    epoch_counter(i) <= debug_adc(i).EpochCounter when rising_edge(CLK_SYS);
     
     THE_CFD : entity work.adc_processor_cfd_ch
       generic map(
@@ -107,7 +113,6 @@ begin
   READOUT_TX.data_write <= RDO_write_main when rising_edge(CLK_SYS);
   READOUT_TX.data       <= RDO_data_main when rising_edge(CLK_SYS);
   readout_reset         <= CONTROL(12) when rising_edge(CLK_SYS);
-  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC);
 
   proc_readout : process
     variable channelselect : integer range 0 to 3;
@@ -157,6 +162,9 @@ begin
           end if;
         end if;
 
+      --when TRIG_DLY =>
+                
+
       when WAIT_BSY =>
         busy_in_sys(channelselect) <= '1';
         if busy_out_sys(channelselect) = '0' then
@@ -169,6 +177,8 @@ begin
       when WAIT_RAM =>
         busy_in_sys(channelselect) <= '1';
         ram_counter(channelselect) <= ram_counter(channelselect) + 1;
+        RDO_data_main <= x"cc" & std_logic_vector(epoch_counter(channelselect));
+        RDO_write_main <= '1'; 
         state <= READOUT;
         
           
@@ -204,6 +214,8 @@ begin
     end if;
   end process;
 
+  statebits             <= std_logic_vector(to_unsigned(state_t'pos(state), 8)) when rising_edge(CLK_ADC);
+  
   PROC_DEBUG_BUFFER : process
     variable c : integer range 0 to 3;
   begin
diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd
index 60a07cd..d602558 100644
--- a/ADC/source/adc_processor_cfd_ch.vhd
+++ b/ADC/source/adc_processor_cfd_ch.vhd
@@ -104,6 +104,7 @@ begin
   DEBUG.InvalidWordCount <= invalid_word_count;
   DEBUG.Baseline         <= baseline;
   DEBUG.LastWord         <= input;
+  DEBUG.EpochCounter     <= epoch_counter;
 
   -- word checker, needed for ADC phase adjustment
   gen_word_checker : for i in 0 to CHANNELS - 1 generate
-- 
2.43.0