From 7ae89ef90582bc2fe777f15841979f358900c5a7 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 24 Jun 2009 15:28:43 +0000 Subject: [PATCH] added regio bus handler, Jan --- compile_frankfurt.pl | 3 +- constraints.lpf | 12 +-- mdc_oepb.prj | 1 + mdc_oepb.vhd | 182 ++++++++++++++++++++++++++----------------- 4 files changed, 121 insertions(+), 77 deletions(-) diff --git a/compile_frankfurt.pl b/compile_frankfurt.pl index c305714..a84ba04 100755 --- a/compile_frankfurt.pl +++ b/compile_frankfurt.pl @@ -13,7 +13,8 @@ use warnings; use strict; my $lattice_path = '/d/sugar/lattice/ispLever7.2/isptools/'; -my $synplify_path = '/d/sugar/lattice/synplify/synOEM7.2/synplify_linux/'; +my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/'; + #my $synplify_path = '/home/hadaq/bin/'; use FileHandle; diff --git a/constraints.lpf b/constraints.lpf index 456f830..8f6f726 100644 --- a/constraints.lpf +++ b/constraints.lpf @@ -1,12 +1,12 @@ ################################################################# # Constraints ################################################################# - FREQUENCY PORT CLK 30 MHz; - FREQUENCY NET CLK_100 120 MHz; - FREQUENCY NET THE_MED_INTERFACE/ff_txfullclk 30 MHz; - FREQUENCY NET THE_MED_INTERFACE_ff_txfullclk 30 MHz; - FREQUENCY NET THE_MED_INTERFACE/ff_rxfullclk 30 MHz; - FREQUENCY NET THE_MED_INTERFACE_ff_rxfullclk 30 MHz; + FREQUENCY PORT CLK 25 MHz; + FREQUENCY NET CLK_100 100 MHz; + FREQUENCY NET THE_MED_INTERFACE/ff_txfullclk 25 MHz; + FREQUENCY NET THE_MED_INTERFACE_ff_txfullclk 25 MHz; + FREQUENCY NET THE_MED_INTERFACE/ff_rxfullclk 25 MHz; + FREQUENCY NET THE_MED_INTERFACE_ff_rxfullclk 25 MHz; BLOCK NET "reset" ; # MULTICYCLE FROM CELL reset 2.0 x; \ No newline at end of file diff --git a/mdc_oepb.prj b/mdc_oepb.prj index df38809..91e1db1 100644 --- a/mdc_oepb.prj +++ b/mdc_oepb.prj @@ -20,6 +20,7 @@ add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd" add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd" add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd" add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd" add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd" diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd index e2a1c78..5124842 100644 --- a/mdc_oepb.vhd +++ b/mdc_oepb.vhd @@ -156,6 +156,13 @@ architecture mdc_oepb_arch of mdc_oepb is signal motherboard_type_in_i : std_logic_vector(3 downto 0); signal pulse_begin_run_trigger_i : std_logic; + + + signal datbus_data_out : std_logic_vector(31 downto 0); + signal datbus_addr_out : std_logic_vector(15 downto 0); + signal datbus_timeout_out : std_logic; + + signal test_debug_i : std_logic_vector(7 downto 0); signal counter_led : unsigned(31 downto 0); signal reset_counter_led : std_logic; @@ -179,8 +186,13 @@ begin THE_RESET_COUNTER_PROC: process(CLK) begin if rising_edge(CLK) then - if SD = '0' or pll_locked = '0' then --MED_STAT_OP(14) = '1' then + if pll_locked = '0' then + reset_counter <= x"000F00"; + reset_internal <= '1'; + reset_startup <= '1'; + elsif MED_STAT_OP(14) = '1' then --MED_STAT_OP(14) = '1' then reset_counter <= x"000F00"; + reset_startup <= '0'; reset_internal <= '1'; elsif( reset_counter = x"000FEF" ) then reset_startup <= '0'; @@ -188,7 +200,6 @@ begin reset_counter <= x"000FEF"; else reset_counter <= reset_counter + "1"; - reset_startup <= '0'; reset_internal <= '1'; end if; end if; @@ -372,71 +383,102 @@ THE_REG_DAT_ADDR : process(CLK_100) end if; end process; +-- +-- THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) +-- begin +-- if rising_edge(CLK_100) then +-- REGIO_WRITE_ACK_IN <= '0'; +-- REGIO_NO_MORE_DATA_IN <= '0'; +-- REGIO_DATAREADY_IN <= '0'; +-- REGIO_DATA_IN <= (others => '0'); +-- REGIO_UNKNOWN_ADDR_IN <= '0'; +-- --adc +-- adc_read <= '0'; +-- adc_write <= '0'; +-- adc_data_in <= REGIO_DATA_OUT; +-- adc_addr <= REGIO_ADDR_OUT(5 downto 0); +-- adc_timeout <= REGIO_TIMEOUT_OUT; +-- +-- --configuration memory +-- thresh_mem_data <= REGIO_DATA_OUT(15 downto 0); +-- thresh_mem_addr <= REGIO_ADDR_OUT(8 downto 0);--(6 downto 0); +-- thresh_mem_write <= '0'; +-- thresh_mem_read <= '0'; +-- +-- --FEE control register +-- if reg_REGIO_ADDR(15 downto 12) = x"A" then +-- thresh_mem_write <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE; +-- thresh_mem_read <= reg_REGIO_READ; +-- REGIO_DATA_IN(15 downto 0) <= thresh_mem_data_out; +-- REGIO_DATA_IN(31 downto 16)<= (others => '0'); +-- REGIO_UNKNOWN_ADDR_IN <= '0'; +-- REGIO_NO_MORE_DATA_IN <= '0'; +-- REGIO_WRITE_ACK_IN <= reg_REGIO_WRITE; +-- REGIO_DATAREADY_IN <= very_last_reg_REGIO_READ; +-- +-- elsif reg_REGIO_ADDR(15 downto 8) = x"80" then +-- REGIO_DATA_IN <= adc_data_out; +-- REGIO_DATAREADY_IN <= adc_dataready; +-- REGIO_NO_MORE_DATA_IN <= adc_no_more_data; +-- REGIO_WRITE_ACK_IN <= adc_write_ack; +-- REGIO_UNKNOWN_ADDR_IN <= adc_unknown_addr; +-- adc_write <= reg_REGIO_WRITE; +-- adc_read <= reg_REGIO_READ; +-- +-- else +-- REGIO_UNKNOWN_ADDR_IN <= reg_REGIO_READ or reg_REGIO_WRITE; +-- end if; +-- end if; +-- end process; + + +THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"A000", 1 => x"8000", others => x"0000"), + PORT_ADDR_MASK => (0 => 8, 1 => 6, others => 0) + ) + port map( + CLK => CLK_100, + RESET => reset_internal, + --I/O to RegIO + DAT_ADDR_IN => REGIO_ADDR_OUT, + DAT_DATA_IN => REGIO_DATA_OUT, + DAT_DATA_OUT => REGIO_DATA_IN, + DAT_READ_ENABLE_IN => REGIO_READ_ENABLE_OUT, + DAT_WRITE_ENABLE_IN => REGIO_WRITE_ENABLE_OUT, + DAT_TIMEOUT_IN => REGIO_TIMEOUT_OUT, + DAT_DATAREADY_OUT => REGIO_DATAREADY_IN, + DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_IN, + DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_IN, + DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_IN, + --Bus Handler input on first port (Threshold memory) + BUS_READ_ENABLE_OUT(0) => thresh_mem_read, + BUS_WRITE_ENABLE_OUT(0) => thresh_mem_write, + BUS_DATA_OUT(0*32+15 downto 0*32) => thresh_mem_data, + BUS_ADDR_OUT(0*16+8 downto 0*16) => thresh_mem_addr, + BUS_TIMEOUT_OUT(0) => open, + BUS_DATA_IN(0*32+15 downto 0*32) => thresh_mem_data_out, + BUS_DATA_IN(0*32+31 downto 0*32+16) => x"0000", + BUS_DATAREADY_IN(0) => very_last_reg_REGIO_READ, + BUS_WRITE_ACK_IN(0) => reg_REGIO_WRITE, + BUS_NO_MORE_DATA_IN(0) => '0', + BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler input on second port (ADC) + BUS_READ_ENABLE_OUT(1) => adc_read, + BUS_WRITE_ENABLE_OUT(1) => adc_write, + BUS_DATA_OUT(1*32+31 downto 1*32) => adc_data_in, + BUS_ADDR_OUT(1*16+5 downto 1*16) => adc_addr, + BUS_TIMEOUT_OUT(1) => adc_timeout, + BUS_DATA_IN(1*32+31 downto 1*32) => adc_data_out, + BUS_DATAREADY_IN(1) => adc_dataready, + BUS_WRITE_ACK_IN(1) => adc_write_ack, + BUS_NO_MORE_DATA_IN(1) => adc_no_more_data, + BUS_UNKNOWN_ADDR_IN(1) => adc_unknown_addr, + --Debugging + STAT_DEBUG => open + ); -THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) - begin - if rising_edge(CLK_100) then - REGIO_WRITE_ACK_IN <= '0'; - REGIO_NO_MORE_DATA_IN <= '0'; - REGIO_DATAREADY_IN <= '0'; - REGIO_DATA_IN <= (others => '0'); - REGIO_UNKNOWN_ADDR_IN <= '0'; ---adc - adc_read <= '0'; - adc_write <= '0'; - adc_data_in <= REGIO_DATA_OUT; - adc_addr <= REGIO_ADDR_OUT(5 downto 0); - adc_timeout <= REGIO_TIMEOUT_OUT; - ---configuration memory - thresh_mem_data <= REGIO_DATA_OUT(15 downto 0); - thresh_mem_addr <= REGIO_ADDR_OUT(8 downto 0);--(6 downto 0); - thresh_mem_write <= '0'; - thresh_mem_read <= '0'; - ---FEE control register - if reg_REGIO_ADDR(15 downto 12) = x"A" then - thresh_mem_write <= REGIO_WRITE_ENABLE_OUT;--reg_REGIO_WRITE; - thresh_mem_read <= reg_REGIO_READ; - REGIO_DATA_IN(15 downto 0) <= thresh_mem_data_out; - REGIO_DATA_IN(31 downto 16)<= (others => '0'); - REGIO_UNKNOWN_ADDR_IN <= '0'; - REGIO_NO_MORE_DATA_IN <= '0'; - REGIO_WRITE_ACK_IN <= reg_REGIO_WRITE; - REGIO_DATAREADY_IN <= very_last_reg_REGIO_READ; - - elsif reg_REGIO_ADDR(15 downto 8) = x"80" then - REGIO_DATA_IN <= adc_data_out; - REGIO_DATAREADY_IN <= adc_dataready; - REGIO_NO_MORE_DATA_IN <= adc_no_more_data; - REGIO_WRITE_ACK_IN <= adc_write_ack; - REGIO_UNKNOWN_ADDR_IN <= adc_unknown_addr; - adc_write <= reg_REGIO_WRITE; - adc_read <= reg_REGIO_READ; - - else - REGIO_UNKNOWN_ADDR_IN <= reg_REGIO_READ or reg_REGIO_WRITE; - end if; - end if; - end process; - ---------------------------------------------------------------------- --- Threshold memory ---------------------------------------------------------------------- --- THE_THRESH_MEM : ram_dp --- generic map( --- depth => 7, --- width => 8 --- ) --- port map( --- CLK => CLK_100, --- wr1 => thresh_mem_write, --- a1 => thresh_mem_addr, --- dout1 => thresh_mem_data_out, --- din1 => thresh_mem_data, --- a2 => (others => '0'), --- dout2 => open --- ); --------------------------------------------------------------------- -- ADC @@ -475,7 +517,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) CLK => CLK_100, CLK_25 => CLK, CLK_EN => '1', - RESET => reset_internal, + RESET => reset_startup, --reset_internal, --Internal Connection MED_DATA_IN => MED_DATA_OUT, @@ -701,7 +743,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) -- D(3) <= not MED_STAT_DEBUG(7); -- D(4) <= not MED_STAT_DEBUG(8); --- D(1) <= IPU_START_READOUT_OUT; +-- D(1) <= IPU_START_READOUT_OUT; -- D(2) <= IPU_DATAREADY_IN; --to trbnet -- D(3) <= IPU_READOUT_FINISHED_IN; -- D(4) <= IPU_READ_OUT; --to fee readout @@ -721,9 +763,9 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 ) end if; end if; end process; - + D <= "1010" when (counter_led < x"00002710") else "0101"; - + --------------------------------------------------------------------- -- List of debugging signals --------------------------------------------------------------------- -- 2.43.0