From 7b2e1b499f30e9d830e8654ea6edd0c7caab28e4 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 25 Jul 2017 16:03:33 +0200 Subject: [PATCH] Update few bits of sync media interface reset handling --- media_interfaces/med_ecp5_sfp_sync.vhd | 29 ++-- media_interfaces/sync/med_sync_control.vhd | 27 +++- media_interfaces/sync/rx_control.vhd | 9 +- special/handler_ipu.vhd | 2 +- special/uart_rec.vhd | 161 +-------------------- special/uart_trans.vhd | 149 +------------------ 6 files changed, 47 insertions(+), 330 deletions(-) mode change 100644 => 120000 special/uart_rec.vhd mode change 100644 => 120000 special/uart_trans.vhd diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd index 2556739..9c9b892 100644 --- a/media_interfaces/med_ecp5_sfp_sync.vhd +++ b/media_interfaces/med_ecp5_sfp_sync.vhd @@ -7,6 +7,7 @@ USE IEEE.numeric_std.all; library work; use work.trb_net_std.all; +use work.config.all; use work.trb_net_components.all; use work.med_sync_define.all; @@ -59,8 +60,8 @@ architecture med_ecp5_sfp_sync_arch of med_ecp5_sfp_sync is -- signal clk_200_i : std_logic; signal clk_200_ref : std_logic; -signal clk_rx_full, clk_rx_half : std_logic; -signal clk_tx_full, clk_tx_half : std_logic; +signal clk_rx_full : std_logic; +signal clk_tx_full : std_logic; signal tx_data : std_logic_vector(7 downto 0); signal tx_k : std_logic; @@ -96,6 +97,7 @@ signal stat_tx_control_i : std_logic_vector(31 downto 0); signal debug_rx_control_i : std_logic_vector(31 downto 0); signal debug_tx_control_i : std_logic_vector(31 downto 0); signal stat_fsm_reset_i : std_logic_vector(31 downto 0); +signal debug_med_sync_control_i : std_logic_vector(31 downto 0); signal rx_ready, tx_ready : std_logic; signal hdinp, hdinn, hdoutp, hdoutn : std_logic; attribute nopad : string; @@ -107,8 +109,8 @@ begin clk_200_ref <= CLK_REF_FULL; --- SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -SD_TXDIS_OUT <= RESET; +SD_TXDIS_OUT <= not rx_ready when IS_SYNC_SLAVE = 1 else '0'; --slave only switches on when RX is ready +-- SD_TXDIS_OUT <= RESET; -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate -- clk_200_i <= clk_rx_full; @@ -163,13 +165,13 @@ gen_pcs0 : if SERDES_NUM = 0 generate serdes_sync_0_sci_wrn => sci_write_i, serdes_sync_0_sci_int => open, - serdes_sync_0_cyawstn => '1', --? + serdes_sync_0_cyawstn => '0', --? serdes_sync_0_rst_dual_c => rst_qd, serdes_sync_0_serdes_rst_dual_c => '0', serdes_sync_0_tx_pwrup_c => '1', serdes_sync_0_rx_pwrup_c => '1', serdes_sync_0_serdes_pdb => '1', - serdes_sync_0_tx_serdes_rst_c => '0', + serdes_sync_0_tx_serdes_rst_c => tx_serdes_rst, serdes_sync_0_pll_refclki => clk_200_ref, -- sli_rst => '0', @@ -181,7 +183,7 @@ gen_pcs0 : if SERDES_NUM = 0 generate ); end generate; - tx_serdes_rst <= '0'; --no function + tx_serdes_rst <= '0'; --SD_LOS_IN; --no function serdes_rst_qd <= '0'; --included in rst_qd wa_position_sel <= x"0"; -- wa_position_sel <= wa_position(3 downto 0) when SERDES_NUM = 0 @@ -229,7 +231,8 @@ THE_MED_CONTROL : entity work.med_sync_control STAT_RX_CONTROL => stat_rx_control_i, DEBUG_TX_CONTROL => debug_tx_control_i, DEBUG_RX_CONTROL => debug_rx_control_i, - STAT_RESET => stat_fsm_reset_i + STAT_RESET => stat_fsm_reset_i, + DEBUG_OUT => debug_med_sync_control_i ); THE_SCI_READER : entity work.sci_reader @@ -263,8 +266,14 @@ THE_SCI_READER : entity work.sci_reader -- STAT_DEBUG(7) <= '0'; -- STAT_DEBUG(15 downto 8) <= stat_fsm_reset_i(7 downto 0); -- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16); -STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); - +-- STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0); + STAT_DEBUG(3 downto 0) <= debug_med_sync_control_i(3 downto 0); + STAT_DEBUG(7 downto 4) <= rx_los_low & lsm_status & rx_cdr_lol & tx_pll_lol; + STAT_DEBUG(9) <= clk_200_ref; + STAT_DEBUG(10) <= clk_rx_full; + STAT_DEBUG(11) <= clk_tx_full; + + stat_med(0) <= rst_qd; stat_med(1) <= rx_pcs_rst; stat_med(2) <= tx_pcs_rst; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index c58eef8..56cca26 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -49,7 +49,8 @@ entity med_sync_control is STAT_RX_CONTROL : out std_logic_vector(31 downto 0); DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); - STAT_RESET : out std_logic_vector(31 downto 0) + STAT_RESET : out std_logic_vector(31 downto 0); + DEBUG_OUT : out std_logic_vector(31 downto 0) ); end entity; @@ -88,7 +89,11 @@ signal media_med2int_i : MED2INT; begin -rst_n_tx <= not (CLEAR or make_link_reset_real_i); +rst_n_tx <= not (CLEAR or sd_los_i or make_link_reset_real_i) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) + else not (CLEAR or make_link_reset_real_i); + + + rst_n <= not (CLEAR or sd_los_i or make_link_reset_real_i); reset_i <= (RESET or sd_los_i or make_link_reset_real_i); @@ -143,7 +148,7 @@ PROC_ALLOW : process begin else rx_allow <= '0'; end if; - if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then + if tx_fsm_state = x"5" and rx_fsm_state = x"6" and (IS_SYNC_SLAVE = 1 or start_timer(start_timer'left) = '1') then tx_allow <= '1'; else tx_allow <= '0'; @@ -269,7 +274,8 @@ STAT_RESET(15 downto 10) <= (others => '0'); STAT_RESET(16) <= RX_CDR_LOL; STAT_RESET(17) <= RX_LOS; STAT_RESET(18) <= RX_PCS_RST; -STAT_RESET(31 downto 19) <= (others => '0'); +STAT_RESET(19) <= '0'; +STAT_RESET(31 downto 20) <= start_timer(start_timer'left downto start_timer'left - 11); gen_link_reset : if IS_SYNC_SLAVE = 1 generate @@ -292,8 +298,15 @@ media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); media_med2int_i.stat_op(12) <= led_dlm when rising_edge(CLK_SYS); -- or last_led_dlm; media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx; media_med2int_i.stat_op(10) <= led_rx or last_led_rx; -media_med2int_i.stat_op(9) <= led_ok; -media_med2int_i.stat_op(8 downto 4) <= (others => '0'); +media_med2int_i.stat_op(9) <= tx_allow; --led_ok +media_med2int_i.stat_op(8) <= rx_allow; + +media_med2int_i.stat_op(7 downto 4) <= (others => '0'); media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7"; -end architecture; \ No newline at end of file +DEBUG_OUT(0) <= tx_allow; +DEBUG_OUT(1) <= rx_allow; +DEBUG_OUT(2) <= sd_los_i; +DEBUG_OUT(3) <= DEBUG_RX_CONTROL(4); + +end architecture; diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 2ddd92e..12af875 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -142,6 +142,7 @@ PROC_RX_FSM : process begin rx_state_bits <= x"1"; got_link_ready_i <= '0'; make_reset_i <= '0'; + rx_data(7 downto 0) <= reg_rx_data_in; if reg_rx_k_in = '1' and reg_rx_data_in = x"BC" then rx_state <= wAIT_1; end if; @@ -151,6 +152,7 @@ PROC_RX_FSM : process begin when FIRST => rx_state_bits <= x"2"; + rx_data(7 downto 0) <= reg_rx_data_in; if reg_rx_k_in = '1' then case reg_rx_data_in is when K_IDLE => @@ -165,7 +167,6 @@ PROC_RX_FSM : process begin when others => null; end case; else - rx_data(7 downto 0) <= reg_rx_data_in; rx_state <= GET_DATA; end if; @@ -267,7 +268,7 @@ STAT_REG_OUT(4) <= got_link_ready_i; STAT_REG_OUT(5) <= ct_fifo_afull; STAT_REG_OUT(6) <= ct_fifo_empty; STAT_REG_OUT(7) <= ct_fifo_write; -STAT_REG_OUT(15 downto 8) <= reg_rx_data_in(7 downto 0); +STAT_REG_OUT(15 downto 8) <= rx_data(7 downto 0); STAT_REG_OUT(16) <= rx_data(16); STAT_REG_OUT(17) <= '0'; STAT_REG_OUT(31 downto 18) <= (others => '0'); @@ -278,7 +279,7 @@ DEBUG_OUT(4) <= got_link_ready_i; DEBUG_OUT(5) <= ct_fifo_afull; DEBUG_OUT(6) <= ct_fifo_empty; DEBUG_OUT(7) <= ct_fifo_write; -DEBUG_OUT(15 downto 8) <= reg_rx_data_in(7 downto 0); +DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); DEBUG_OUT(16) <= reg_rx_k_in; DEBUG_OUT(17) <= make_reset_i; DEBUG_OUT(18) <= send_link_reset_i; @@ -290,4 +291,4 @@ DEBUG_OUT(31 downto 20) <= (others => '0'); -end architecture; \ No newline at end of file +end architecture; diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index 408d132..b48697a 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -264,7 +264,7 @@ begin hdr_fifo_valid_read <= next_hdr_fifo_valid_read; last_hdr_fifo_valid_read <= hdr_fifo_valid_read; if next_hdr_data_waiting = '1' then - total_length <= 0; + total_length <= (others => '0'); elsif last_hdr_fifo_valid_read = '1' then total_length <= next_total_length; end if; diff --git a/special/uart_rec.vhd b/special/uart_rec.vhd deleted file mode 100644 index f168832..0000000 --- a/special/uart_rec.vhd +++ /dev/null @@ -1,160 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - - -entity uart_rec is --- generic( --- CLK_DIV : integer --- ); - port( - CLK_DIV : in integer; - CLK : in std_logic; - RST : in std_logic; - RX : in std_logic; - - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_WAITING : out std_logic; - DEBUG : out std_logic_vector(3 downto 0) - ); -end entity; - - - -architecture uart_rec_arch of uart_rec is - -signal clk_div_counter: unsigned(15 downto 0) := x"0000"; -signal symbol_pulse : std_logic := '0'; -signal symbol_counter: unsigned(3 downto 0) := x"0"; - -type state_type is (idle,receiving,update_parallel_output); -signal state: state_type := idle; - --- MSB is the stopbit, LSB is the start bit, both are never changed -signal rx_shift_register: std_logic_vector(9 downto 0); -signal symbol : std_logic := '1'; -signal data_waiting_sig: std_logic := '0'; -signal current_data_out: std_logic_vector(7 downto 0) := "00000000"; -signal symbol_start_pulse : std_logic := '0'; -- just debug -signal rst_clk_div_counter : std_logic; -signal rx_reg : std_logic; - -begin ----------------------------- --- debug ----------------------------- - -DEBUG(0) <= symbol_start_pulse; -DEBUG(1) <= symbol_pulse; -DEBUG(2) <= data_waiting_sig; -DEBUG(3) <= '0'; - ----------------------------- --- Inputs ----------------------------- - sync_input : process begin - wait until rising_edge(CLK); - rx_reg <= RX; - symbol <= rx_reg; - end process; - ----------------------------- --- Outputs ----------------------------- - sync_output : process begin - wait until rising_edge(CLK); - DATA_WAITING <= data_waiting_sig; - DATA_OUT <= current_data_out; - end process; - ----------------------------- --- Generate Serial Clock ----------------------------- - clock_division : process begin - wait until rising_edge(CLK); - -- scaling down the main clock to the desired baudrate - if clk_div_counter = to_unsigned(CLK_DIV,16)-1 then - clk_div_counter <= x"0000"; - else - clk_div_counter <= clk_div_counter + 1; - end if; - -- generates symbol_pulse, a signal that has 1 clock cycle pulses, one symbol duration period apart - -- in contrast to the transceiver module, the symbol pulse is generated in the middle of the - -- symbol period - -- if clk_div_counter = '0' & CLK_DIV(15 downto 1) then -- CLK_DIV/2 by >> (right shifting) - if clk_div_counter = to_unsigned(CLK_DIV/2,16) then - symbol_pulse <= '1'; - else - symbol_pulse <= '0'; - end if; - - if clk_div_counter = x"0000" then - symbol_start_pulse <= '1'; - else - symbol_start_pulse <= '0'; - end if; - if (RST or rst_clk_div_counter) = '1' then - clk_div_counter <= x"0000"; - end if; - - end process; - ----------------------------- --- State Machine of the Receiver ----------------------------- - state_machine : process begin - wait until rising_edge(CLK); - data_waiting_sig <= '0'; - rst_clk_div_counter <= '0'; - - -- state machine rules: - case state is - when idle => - rst_clk_div_counter<= '1'; - if symbol = '0' then -- the start bit comes! - state <= receiving; - -- restart the divcounter - -- clk_div_counter <= x"0000"; - symbol_counter <= x"0"; - - end if; - - when receiving => - if symbol_pulse = '1' then - if symbol_counter <= x"9" then -- reception process - rx_shift_register(to_integer(symbol_counter)) <= symbol; - symbol_counter <= symbol_counter + 1; - end if; - if symbol_counter = x"9" then - state <= update_parallel_output; - end if; - - - end if; - when update_parallel_output => - -- check start and stop bit consistency - -- (checking the start bit again seems a little obsolete) - -- only if bit was received correctly output the data! --- if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then - if symbol = '1' then - state <= idle; - if rx_shift_register(0) = '0' and rx_shift_register(9) = '1' then - current_data_out <= rx_shift_register(8 downto 1); - data_waiting_sig <= '1'; - end if; - end if; - - end case; - - -- reset clock divider counters when reset signal is on - if RST = '1' then - symbol_counter <= x"0"; - data_waiting_sig <= '0'; - state <= idle; - end if; - - end process; - - -end architecture; \ No newline at end of file diff --git a/special/uart_rec.vhd b/special/uart_rec.vhd new file mode 120000 index 0000000..054bb8b --- /dev/null +++ b/special/uart_rec.vhd @@ -0,0 +1 @@ +../../vhdlbasics/interface/code/uart_rec.vhd \ No newline at end of file diff --git a/special/uart_trans.vhd b/special/uart_trans.vhd deleted file mode 100644 index 01967dc..0000000 --- a/special/uart_trans.vhd +++ /dev/null @@ -1,148 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - - -entity uart_trans is --- generic( --- CLK_DIV : integer --- ); - port( - CLK_DIV : in integer; - CLK : in std_logic; - RST : in std_logic; - - DATA_IN : in std_logic_vector(7 downto 0); - SEND : in std_logic; - READY : out std_logic; - - TX : out std_logic; - DEBUG : out std_logic_vector(3 downto 0) - - ); -end entity; - - - -architecture uart_trans_arch of uart_trans is - - - -signal clk_div_counter: unsigned(15 downto 0) := x"0000"; -signal symbol_start_pulse : std_logic := '0'; -signal symbol_counter: unsigned(3 downto 0) := x"0"; - -type state_type is (idle,transmitting); -signal state: state_type := idle; - --- MSB is the stopbit, LSB is the start bit, both are never changed -signal tx_shift_register: std_logic_vector(9 downto 0) := "1000000000"; -signal symbol: std_logic := '1'; -signal ready_sig: std_logic := '1'; -signal rst_clk_div_counter : std_logic; - - -begin ----------------------------- --- debug ----------------------------- - -DEBUG(0) <= symbol_start_pulse; -DEBUG(1) <= '0'; -DEBUG(2) <= ready_sig; -DEBUG(3) <= '0'; - ----------------------------- --- Inputs ----------------------------- --- sync_input : process begin --- wait until rising_edge(CLK); --- synced_send <= SEND; --- end process; --- hard wired stuff - ----------------------------- --- Outputs ----------------------------- - sync_output : process begin - wait until rising_edge(CLK); - TX <= symbol; - end process; - - READY <= ready_sig and not SEND; - ----------------------------- --- Generate Serial Clock ----------------------------- - clock_division : process begin - wait until rising_edge(CLK); - -- scaling down the main clock to the desired baudrate - if clk_div_counter = to_unsigned(CLK_DIV,16)-1 then - clk_div_counter <= x"0000"; - else - clk_div_counter <= clk_div_counter + 1; - end if; - - - if clk_div_counter = x"0001" then - symbol_start_pulse <= '1'; - else - symbol_start_pulse <= '0'; - end if; - if (RST or rst_clk_div_counter) = '1' then - clk_div_counter <= x"0000"; - end if; - - end process; - ----------------------------- --- State Machine of the Transmitter ----------------------------- - - state_machine : process begin - wait until rising_edge(CLK); - -- state machine rules: - rst_clk_div_counter <= '0'; - - case state is - when idle => - rst_clk_div_counter <= '1'; - ready_sig <= '1'; - if SEND = '1' then - state <= transmitting; - symbol_counter <= x"0"; - -- capture the byte at the parallel input - tx_shift_register <= '1' & DATA_IN & '0'; - ready_sig <= '0'; - end if; - - when transmitting => - if symbol_start_pulse = '1' then - if symbol_counter <= 9 then -- transmission process - symbol <= tx_shift_register(to_integer(symbol_counter)); - end if; - - symbol_counter <= symbol_counter + 1; - if symbol_counter = 10 then -- pulse #10 (1 start, 8 data, 1 stop) has been sent - --, time to go to idle mode again - -- pull the tx line high again, actually obsolete, because stop bit is 1 - symbol <= '1'; - state <= idle; - end if; - end if; - end case; - - -- reset clock divider counters when reset signal is on - if RST = '1' then - state <= idle; - ready_sig <= '1'; - symbol <= '1'; - end if; - - end process; - - - -end architecture; - diff --git a/special/uart_trans.vhd b/special/uart_trans.vhd new file mode 120000 index 0000000..dd3b3f8 --- /dev/null +++ b/special/uart_trans.vhd @@ -0,0 +1 @@ +../../vhdlbasics/interface/code/uart_trans.vhd \ No newline at end of file -- 2.43.0