From 7c07bb5fb9d945e7b035d95d775c8d2773aca915 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 7 Aug 2012 14:57:35 +0000 Subject: [PATCH] *** empty log message *** --- base/panda_dirc_wasa1.lpf | 134 ++++++++++++++++++++++++++++++++++++++ base/trb3_components.vhd | 9 +-- base/trb3_periph_hub.lpf | 2 - base/trb3_periph_mvd.lpf | 0 4 files changed, 135 insertions(+), 10 deletions(-) create mode 100644 base/panda_dirc_wasa1.lpf create mode 100644 base/trb3_periph_mvd.lpf diff --git a/base/panda_dirc_wasa1.lpf b/base/panda_dirc_wasa1.lpf new file mode 100644 index 0000000..ed06871 --- /dev/null +++ b/base/panda_dirc_wasa1.lpf @@ -0,0 +1,134 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 133.00 JTAG_PORT = ENABLE; +FREQUENCY NET clk_i 133 MHz; +FREQUENCY NET clk_i_inferred_clock 133 MHz; +# +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + +MULTICYCLE FROM PORT "SPI_*" 20.000000 ns ; +MULTICYCLE TO PORT "SPI_*" 20.000000 ns ; + +################################################################# +# I/O +################################################################# + + +LOCATE COMP "CON_1" SITE "A4"; +LOCATE COMP "CON_2" SITE "A5"; +LOCATE COMP "CON_3" SITE "A3"; +LOCATE COMP "CON_4" SITE "D6"; +LOCATE COMP "CON_5" SITE "B7"; +LOCATE COMP "CON_6" SITE "F7"; +LOCATE COMP "CON_7" SITE "C8"; +LOCATE COMP "CON_8" SITE "D8"; +LOCATE COMP "CON_9" SITE "F8"; +LOCATE COMP "CON_10" SITE "B9"; +LOCATE COMP "CON_11" SITE "F9"; +LOCATE COMP "CON_12" SITE "D10"; +LOCATE COMP "CON_13" SITE "A11"; +LOCATE COMP "CON_14" SITE "B11"; +LOCATE COMP "CON_15" SITE "B13"; +LOCATE COMP "CON_16" SITE "C12"; +DEFINE PORT GROUP "CON_group" "CON*" ; +IOBUF GROUP "CON_group" IO_TYPE=LVDS25; + + +LOCATE COMP "INP_1" SITE "T2"; +LOCATE COMP "INP_2" SITE "T3"; +LOCATE COMP "INP_3" SITE "P4"; +LOCATE COMP "INP_4" SITE "R5"; +LOCATE COMP "INP_5" SITE "T5"; +LOCATE COMP "INP_6" SITE "P6"; +LOCATE COMP "INP_7" SITE "R7"; +LOCATE COMP "INP_8" SITE "N6"; +LOCATE COMP "INP_9" SITE "M6"; +LOCATE COMP "INP_10" SITE "M7"; +LOCATE COMP "INP_11" SITE "T7"; +LOCATE COMP "INP_12" SITE "P8"; +LOCATE COMP "INP_13" SITE "N8"; +LOCATE COMP "INP_14" SITE "T9"; +LOCATE COMP "INP_15" SITE "R9"; +LOCATE COMP "INP_16" SITE "M8"; +DEFINE PORT GROUP "INP_group" "INP*" ; +IOBUF GROUP "INP_group" IO_TYPE=LVDS25; + + +LOCATE COMP "PWM_1" SITE "R1"; +LOCATE COMP "PWM_2" SITE "P1"; +LOCATE COMP "PWM_3" SITE "N3"; +LOCATE COMP "PWM_4" SITE "N1"; +LOCATE COMP "PWM_5" SITE "M3"; +LOCATE COMP "PWM_6" SITE "M1"; +LOCATE COMP "PWM_7" SITE "L1"; +LOCATE COMP "PWM_8" SITE "K4"; +LOCATE COMP "PWM_9" SITE "H6"; +LOCATE COMP "PWM_10" SITE "G2"; +LOCATE COMP "PWM_11" SITE "F1"; +LOCATE COMP "PWM_12" SITE "E2"; +LOCATE COMP "PWM_13" SITE "E1"; +LOCATE COMP "PWM_14" SITE "D1"; +LOCATE COMP "PWM_15" SITE "C2"; +LOCATE COMP "PWM_16" SITE "B1"; +DEFINE PORT GROUP "PWM_group" "PWM*" ; +IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; + + +LOCATE COMP "SPARE_LINE_0" SITE "R13"; +LOCATE COMP "SPARE_LINE_1" SITE "T14"; +LOCATE COMP "SPARE_LINE_2" SITE "R11"; +LOCATE COMP "SPARE_LINE_3" SITE "T12"; +LOCATE COMP "SPARE_LINE_4" SITE "C4"; +LOCATE COMP "SPARE_LINE_5" SITE "B5"; +DEFINE PORT GROUP "SPARE_LINE_group" "SPARE_LINE*" ; +IOBUF GROUP "SPARE_LINE_group" IO_TYPE=LVCMOS33; + + +LOCATE COMP "LED_GREEN" SITE "N16"; +LOCATE COMP "LED_ORANGE" SITE "N14"; +LOCATE COMP "LED_RED" SITE "P15"; +LOCATE COMP "LED_YELLOW" SITE "R16"; +DEFINE PORT GROUP "LED_group" "LED*" ; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33 DRIVE=8; + + +LOCATE COMP "SPI_CLK" SITE "T15"; +LOCATE COMP "SPI_CS" SITE "P12"; +LOCATE COMP "SPI_IN" SITE "R12"; +LOCATE COMP "SPI_OUT" SITE "B14"; + +IOBUF PORT "SPI_CLK" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "SPI_CS" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "SPI_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; +IOBUF PORT "SPI_OUT" IO_TYPE=LVDS25; + +LOCATE COMP "TEMP_LINE" SITE "L12"; +IOBUF PORT "TEMP_LINE" IO_TYPE=LVCMOS33 PULLMODE=UP; + +LOCATE COMP "TEST_LINE_0" SITE "D14"; +LOCATE COMP "TEST_LINE_1" SITE "E15"; +LOCATE COMP "TEST_LINE_2" SITE "C15"; +LOCATE COMP "TEST_LINE_3" SITE "B16"; +LOCATE COMP "TEST_LINE_4" SITE "D16"; +LOCATE COMP "TEST_LINE_5" SITE "E14"; +LOCATE COMP "TEST_LINE_6" SITE "C16"; +LOCATE COMP "TEST_LINE_7" SITE "D15"; +LOCATE COMP "TEST_LINE_8" SITE "E16"; +LOCATE COMP "TEST_LINE_9" SITE "F15"; +LOCATE COMP "TEST_LINE_10" SITE "F13"; +LOCATE COMP "TEST_LINE_11" SITE "G12"; +LOCATE COMP "TEST_LINE_12" SITE "F14"; +LOCATE COMP "TEST_LINE_13" SITE "F16"; +LOCATE COMP "TEST_LINE_14" SITE "F12"; +LOCATE COMP "TEST_LINE_15" SITE "G13"; +DEFINE PORT GROUP "TEST_group" "TEST*" ; +IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS33 DRIVE=8; diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index f125132..ffc702d 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -169,14 +169,7 @@ component ROM_Encoder Q : out std_logic_vector(7 downto 0)); end component; -component ROM_FIFO - port ( - Address : in std_logic_vector(7 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(3 downto 0)); -end component; + component bit_sync generic ( diff --git a/base/trb3_periph_hub.lpf b/base/trb3_periph_hub.lpf index 022068f..6071fee 100644 --- a/base/trb3_periph_hub.lpf +++ b/base/trb3_periph_hub.lpf @@ -155,8 +155,6 @@ DEFINE PORT GROUP "SFP_group" "SFP*" ; IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP; - - ################################################################# # Additional Lines to AddOn ################################################################# diff --git a/base/trb3_periph_mvd.lpf b/base/trb3_periph_mvd.lpf new file mode 100644 index 0000000..e69de29 -- 2.43.0