From 7e373726c45c15bfd627426057c7bf2ee0e1e47c Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 27 Jul 2016 10:17:58 +0200 Subject: [PATCH] Add ports for MBS master to CTS description --- trb3/CtsFeatures.tex | 1 + trb3/CtsHowtos.tex | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/trb3/CtsFeatures.tex b/trb3/CtsFeatures.tex index d5fcbd7..4e9d9da 100644 --- a/trb3/CtsFeatures.tex +++ b/trb3/CtsFeatures.tex @@ -11,6 +11,7 @@ \item \textbf{Up to 16 independent trigger modules} to implement complex behaviour. \item \textbf{8 general purpose trigger inputs} with independent spike rejection and delay lines. \item \textbf{4 channel TDC} to determine the trigger time with a resolution of 20~ps. + \item \textbf{MBS master} Sends out a MBS trigger word for each trigger on a serial LVDS line parallel to a 50 MHz clock \item \textbf{Run-time configurable periodical and random pulsers modules}. The mCTS supports regular and (pseudo-)random pulsers to produce trigger decisions with an (average) interval of 10~ns to 40~s. \item \textbf{Run-time configurable Coincidence detection} based on the general purpose inputs. Criterion can be diff --git a/trb3/CtsHowtos.tex b/trb3/CtsHowtos.tex index bb6f926..423add0 100644 --- a/trb3/CtsHowtos.tex +++ b/trb3/CtsHowtos.tex @@ -40,9 +40,9 @@ for the ETM. \begin{tabularx}{\textwidth}{lllllX} \hline Signal & FPGA Loc & Conn. & Wire & Usage\\ \hline\hline - CLK\_EXT(3) & U9 (P) & Clock & 4 blue & TriggerIn0 / MbsIn / A2Data\\ + CLK\_EXT(3) & U9 (P) & Clock & 4 blue & TriggerIn0 / MbsIn / MbsOut / A2Data\\ & U8 (N) & Clock & 5 wh/blue & \\ - CLK\_EXT(4) & Y34 (P) & Clock & 7 wh/brown & TriggerIn1 / A2Clk\\ + CLK\_EXT(4) & Y34 (P) & Clock & 7 wh/brown & TriggerIn1 / MbsClkOut / A2Clk\\ & Y33 (N) & Clock & 8 brown & \\ \hline TRIGGER\_IN & -- & Trigger & 1 wh/orange & Global Reference Time (on non-CTS)\\ -- 2.43.0