From 7eb0eeaa9c48784dac6465cdbac987d04501ca26 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 19 Aug 2009 08:54:20 +0000 Subject: [PATCH] untested media interface with reset --- media_interfaces/trb_net16_lsm_sfp.vhd | 2 +- .../trb_net16_med_ecp_sfp_4_gbe.vhd | 72 ++++--- .../trb_net16_med_ecp_sfp_gbe.vhd | 175 +++++++++++------- trb_net_components.vhd | 65 +++---- 4 files changed, 179 insertions(+), 135 deletions(-) diff --git a/media_interfaces/trb_net16_lsm_sfp.vhd b/media_interfaces/trb_net16_lsm_sfp.vhd index 141a96c..bb10bfb 100644 --- a/media_interfaces/trb_net16_lsm_sfp.vhd +++ b/media_interfaces/trb_net16_lsm_sfp.vhd @@ -280,7 +280,7 @@ begin next_rx_allow <= '1'; next_reset_me <= '0'; next_med_error <= ERROR_WAIT; - elsif( (timing_ctr(28) = '1') and (rst_tctr = '0') ) then -- we could use [29:0] as counter and use [29] here + elsif( (timing_ctr(28) = '1') and (rst_tctr = '0') ) then -- we could use [29:0] as counter and use [29] here NEXT_STATE <= LINK; -- wait cycle done, allow transmission of data next_rst_tctr <= '1'; next_rx_allow <= '1'; diff --git a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd index efdc865..ec1bf76 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd @@ -275,6 +275,12 @@ component serdes_gbe_all is attribute syn_keep : boolean; attribute syn_keep of led_counter : signal is true; + + signal reset_word_cnt : std_logic_vector(19 downto 0); + signal make_trbnet_reset : std_logic_vector(3 downto 0); + signal send_reset_words : std_logic_vector(3 downto 0); + + signal tx_correct : std_logic_vector(7 downto 0); signal first_idle : std_logic_vector(3 downto 0); @@ -288,7 +294,7 @@ begin PROC_RESET : process(SYSCLK) begin if rising_edge(SYSCLK) then - reset_i(i) <= RESET or CTRL_OP(i*16+14); + reset_i(i) <= RESET or CTRL_OP(i*16+13); pwr_up(i) <= '1'; --not CTRL_OP(i*16+14); end if; end process; @@ -754,6 +760,33 @@ begin buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3); med_read_out(i) <= tx_allow_q(i); + + + THE_CNT_RESET_PROC : process( sysclk ) + begin + if rising_edge(sysclk) then + if reset_i(i) = '1' then + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); + else + send_reset_words(i) <= '0'; + make_trbnet_reset(i) <= '0'; + if fifo_rx_din(i*18+17 downto i*18) = "11" & x"FEFE" then + if reset_word_cnt(i*5+4) = '0' then + reset_word_cnt(i*5+4 downto i*5) <= reset_word_cnt(i*5+4 downto i*5) + 1; + else + send_reset_words(i) <= '1'; + end if; + else + reset_word_cnt(i*5+4 downto i*5) <= (others => '0'); + make_trbnet_reset(i) <= reset_word_cnt(i*5+4); + end if; + end if; + end if; + end process; + + THE_SYNC_PROC: process( SYSCLK ) begin if( rising_edge(SYSCLK) ) then @@ -825,6 +858,9 @@ begin tx_data(i*16+15 downto i*16) <= x"50bc"; tx_k(i*2+1 downto i*2) <= "01"; tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0'; + elsif CTRL_OP(i*16+15) = '1' then + tx_data(i*16+15 downto i*16) <= x"FEFE"; + tx_k(i*2+1 downto i*2) <= "11"; else tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18+0); tx_k(i*2+1 downto i*2) <= "00"; @@ -834,27 +870,6 @@ begin end process; -THE_SERDES_INPUT_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - last_fifo_tx_empty <= fifo_tx_empty; - first_idle <= not last_fifo_tx_empty and fifo_tx_empty; - if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then - tx_data <= x"50bc"; - tx_k <= "01"; - tx_correct <= first_idle & '0'; --- elsif send_resync = '1' then --- tx_data <= x"FEFE"; --- tx_k <= "11"; - else - tx_data <= fifo_tx_dout(15 downto 0); - tx_k <= "00"; - tx_correct <= "00"; - end if; - end if; -end process THE_SERDES_INPUT_PROC; - - --------------------------------------------------------------------- --LED Signals --------------------------------------------------------------------- @@ -880,10 +895,15 @@ end process THE_SERDES_INPUT_PROC; --------------------------------------------------------------------- - STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0); - STAT_OP(i*16+10) <= rx_led(i); - STAT_OP(i*16+11) <= tx_led(i); - STAT_OP(i*16+15 downto i*16+12) <= FSM_STAT_OP(i*16+15 downto i*16+12); + STAT_OP(i*16+15) <= send_reset_words(i); + STAT_OP(i*16+14) <= FSM_STAT_OP(i*16+14); + STAT_OP(i*16+13) <= make_trbnet_reset(i); + STAT_OP(i*16+12) <= '0'; + STAT_OP(i*16+11) <= tx_led(i); + STAT_OP(i*16+10) <= rx_led(i); + STAT_OP(i*16+9 downto i*16+0) <= FSM_STAT_OP(i*16+9 downto i*16+0); + +-- STAT_OP(i*16+15 downto i*16+12) <= FSM_STAT_OP(i*16+15 downto i*16+12); FSM_CTRL_OP(i*16+15 downto i*16+0) <= CTRL_OP(i*16+15 downto i*16+0); STAT_DEBUG(i*64+31 downto i*64+0) <= FSM_STAT_DEBUG(i*32+31 downto i*32); diff --git a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd index f66de55..e34ad01 100755 --- a/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd +++ b/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd @@ -350,7 +350,7 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is signal buf_STAT_OP : std_logic_vector(15 downto 0); - signal led_counter : std_logic_vector(17 downto 0); + signal led_counter : std_logic_vector(16 downto 0); signal rx_led : std_logic; signal tx_led : std_logic; attribute syn_keep : boolean; @@ -360,6 +360,9 @@ architecture med_ecp_sfp of trb_net16_med_ecp_sfp_gbe is signal tx_correct : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion signal first_idle : std_logic; -- tag the first IDLE2 after data + signal reset_word_cnt : std_logic_vector(4 downto 0); + signal make_trbnet_reset : std_logic; + signal send_reset_words : std_logic; signal reset_i : std_logic; signal pwr_up : std_logic; @@ -372,7 +375,7 @@ begin PROC_RESET : process(SYSCLK) begin if rising_edge(SYSCLK) then - reset_i <= RESET or CTRL_OP(14); + reset_i <= RESET or CTRL_OP(13); pwr_up <= '1'; --not CTRL_OP(i*16+14); end if; end process; @@ -754,73 +757,100 @@ fifo_rx_rd_en <= '1'; -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path THE_BYTE_SWAP_PROC: process( sysclk ) -- CHANGED -begin - if( rising_edge(sysclk) ) then -- CHANGED - last_rx <= rx_k(1) & rx_data(15 downto 8); - if( swap_bytes = '0' ) then - fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); - fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); - else - fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); - fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + begin + if( rising_edge(sysclk) ) then -- CHANGED + last_rx <= rx_k(1) & rx_data(15 downto 8); + if( swap_bytes = '0' ) then + fifo_rx_din <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0); + fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0); + else + fifo_rx_din <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0); + fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0); + end if; end if; - end if; -end process THE_BYTE_SWAP_PROC; + end process THE_BYTE_SWAP_PROC; buf_med_data_out <= fifo_rx_dout(15 downto 0); buf_med_dataready_out <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q; buf_med_packet_num_out <= rx_counter; med_read_out <= tx_allow_q; + +THE_CNT_RESET_PROC : process( sysclk ) + begin + if rising_edge(sysclk) then + if reset_i = '1' then + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + reset_word_cnt <= (others => '0'); + else + send_reset_words <= '0'; + make_trbnet_reset <= '0'; + if fifo_rx_din = "11" & x"FEFE" then + if reset_word_cnt(4) = '0' then + reset_word_cnt <= reset_word_cnt + 1; + else + send_reset_words <= '1'; + end if; + else + reset_word_cnt <= (others => '0'); + make_trbnet_reset <= reset_word_cnt(4); + end if; + end if; + end if; + end process; + + THE_SYNC_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - if reset_i = '1' then - med_dataready_out <= '0'; - else - med_dataready_out <= buf_med_dataready_out; - med_data_out <= buf_med_data_out; - med_packet_num_out <= buf_med_packet_num_out; + begin + if( rising_edge(sysclk) ) then + if reset_i = '1' then + med_dataready_out <= '0'; + else + med_dataready_out <= buf_med_dataready_out; + med_data_out <= buf_med_data_out; + med_packet_num_out <= buf_med_packet_num_out; + end if; end if; - end if; -end process THE_SYNC_PROC; + end process THE_SYNC_PROC; + --rx packet counter --------------------- THE_RX_PACKETS_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - last_fifo_rx_empty <= fifo_rx_empty; - if reset_i = '1' or rx_allow_q = '0' then - rx_counter <= c_H0; - else - if( buf_med_dataready_out = '1' ) then - if( rx_counter = c_max_word_number ) then - rx_counter <= (others => '0'); - else - rx_counter <= rx_counter + 1; + begin + if( rising_edge(sysclk) ) then + last_fifo_rx_empty <= fifo_rx_empty; + if reset_i = '1' or rx_allow_q = '0' then + rx_counter <= c_H0; + else + if( buf_med_dataready_out = '1' ) then + if( rx_counter = c_max_word_number ) then + rx_counter <= (others => '0'); + else + rx_counter <= rx_counter + 1; + end if; end if; end if; end if; - end if; -end process; + end process; --TX Fifo & Data output to Serdes --------------------- THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport -generic map( - USE_STATUS_FLAGS => c_NO - ) -port map( read_clock_in => sysclk, - write_clock_in => sysclk, - read_enable_in => fifo_tx_rd_en, - write_enable_in => fifo_tx_wr_en, - fifo_gsr_in => fifo_tx_reset, - write_data_in => fifo_tx_din, - read_data_out => fifo_tx_dout, - full_out => fifo_tx_full, - empty_out => fifo_tx_empty - ); + generic map( + USE_STATUS_FLAGS => c_NO + ) + port map( read_clock_in => sysclk, + write_clock_in => sysclk, + read_enable_in => fifo_tx_rd_en, + write_enable_in => fifo_tx_wr_en, + fifo_gsr_in => fifo_tx_reset, + write_data_in => fifo_tx_din, + read_data_out => fifo_tx_dout, + full_out => fifo_tx_full, + empty_out => fifo_tx_empty + ); fifo_tx_reset <= reset_i or not tx_allow_q; fifo_tx_din <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in; @@ -829,29 +859,29 @@ fifo_tx_rd_en <= tx_allow; THE_SERDES_INPUT_PROC: process( sysclk ) -begin - if( rising_edge(sysclk) ) then - last_fifo_tx_empty <= fifo_tx_empty; - first_idle <= not last_fifo_tx_empty and fifo_tx_empty; - if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then - tx_data <= x"50bc"; - tx_k <= "01"; - tx_correct <= first_idle & '0'; --- elsif send_resync = '1' then --- tx_data <= x"FEFE"; --- tx_k <= "11"; - else - tx_data <= fifo_tx_dout(15 downto 0); - tx_k <= "00"; - tx_correct <= "00"; + begin + if( rising_edge(sysclk) ) then + last_fifo_tx_empty <= fifo_tx_empty; + first_idle <= not last_fifo_tx_empty and fifo_tx_empty; + if( (last_fifo_tx_empty = '1') or (tx_allow = '0') ) then + tx_data <= x"50bc"; + tx_k <= "01"; + tx_correct <= first_idle & '0'; + elsif CTRL_OP(15) = '1' then + tx_data <= x"FEFE"; + tx_k <= "11"; + else + tx_data <= fifo_tx_dout(15 downto 0); + tx_k <= "00"; + tx_correct <= "00"; + end if; end if; - end if; -end process THE_SERDES_INPUT_PROC; + end process THE_SERDES_INPUT_PROC; --Generate LED signals ---------------------- -process(sysclk) +process( sysclk ) begin if rising_edge(sysclk) then led_counter <= led_counter + 1; @@ -871,7 +901,10 @@ process(sysclk) end if; end process; -stat_op(15 downto 12) <= buf_stat_op(15 downto 12); +stat_op(15) <= send_reset_words; +stat_op(14) <= buf_stat_op(14); +stat_op(13) <= make_trbnet_reset; +stat_op(12) <= '0'; stat_op(11) <= tx_led; --tx led stat_op(10) <= rx_led; --rx led stat_op(9 downto 0) <= buf_stat_op(9 downto 0); @@ -882,10 +915,10 @@ stat_debug(17 downto 16) <= rx_k; stat_debug(19 downto 18) <= (others => '0'); stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0); stat_debug(41 downto 24) <= (others => '0'); -stat_debug(42) <= sysclk; -- CHANGED -stat_debug(43) <= sysclk; -- CHANGED +stat_debug(42) <= sysclk; +stat_debug(43) <= sysclk; stat_debug(59 downto 44) <= (others => '0'); -stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); --link_error(3 downto 0); +stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0); --stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits --stat_debug(4) <= buf_stat_debug(4); -- alignme diff --git a/trb_net_components.vhd b/trb_net_components.vhd index c0762b6..05198f8 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -913,7 +913,7 @@ package trb_net_components is - component trb_net16_med_ecp_sfp_8bit_4 is + component trb_net16_med_ecp_sfp_4 is generic( REVERSE_ORDER : integer range 0 to 1 := c_NO -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" @@ -954,8 +954,7 @@ package trb_net_components is - - component trb_net16_med_ecp_sfp_4 is + component trb_net16_med_ecp_sfp_4_gbe is generic( REVERSE_ORDER : integer range 0 to 1 := c_NO -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" @@ -996,42 +995,34 @@ package trb_net_components is - component trb_net16_med_ecp_sfp_4_gbe is - generic( - REVERSE_ORDER : integer range 0 to 1 := c_NO - -- USED_PORTS : std_logic-vector(3 downto 0) := "1111" - ); + + + component trb_net16_med_16_CC is port( - CLK : in std_logic; -- SerDes clock - SYSCLK : in std_logic; -- fabric clock - RESET : in std_logic; -- synchronous reset - CLEAR : in std_logic; -- asynchronous reset - CLK_EN : in std_logic; + CLK : in std_logic; + CLK_EN : in std_logic; + RESET : in std_logic; + --Internal Connection - MED_DATA_IN : in std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_IN : in std_logic_vector(3 downto 0); - MED_READ_OUT : out std_logic_vector(3 downto 0); - MED_DATA_OUT : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0); - MED_DATAREADY_OUT : out std_logic_vector(3 downto 0); - MED_READ_IN : in std_logic_vector(3 downto 0); - REFCLK2CORE_OUT : out std_logic; - --SFP Connection - SD_RXD_P_IN : in std_logic_vector(3 downto 0); - SD_RXD_N_IN : in std_logic_vector(3 downto 0); - SD_TXD_P_OUT : out std_logic_vector(3 downto 0); - SD_TXD_N_OUT : out std_logic_vector(3 downto 0); - SD_REFCLK_P_IN : in std_logic; - SD_REFCLK_N_IN : in std_logic; - SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); - SD_LOS_IN : in std_logic_vector(3 downto 0); - SD_TXDIS_OUT : out std_logic_vector(3 downto 0); - -- Status and control port - STAT_OP : out std_logic_vector (4*16-1 downto 0); - CTRL_OP : in std_logic_vector (4*16-1 downto 0); - STAT_DEBUG : out std_logic_vector (63 downto 0); - CTRL_DEBUG : in std_logic_vector (63 downto 0) + MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_IN : in std_logic; + MED_READ_OUT : out std_logic; + MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_DATAREADY_OUT : out std_logic; + MED_READ_IN : in std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + DATA_VALID_OUT : out std_logic; + DATA_CTRL_OUT : out std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + DATA_VALID_IN : in std_logic; + DATA_CTRL_IN : in std_logic; + + STAT_OP : out std_logic_vector(15 downto 0); + CTRL_OP : in std_logic_vector(15 downto 0); + STAT_DEBUG : out std_logic_vector(63 downto 0) ); end component; -- 2.43.0