From 7ed54b172b3893cd5f5262d9f60ae5a780636be5 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 9 May 2022 13:22:40 +0200 Subject: [PATCH] initial checkin --- pinout/basic_constraints.lpf | 37 +++ pinout/tomcat_prototype.lpf | 153 +++++++++++++ prototype/compile.pl | 1 + prototype/config.vhd | 117 ++++++++++ prototype/config_compile_frankfurt.pl | 25 +++ prototype/config_compile_gsi.pl | 23 ++ prototype/nodelist.txt | 8 + prototype/nodelist_frankfurt.txt | 13 ++ prototype/par.p2t | 65 ++++++ prototype/tomcat_template.lpf | 31 +++ prototype/tomcat_template.prj | 241 ++++++++++++++++++++ prototype/tomcat_template.vhd | 311 ++++++++++++++++++++++++++ 12 files changed, 1025 insertions(+) create mode 100644 pinout/basic_constraints.lpf create mode 100644 pinout/tomcat_prototype.lpf create mode 120000 prototype/compile.pl create mode 100644 prototype/config.vhd create mode 100644 prototype/config_compile_frankfurt.pl create mode 100644 prototype/config_compile_gsi.pl create mode 100644 prototype/nodelist.txt create mode 100644 prototype/nodelist_frankfurt.txt create mode 100644 prototype/par.p2t create mode 100644 prototype/tomcat_template.lpf create mode 100644 prototype/tomcat_template.prj create mode 100644 prototype/tomcat_template.vhd diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf new file mode 100644 index 0000000..31e3330 --- /dev/null +++ b/pinout/basic_constraints.lpf @@ -0,0 +1,37 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT "CLK_200" 200.000 MHz ; +FREQUENCY PORT "CLK_125" 125.000 MHz ; +FREQUENCY NET "clk_sys" 100.000 MHz ; + +#If these signals do not exist, somebody messed around with the design... +MULTICYCLE TO CELL "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio[*]" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; +GSR_NET NET "GSR_N"; + +BLOCK PATH TO CELL "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/inp_reg*"; +BLOCK PATH FROM CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/inp_verylong*"; +BLOCK PATH TO CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/out_reg*"; + +FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps +FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "SFP*"; +BLOCK PATH FROM PORT "SFP*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMPSENS"; +BLOCK PATH FROM PORT "TEMPSENS"; diff --git a/pinout/tomcat_prototype.lpf b/pinout/tomcat_prototype.lpf new file mode 100644 index 0000000..250a295 --- /dev/null +++ b/pinout/tomcat_prototype.lpf @@ -0,0 +1,153 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; + +SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; +BANK 0 VCCIO 2.5 V; +BANK 1 VCCIO 2.5 V; +BANK 2 VCCIO 2.5 V; +BANK 3 VCCIO 2.5 V; +BANK 6 VCCIO 3.3 V; +BANK 7 VCCIO 3.3 V; +BANK 8 VCCIO 3.3 V; + +################################################################# +# Clock I/O +################################################################# +LOCATE COMP "CLK_125" SITE "A4" ; +IOBUF PORT "CLK_125" IO_TYPE="LVDS" DIFFRESISTOR="100"; +LOCATE COMP "CLK_200" SITE "C18" ; +IOBUF PORT "CLK_200" IO_TYPE="LVDS" DIFFRESISTOR="100"; + +################################################################# +# SFP +################################################################# +LOCATE COMP "SFP_TX_DIS" SITE "N3"; +IOBUF PORT "SFP_TX_DIS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_LOS" SITE "N2"; +IOBUF PORT "SFP_LOS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_MOD_0" SITE "P1"; +IOBUF PORT "SFP_MOD_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_RATE_SEL" SITE "N1"; +IOBUF PORT "SFP_RATE_SEL" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_TX_FAULT" SITE "P2"; +IOBUF PORT "SFP_TX_FAULT" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_MOD_1" SITE "M1"; +IOBUF PORT "SFP_MOD_1" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "SFP_MOD_2" SITE "P3"; +IOBUF PORT "SFP_MOD_2" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +################################################################# +# Temperature, Flash & ID +################################################################# +LOCATE COMP "I2C_SDA" SITE "L2" ; +IOBUF PORT "I2C_SDA" IO_TYPE=LVCMOS33 ; +LOCATE COMP "I2C_SCL" SITE "L1" ; +IOBUF PORT "I2C_SCL" IO_TYPE=LVCMOS33 ; + +LOCATE COMP "PROGRAMN" SITE "V1"; +IOBUF PORT "PROGRAMN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8 ; + +LOCATE COMP "FLASH_HOLD" SITE "W1" ; +IOBUF PORT "FLASH_HOLD" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_MISO" SITE "V2" ; +IOBUF PORT "FLASH_MISO" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_MOSI" SITE "W2" ; +IOBUF PORT "FLASH_MOSI" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_NCS" SITE "R2" ; +IOBUF PORT "FLASH_NCS" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_SCLK" SITE "U2" ; +IOBUF PORT "FLASH_SCLK" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_WP" SITE "Y2" ; +IOBUF PORT "FLASH_WP" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_SELECT" SITE "T3" ; +IOBUF PORT "FLASH_SELECT" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "FLASH_OVERRIDE" SITE "U1" ; +IOBUF PORT "FLASH_OVERRIDE" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +################################################################# +# GPIO +################################################################# +LOCATE COMP "GPIO_15" SITE "A3" ; +IOBUF PORT "GPIO_15" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_14" SITE "B3" ; +IOBUF PORT "GPIO_14" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_13" SITE "A2" ; +IOBUF PORT "GPIO_13" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_12" SITE "B2" ; +IOBUF PORT "GPIO_12" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_11" SITE "B1" ; +IOBUF PORT "GPIO_11" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_10" SITE "C2" ; +IOBUF PORT "GPIO_10" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_9" SITE "C1" ; +IOBUF PORT "GPIO_9" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_8" SITE "D2" ; +IOBUF PORT "GPIO_8" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_7" SITE "D1" ; +IOBUF PORT "GPIO_7" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_6" SITE "E2" ; +IOBUF PORT "GPIO_6" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_5" SITE "E1" ; +IOBUF PORT "GPIO_5" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_4" SITE "F2" ; +IOBUF PORT "GPIO_4" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_3" SITE "F1" ; +IOBUF PORT "GPIO_3" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_2" SITE "G2" ; +IOBUF PORT "GPIO_2" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_1" SITE "G1" ; +IOBUF PORT "GPIO_1" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "GPIO_0" SITE "J4" ; +IOBUF PORT "GPIO_0" IO_TYPE=LVTTL33 PULLMODE=NONE ; +LOCATE COMP "TIMING_TEST" SITE "H1" ; +IOBUF PORT "TIMING_TEST" IO_TYPE=LVTTL33 PULLMODE=NONE ; + +################################################################# +# LVDS interface +################################################################# +LOCATE COMP "INTCOM_9" SITE "C18" ; +IOBUF PORT "INTCOM_9" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_8" SITE "D18" ; +IOBUF PORT "INTCOM_8" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_7" SITE "F17" ; +IOBUF PORT "INTCOM_7" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_6" SITE "H18" ; +IOBUF PORT "INTCOM_6" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_5" SITE "K16" ; +IOBUF PORT "INTCOM_5" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_4" SITE "C20" ; +IOBUF PORT "INTCOM_4" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_3" SITE "E20" ; +IOBUF PORT "INTCOM_3" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_2" SITE "G19" ; +IOBUF PORT "INTCOM_2" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_1" SITE "J19" ; +IOBUF PORT "INTCOM_1" IO_TYPE=LVDS DIFFRESISTOR=100; +LOCATE COMP "INTCOM_0" SITE "L20" ; +IOBUF PORT "INTCOM_0" IO_TYPE=LVDS DIFFRESISTOR=100; + +################################################################# +# LED +################################################################# +LOCATE COMP "LED_SFP_YELLOW" SITE "L3"; +IOBUF PORT "LED_SFP_YELLOW" IO_TYPE=LVTTL33 ; +LOCATE COMP "LED_SFP_GREEN" SITE "J3"; +IOBUF PORT "LED_SFP_GRENN" IO_TYPE=LVTTL33 ; +LOCATE COMP "LED_SFP_RED" SITE "K3"; +IOBUF PORT "LED_SFP_RED" IO_TYPE=LVTTL33 ; + +LOCATE COMP "LED_0" SITE "K1"; +IOBUF PORT "LED_0" IO_TYPE=LVCMOS33 DRIVE=8; +LOCATE COMP "LED_1" SITE "K2"; +IOBUF PORT "LED_1" IO_TYPE=LVCMOS33 DRIVE=8; +LOCATE COMP "LED_2" SITE "J1"; +IOBUF PORT "LED_2" IO_TYPE=LVCMOS33 DRIVE=8; +LOCATE COMP "LED_3" SITE "H2"; +IOBUF PORT "LED_3" IO_TYPE=LVCMOS33 DRIVE=8; + +################################################################# +################################################################# +#### OLD #### +################################################################# +################################################################# diff --git a/prototype/compile.pl b/prototype/compile.pl new file mode 120000 index 0000000..933ff60 --- /dev/null +++ b/prototype/compile.pl @@ -0,0 +1 @@ +../../trb3/scripts/compile.pl \ No newline at end of file diff --git a/prototype/config.vhd b/prototype/config.vhd new file mode 100644 index 0000000..79e7647 --- /dev/null +++ b/prototype/config.vhd @@ -0,0 +1,117 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ +--set to 0 for backplane serdes, set to 1 for SFP serdes + constant SERDES_NUM : integer := 1; + +--TDC settings + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size + -- mode: 0, 1, 2, 3, 7 + -- size: 32, 64, 96, 128, dyn + constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC + -- 0: Single fine time as the sum of the two transitions + -- 1: Double fine time, individual transitions + -- 13: Debug - fine time + (if 0x3ff full chain) + -- 14: Debug - single fine time and the ROM addresses for the two transitions + -- 15: Debug - complete carry chain dump + + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N + constant EVENT_MAX_SIZE : integer := 500; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2 + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F570"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"81"; + + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_NO; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + + constant FPGA_SIZE : string := "85KUM"; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := (others => x"00"); + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + type intlist_t is array(0 to 7) of integer; + type hw_info_t is array(0 to 7) of unsigned(31 downto 0); + constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1 + + t(7 downto 0) := std_logic_vector(to_unsigned(1,8)); + t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4)); + t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3)); + t(15) := '1'; --TDC + t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2)); + + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/prototype/config_compile_frankfurt.pl b/prototype/config_compile_frankfurt.pl new file mode 100644 index 0000000..a681cf6 --- /dev/null +++ b/prototype/config_compile_frankfurt.pl @@ -0,0 +1,25 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA756', +Speedgrade => '8', + + +TOPNAME => "trb5sc_template", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@jspc29", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', + +nodelist_file => '../nodelist_frankfurt.txt', +pinout_file => 'trb5sc_tdc', +par_options => '../par.p2t', + + +#Include only necessary lpf files +include_TDC => 1, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used diff --git a/prototype/config_compile_gsi.pl b/prototype/config_compile_gsi.pl new file mode 100644 index 0000000..cdfe689 --- /dev/null +++ b/prototype/config_compile_gsi.pl @@ -0,0 +1,23 @@ +Familyname => 'ECP5UM', +Devicename => 'LFE5UM-85F', +Package => 'CABGA381', +Speedgrade => '8', + +TOPNAME => "tomcat_template", +lm_license_file_for_synplify => "27000\@lxcad04.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.12', +synplify_path => '/opt/synplicity/R-2020.09-SP1', +synplify_command => "/opt/synplicity/R-2020.09-SP1/bin/synplify_premier", + +nodelist_file => '../nodelist.txt', +pinout_file => 'tomcat_prototype', +par_options => '../par.p2t', + +include_TDC => 0, +include_GBE => 0, + +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #must not be set for ECP5 + diff --git a/prototype/nodelist.txt b/prototype/nodelist.txt new file mode 100644 index 0000000..a99f562 --- /dev/null +++ b/prototype/nodelist.txt @@ -0,0 +1,8 @@ +// nodes file for parallel place&route + +[hades66] +system = linux +corenum = 24 +ENV = /home/compile/bin/diamond_env +workdir = /home/compile/vhdl/dirich/dirich/workdir + diff --git a/prototype/nodelist_frankfurt.txt b/prototype/nodelist_frankfurt.txt new file mode 100644 index 0000000..2e858da --- /dev/null +++ b/prototype/nodelist_frankfurt.txt @@ -0,0 +1,13 @@ +// nodes file for parallel place&route + +[jspc37] +SYSTEM = linux +CORENUM = 7 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir + +[jspc57] +SYSTEM = linux +CORENUM = 3 +ENV = /d/jspc29/lattice/310_settings.sh +WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir diff --git a/prototype/par.p2t b/prototype/par.p2t new file mode 100644 index 0000000..722b6fe --- /dev/null +++ b/prototype/par.p2t @@ -0,0 +1,65 @@ +-w +-l 5 +-s 10 +-t 11 # seed setting here! +-c 2 +-e 2 +-i 10 +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 +#General PAR Command Line Options +# -w With this option, any files generated will overwrite existing files +# (e.g., any .par, .pad files). +# -y Adds the Delay Summary Report in the .par file and creates the delay +# file (in .dly format) at the end of the par run. +# +#PAR Placement Command Line Options +# -l Specifies the effort level of the design from 1 (simplest designs) +# to 5 (most complex designs). +# -m Multi-tasking option. Controlled by the compile.pl script. +# -n Sets the number of iterations performed at the effort level +# specified by the -l option. Controlled by the compile.pl script. +# -s Save the number of best results for this run. +# -t Start placement at the specified cost table. Default is 1. +# +#PAR Routing Command Line Options +# -c Run number of cost-based cleanup passes of the router. +# -e Run number of delay-based cleanup passes of the router on +# completely-routed designs only. +# -i Run a maximum number of passes, stopping earlier only if the routing +# goes to 100 percent completion and all constraints are met. +# +#PAR Explorer Command Line Options +# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is +# compatible with all Lattice FPGA device families; however, most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families. +# parCDR Enable the congestion-driven router (CDR) algorithm. +# Congestion-driven options like parCDR and parCDP can improve +# performance given a design with multiple congestion “hotspots.” The +# Layer > Congestion option of the Design Planner Floorplan View can +# help visualize routing congestion. Large congested areas may prevent +# the options from finding a successful solution. +# CDR is compatible with all Lattice FPGA device families however most +# benefit has been demonstrated with benchmarks targeted to ECP5, +# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families. +# paruseNBR NBR Router or Negotiation-based routing option. Supports all +# FPGA device families except LatticeXP and MachXO. +# When turned on, an alternate routing engine from the traditional +# Rip-up-based routing selection (RBR) is used. This involves an +# iterative routing algorithm that routes connections to achieve +# minimum delay cost. It does so by computing the demand on each +# routing resource and applying cost values per node. It will +# complete when an optimal solution is arrived at or the number of +# iterations is reached. +# parPathBased Path-based placement option. Path-based timing driven +# placement will yield better performance and more +# predictable results in many cases. +# parHold Additional hold time correction option. This option +# forces the router to automatically insert extra wires to compensate for the +# hold time violation. +# parHoldLimit This option allows you to set a limit on the number of +# hold time violations to be processed by the auto hold time correction option +# parHold. +# parPlcInLimit Cannot find in the online help +# parPlcInNeighborSize Cannot find in the online help + diff --git a/prototype/tomcat_template.lpf b/prototype/tomcat_template.lpf new file mode 100644 index 0000000..a7c086c --- /dev/null +++ b/prototype/tomcat_template.lpf @@ -0,0 +1,31 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +FREQUENCY PORT CLK_200 200 MHz; +FREQUENCY PORT CLK_125 125 MHz; + +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; +FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz; + +FREQUENCY NET "med2int_0.clk_full" 200 MHz; + +BLOCK PATH TO PORT "LED*"; +BLOCK PATH TO PORT "PROGRAMN"; +BLOCK PATH TO PORT "TEMP_LINE"; +BLOCK PATH FROM PORT "TEMP_LINE"; +BLOCK PATH TO PORT "TEST_LINE*"; + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; + +GSR_NET NET "clear_i"; + +REGION "MEDIA" "R81C44D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ; + diff --git a/prototype/tomcat_template.prj b/prototype/tomcat_template.prj new file mode 100644 index 0000000..5da9436 --- /dev/null +++ b/prototype/tomcat_template.prj @@ -0,0 +1,241 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology ECP5UM +set_option -part LFE5UM_85F +set_option -package BG381C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "tomcat_template" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -forcegsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true +set_option -multi_file_compilation_unit 1 + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/tomcat_template.edf" +set_option log_file "workdir/tomcat_project.srf" +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + +add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd" + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "tdc_release/tdc_version.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +#add_file -vhdl -lib work "../../dirich/code/sedcheck.vhd" +add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd" +#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v" + +#channel 1, SFP +#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd" +#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v" +########################################## + + +######################################### +#channel 0, backplane +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0/serdes_sync_0.vhd" + +#channel 1, SFP +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" +########################################## + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" + +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" + +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + +add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd" + + +add_file -vhdl -lib work "tdc_release/tdc_components.vhd" +add_file -vhdl -lib work "tdc_release/bit_sync.vhd" +add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" +add_file -vhdl -lib work "tdc_release/Channel_200.vhd" +add_file -vhdl -lib work "tdc_release/Channel.vhd" +add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" +add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/hit_mux.vhd" +add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" +add_file -vhdl -lib work "tdc_release/Readout_record.vhd" +add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" +add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" +add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd" +add_file -vhdl -lib work "tdc_release/Stretcher.vhd" +add_file -vhdl -lib work "tdc_release/TDC_record.vhd" +add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd" +add_file -vhdl -lib work "tdc_release/up_counter.vhd" + +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/TDC/Adder_288/Adder_288.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_DynThr_OutReg/FIFO_DC_36x128_DynThr_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x128_OutReg/FIFO_DC_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x64_OutReg/FIFO_DC_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FIFO_DC_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" + +add_file -vhdl -lib work "./tomcat_template.vhd" diff --git a/prototype/tomcat_template.vhd b/prototype/tomcat_template.vhd new file mode 100644 index 0000000..dfcdee4 --- /dev/null +++ b/prototype/tomcat_template.vhd @@ -0,0 +1,311 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.med_sync_define.all; + +entity tomcat_template is + port( + -- clock oscillators + CLK_200 : in std_logic; + CLK_125 : in std_logic; + -- SFP signals + SFP_TX_DIS : out std_logic; + SFP_LOS : in std_logic; + SFP_RATESEL : out std_logic; + SFP_MOD_0 : in std_logic; -- detect + SFP_MOD_1 : inout std_logic; -- SCL + SFP_MOD_2 : inout std_logic; -- SDA + -- Flash, Reload + FLASH_SCLK : out std_logic; + FLASH_NCS : out std_logic; + FLASH_MOSI : out std_logic; + FLASH_MISO : in std_logic; + FLASH_HOLD : out std_logic; + FLASH_WP : out std_logic; + FLASH_SELECT : in std_logic; + FLASH_OVERRIDE : out std_logic; + PROGRAMN : out std_logic; + -- I2C (temperature, UID) + I2C_SDA : inout std_logic; + I2C_SCL : inout std_logic; + -- LEDs + LED : out std_logic_vector(3 downto 0); + LED_SFP_YELLOW : out std_logic; + LED_SFP_GREEN : out std_logic; + LED_SFP_RED : out std_logic; + -- LVDS intercom + INTCOM : inout std_logic_vector(9 downto 0); + -- GPIO + GPIO : out std_logic_vector(15 downto 0) + ); + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_NCS : signal is true; + attribute syn_useioff of FLASH_SCLK : signal is true; + attribute syn_useioff of FLASH_MOSI : signal is true; + attribute syn_useioff of FLASH_MISO : signal is true; + +end entity; + +architecture arch of tomcat_template is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys : std_logic; + signal clk_full : std_logic; + signal clk_full_osc : std_logic; + signal clk_cal : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal trigger_in_i : std_logic; + + signal debug_clock_reset : std_logic_vector(31 downto 0); + signal debug_tools : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 0); + signal int2med : int2med_array_t(0 to 0); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + signal sfp_los_i : std_logic; + signal sfp_txdis_i : std_logic; + signal sfp_prsnt_i : std_logic; + + signal readout_rx : READOUT_RX; + signal readout_tx : readout_tx_array_t(0 to 0); + + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out : CTRLBUS_RX; + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal bus_master_active : std_logic; + + signal timer : TIMERS; + signal led_off : std_logic; + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + + signal link_stat_in_reg : std_logic; + +begin + +trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger" + +------------------------------------------------------------------------------- +-- Clock & Reset Handling +------------------------------------------------------------------------------- + THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + CLOCK_IN => CLK_200, + RESET_FROM_NET => med2int(0).stat_op(13), + SEND_RESET_IN => med2int(0).stat_op(15), + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + REF_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + RAW_CLK_OUT => clk_full_osc, + DEBUG_OUT => debug_clock_reset + ); + + THE_CAL_PLL : entity work.pll_in125_out50 + port map( + CLKI => CLK_125, + CLKOP => clk_cal + ); + +------------------------------------------------------------------------------- +-- TrbNet Uplink +------------------------------------------------------------------------------- + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + --SFP Connection + SD_PRSNT_N_IN => sfp_prsnt_i, + SD_LOS_IN => sfp_los_i, + SD_TXDIS_OUT => sfp_txdis_i, + --Control Interface + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + + sfp_los_i <= SFP_LOS; + sfp_prsnt_i <= SFP_MOD_0; + SFP_TX_DIS <= sfp_txdis_i; + +------------------------------------------------------------------------------- +-- Endpoint +------------------------------------------------------------------------------- + THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record + generic map ( + ADDRESS_MASK => x"FFFF", + BROADCAST_BITMASK => x"FF", + REGIO_INIT_ENDPOINT_ID => x"0001", + REGIO_USE_1WIRE_INTERFACE => c_I2C, + TIMING_TRIGGER_RAW => c_YES, + --Configure data handler + DATA_INTERFACE_NUMBER => 1, + DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE, + DATA_BUFFER_WIDTH => 32, + DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE, + TRG_RELEASE_AFTER_DATA => c_YES, + HEADER_BUFFER_DEPTH => 9, + HEADER_BUFFER_FULL_THRESH => 2**9-16 + ) + port map( + -- Misc + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + -- Media direction port + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + --Timing trigger in + TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i, + -- readout + READOUT_RX => readout_rx, + READOUT_TX => readout_tx, + --Slow Control Port + REGIO_COMMON_STAT_REG_IN => common_stat_reg, + REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, + BUS_RX => ctrlbus_rx, + BUS_TX => ctrlbus_tx, + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + --UniqueID + ONEWIRE_INOUT => open, + I2C_SCL => I2C_SCL, + I2C_SDA => I2C_SDA, + --Timing registers + TIMERS_OUT => timer + ); + +------------------------------------------------------------------------------- +-- Bus Handler +------------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + REGIO_RX => ctrlbus_rx, + REGIO_TX => ctrlbus_tx, + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, + STAT_DEBUG => open + ); + +------------------------------------------------------------------------------- +-- Control Tools +------------------------------------------------------------------------------- + THE_TOOLS : entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + --Flash & Reload + FLASH_CS => FLASH_NCS, + FLASH_CLK => FLASH_SCLK, + FLASH_IN => FLASH_MISO, + FLASH_OUT => FLASH_MOSI, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => open, + SPI_MOSI_OUT => open, + SPI_MISO_IN => (others => '0'), + SPI_CLK_OUT => open, + --Header + HEADER_IO => open, + ADDITIONAL_REG(0) => led_off, + --LCD + LCD_DATA_IN => (others => '0'), + --ADC + ADC_CS => open, + ADC_MOSI => open, + ADC_MISO => '0', + ADC_CLK => open, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS(1 downto 0) => open, + TRIG_GEN_OUTPUTS(3 downto 2) => open, + --SED + SED_ERROR_OUT => open, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => bus_master_in, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => debug_tools + ); + + FLASH_HOLD <= '1'; + FLASH_WP <= '1'; + FLASH_OVERRIDE <= 'Z'; + +------------------------------------------------------------------------------- +-- I/O +------------------------------------------------------------------------------- + +------------------------------------------------------------------------------- +-- LED +------------------------------------------------------------------------------- + LED_SFP_GREEN <= not med2int(0).stat_op(9) or led_off; + LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off; + LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off; + LED <= (others => '0'); + +------------------------------------------------------------------------------- +-- No trigger/data endpoint included +------------------------------------------------------------------------------- + readout_tx(0).data_finished <= '1'; + readout_tx(0).data_write <= '0'; + readout_tx(0).busy_release <= '1'; + +end architecture; + + + -- 2.43.0